2006_APP/logic/db/test_uart.hier_info

|test_uart
GPIO1_0 <= GPIO1_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_1 <= GPIO1_1.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_2 <= GPIO1_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_3 <= GPIO1_3.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_4 <= GPIO1_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_5 <= GPIO1_5.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_6 <= GPIO1_6.DB_MAX_OUTPUT_PORT_TYPE
GPIO1_7 <= GPIO1_7.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_0 <= GPIO2_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_1 <= GPIO2_1.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_2 <= GPIO2_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_3 <= GPIO2_3.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_4 <= GPIO2_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_5 <= GPIO2_5.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_6 <= GPIO2_6.DB_MAX_OUTPUT_PORT_TYPE
GPIO2_7 <= GPIO2_7.DB_MAX_OUTPUT_PORT_TYPE
GPIO3_0 => gpio3_io_in[0].DATAIN
GPIO3_1 => gpio3_io_in[1].DATAIN
GPIO3_2 => gpio3_io_in[2].DATAIN
GPIO3_3 => gpio3_io_in[3].DATAIN
GPIO3_4 => gpio3_io_in[4].DATAIN
GPIO6_0 <= GPIO6_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO6_2 <= GPIO6_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO6_4 <= GPIO6_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO6_6 <> GPIO6_6
GPIO9_0 <= GPIO9_0.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_1 <> GPIO9_1
GPIO9_2 <= GPIO9_2.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_3 <= GPIO9_3.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_4 <= GPIO9_4.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_5 <= GPIO9_5.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_6 <= GPIO9_6.DB_MAX_OUTPUT_PORT_TYPE
GPIO9_7 <= GPIO9_7.DB_MAX_OUTPUT_PORT_TYPE
PIN_HSE => PIN_HSE_in.IN2
PIN_HSI => PIN_HSI_in.IN1
PIN_OSC => ~NO_FANOUT~
SIM_CLK <= multi_uart_ip:macro_inst.SIM_CLK
SIM_IO[0] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[1] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[2] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[3] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[4] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[5] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[6] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[7] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[8] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[9] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[10] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO[11] <> multi_uart_ip:macro_inst.SIM_IO
SIM_IO_12 <> multi_uart_ip:macro_inst.SIM_IO_12
SIM_IO_13 <> multi_uart_ip:macro_inst.SIM_IO_13
SIM_IO_15 <> multi_uart_ip:macro_inst.SIM_IO_15
UART3_UARTRXD => gpio6_io_in[7].DATAIN
UART3_UARTTXD <= UART3_UARTTXD.DB_MAX_OUTPUT_PORT_TYPE
UART4_UARTRXD => gpio7_io_in[1].DATAIN
UART4_UARTTXD <= UART4_UARTTXD.DB_MAX_OUTPUT_PORT_TYPE
uart15_rx => uart15_rx.IN1
uart15_tx <= multi_uart_ip:macro_inst.uart15_tx


|test_uart|altpll:pll_inst
inclk[0] => altpll_9g32:auto_generated.inclk[0]
inclk[1] => altpll_9g32:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => altpll_9g32:auto_generated.areset
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <> <GND>
clk[0] <= clk[0].DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1].DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2].DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3].DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4].DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= altpll_9g32:auto_generated.locked
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>
fref <= <GND>
icdrclk <= <GND>


|test_uart|altpll:pll_inst|altpll_9g32:auto_generated
areset => pll_lock_sync.IN0
areset => pll1.ARESET
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
locked <= locked.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|alta_gclksw:gclksw_inst
resetn => ~NO_FANOUT~
ena => gclk_switch.ENA
clkin0 => gclk_switch.INCLK
clkin1 => ~NO_FANOUT~
clkin2 => gclk_switch.INCLK2
clkin3 => gclk_switch.INCLK3
select[0] => gclk_switch.CLKSELECT
select[1] => gclk_switch.CLKSELECT1
clkout <= gclk_switch.CLK


|test_uart|multi_uart_ip:macro_inst
SIM_CLK <= sim_clk_reg.DB_MAX_OUTPUT_PORT_TYPE
SIM_IO[0] <> SIM_IO[0]
SIM_IO[1] <> SIM_IO[1]
SIM_IO[2] <> SIM_IO[2]
SIM_IO[3] <> SIM_IO[3]
SIM_IO[4] <> SIM_IO[4]
SIM_IO[5] <> SIM_IO[5]
SIM_IO[6] <> SIM_IO[6]
SIM_IO[7] <> SIM_IO[7]
SIM_IO[8] <> SIM_IO[8]
SIM_IO[9] <> SIM_IO[9]
SIM_IO[10] <> SIM_IO[10]
SIM_IO[11] <> SIM_IO[11]
SIM_IO_12 <> SIM_IO_12
SIM_IO_13 <> SIM_IO_13
SIM_IO_15 <> SIM_IO_15
uart15_rx => rxd_15_ip_in.DATAA
uart15_tx <= uart15_tx.DB_MAX_OUTPUT_PORT_TYPE
ext_int_in[0] <= <GND>
ext_int_in[1] <= <GND>
ext_int_in[2] <= <GND>
ext_int_in[3] <= <GND>
gpio_int_g0_in[0] <= multi_uart:u_uart[0].interrupts[0]
gpio_int_g0_in[1] <= multi_uart:u_uart[0].interrupts[1]
gpio_int_g0_in[2] <= multi_uart:u_uart[0].interrupts[2]
gpio_int_g0_in[3] <= multi_uart:u_uart[0].interrupts[3]
gpio_int_g0_in[4] <= multi_uart:u_uart[0].interrupts[4]
gpio_int_g0_in[5] <= multi_uart:u_uart[0].interrupts[5]
gpio_int_g1_in[0] <= multi_uart:u_uart[1].interrupts[0]
gpio_int_g1_in[1] <= multi_uart:u_uart[1].interrupts[1]
gpio_int_g1_in[2] <= multi_uart:u_uart[1].interrupts[2]
gpio_int_g1_in[3] <= multi_uart:u_uart[1].interrupts[3]
gpio_int_g1_in[4] <= multi_uart:u_uart[1].interrupts[4]
gpio_int_g1_in[5] <= multi_uart:u_uart[1].interrupts[5]
rxd_12_ip_in <= rxd_12_ip_in.DB_MAX_OUTPUT_PORT_TYPE
rxd_13_ip_in <= rxd_13_ip_in.DB_MAX_OUTPUT_PORT_TYPE
rxd_14_ip_in <= <GND>
rxd_15_ip_in <= rxd_15_ip_in.DB_MAX_OUTPUT_PORT_TYPE
txd_12_ip_out_data => SIM_IO_12.DATAIN
txd_12_ip_out_en => SIM_IO_12.IN1
txd_13_ip_out_data => SIM_IO_13.DATAIN
txd_13_ip_out_en => SIM_IO_13.IN1
txd_14_ip_out_data => ~NO_FANOUT~
txd_14_ip_out_en => ~NO_FANOUT~
txd_15_ip_out_data => uart15_tx.DATAIN
txd_15_ip_out_data => SIM_IO_15.DATAIN
txd_15_ip_out_en => SIM_IO_15.IN1
txen_12_ip_out_data => SIM_IO_12.IN0
txen_12_ip_out_en => SIM_IO_12.IN1
txen_13_ip_out_data => SIM_IO_13.IN0
txen_13_ip_out_en => SIM_IO_13.IN1
txen_14_ip_out_data => ~NO_FANOUT~
txen_14_ip_out_en => ~NO_FANOUT~
txen_15_ip_out_data => SIM_IO_15.IN0
txen_15_ip_out_data => rxd_15_ip_in.IN0
txen_15_ip_out_en => SIM_IO_15.IN1
txen_15_ip_out_en => rxd_15_ip_in.OUTPUTSELECT
txen_15_ip_out_en => uart15_tx.OE
txen_15_ip_out_en => rxd_15_ip_in.IN1
sys_clock => sys_clock.IN1
bus_clock => bus_clock.IN2
resetn => resetn.IN1
stop => ~NO_FANOUT~
mem_ahb_htrans[0] => mem_ahb_htrans[0].IN1
mem_ahb_htrans[1] => mem_ahb_htrans[1].IN1
mem_ahb_hready => mem_ahb_hready.IN1
mem_ahb_hwrite => mem_ahb_hwrite.IN1
mem_ahb_haddr[0] => mem_ahb_haddr[0].IN1
mem_ahb_haddr[1] => mem_ahb_haddr[1].IN1
mem_ahb_haddr[2] => mem_ahb_haddr[2].IN1
mem_ahb_haddr[3] => mem_ahb_haddr[3].IN1
mem_ahb_haddr[4] => mem_ahb_haddr[4].IN1
mem_ahb_haddr[5] => mem_ahb_haddr[5].IN1
mem_ahb_haddr[6] => mem_ahb_haddr[6].IN1
mem_ahb_haddr[7] => mem_ahb_haddr[7].IN1
mem_ahb_haddr[8] => mem_ahb_haddr[8].IN1
mem_ahb_haddr[9] => mem_ahb_haddr[9].IN1
mem_ahb_haddr[10] => mem_ahb_haddr[10].IN1
mem_ahb_haddr[11] => mem_ahb_haddr[11].IN1
mem_ahb_haddr[12] => mem_ahb_haddr[12].IN1
mem_ahb_haddr[13] => ~NO_FANOUT~
mem_ahb_haddr[14] => ~NO_FANOUT~
mem_ahb_haddr[15] => ~NO_FANOUT~
mem_ahb_haddr[16] => ~NO_FANOUT~
mem_ahb_haddr[17] => ~NO_FANOUT~
mem_ahb_haddr[18] => ~NO_FANOUT~
mem_ahb_haddr[19] => ~NO_FANOUT~
mem_ahb_haddr[20] => ~NO_FANOUT~
mem_ahb_haddr[21] => ~NO_FANOUT~
mem_ahb_haddr[22] => ~NO_FANOUT~
mem_ahb_haddr[23] => ~NO_FANOUT~
mem_ahb_haddr[24] => ~NO_FANOUT~
mem_ahb_haddr[25] => ~NO_FANOUT~
mem_ahb_haddr[26] => ~NO_FANOUT~
mem_ahb_haddr[27] => ~NO_FANOUT~
mem_ahb_haddr[28] => ~NO_FANOUT~
mem_ahb_haddr[29] => ~NO_FANOUT~
mem_ahb_haddr[30] => ~NO_FANOUT~
mem_ahb_haddr[31] => ~NO_FANOUT~
mem_ahb_hsize[0] => mem_ahb_hsize[0].IN1
mem_ahb_hsize[1] => mem_ahb_hsize[1].IN1
mem_ahb_hsize[2] => mem_ahb_hsize[2].IN1
mem_ahb_hburst[0] => mem_ahb_hburst[0].IN1
mem_ahb_hburst[1] => mem_ahb_hburst[1].IN1
mem_ahb_hburst[2] => mem_ahb_hburst[2].IN1
mem_ahb_hwdata[0] => mem_ahb_hwdata[0].IN1
mem_ahb_hwdata[1] => mem_ahb_hwdata[1].IN1
mem_ahb_hwdata[2] => mem_ahb_hwdata[2].IN1
mem_ahb_hwdata[3] => mem_ahb_hwdata[3].IN1
mem_ahb_hwdata[4] => mem_ahb_hwdata[4].IN1
mem_ahb_hwdata[5] => mem_ahb_hwdata[5].IN1
mem_ahb_hwdata[6] => mem_ahb_hwdata[6].IN1
mem_ahb_hwdata[7] => mem_ahb_hwdata[7].IN1
mem_ahb_hwdata[8] => mem_ahb_hwdata[8].IN1
mem_ahb_hwdata[9] => mem_ahb_hwdata[9].IN1
mem_ahb_hwdata[10] => mem_ahb_hwdata[10].IN1
mem_ahb_hwdata[11] => mem_ahb_hwdata[11].IN1
mem_ahb_hwdata[12] => mem_ahb_hwdata[12].IN1
mem_ahb_hwdata[13] => mem_ahb_hwdata[13].IN1
mem_ahb_hwdata[14] => mem_ahb_hwdata[14].IN1
mem_ahb_hwdata[15] => mem_ahb_hwdata[15].IN1
mem_ahb_hwdata[16] => mem_ahb_hwdata[16].IN1
mem_ahb_hwdata[17] => mem_ahb_hwdata[17].IN1
mem_ahb_hwdata[18] => mem_ahb_hwdata[18].IN1
mem_ahb_hwdata[19] => mem_ahb_hwdata[19].IN1
mem_ahb_hwdata[20] => mem_ahb_hwdata[20].IN1
mem_ahb_hwdata[21] => mem_ahb_hwdata[21].IN1
mem_ahb_hwdata[22] => mem_ahb_hwdata[22].IN1
mem_ahb_hwdata[23] => mem_ahb_hwdata[23].IN1
mem_ahb_hwdata[24] => mem_ahb_hwdata[24].IN1
mem_ahb_hwdata[25] => mem_ahb_hwdata[25].IN1
mem_ahb_hwdata[26] => mem_ahb_hwdata[26].IN1
mem_ahb_hwdata[27] => mem_ahb_hwdata[27].IN1
mem_ahb_hwdata[28] => mem_ahb_hwdata[28].IN1
mem_ahb_hwdata[29] => mem_ahb_hwdata[29].IN1
mem_ahb_hwdata[30] => mem_ahb_hwdata[30].IN1
mem_ahb_hwdata[31] => mem_ahb_hwdata[31].IN1
mem_ahb_hreadyout <= ahb2apb:u_ahb2apb.ahb_hreadyout
mem_ahb_hresp <= ahb2apb:u_ahb2apb.ahb_hresp
mem_ahb_hrdata[0] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[1] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[2] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[3] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[4] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[5] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[6] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[7] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[8] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[9] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[10] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[11] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[12] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[13] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[14] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[15] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[16] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[17] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[18] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[19] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[20] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[21] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[22] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[23] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[24] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[25] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[26] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[27] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[28] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[29] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[30] <= ahb2apb:u_ahb2apb.ahb_hrdata
mem_ahb_hrdata[31] <= ahb2apb:u_ahb2apb.ahb_hrdata
slave_ahb_hsel <= <GND>
slave_ahb_hready <= <VCC>
slave_ahb_hreadyout => ~NO_FANOUT~
slave_ahb_htrans[0] <= <GND>
slave_ahb_htrans[1] <= <GND>
slave_ahb_hsize[0] <= <GND>
slave_ahb_hsize[1] <= <GND>
slave_ahb_hsize[2] <= <GND>
slave_ahb_hburst[0] <= <GND>
slave_ahb_hburst[1] <= <GND>
slave_ahb_hburst[2] <= <GND>
slave_ahb_hwrite <= <GND>
slave_ahb_haddr[0] <= <GND>
slave_ahb_haddr[1] <= <GND>
slave_ahb_haddr[2] <= <GND>
slave_ahb_haddr[3] <= <GND>
slave_ahb_haddr[4] <= <GND>
slave_ahb_haddr[5] <= <GND>
slave_ahb_haddr[6] <= <GND>
slave_ahb_haddr[7] <= <GND>
slave_ahb_haddr[8] <= <GND>
slave_ahb_haddr[9] <= <GND>
slave_ahb_haddr[10] <= <GND>
slave_ahb_haddr[11] <= <GND>
slave_ahb_haddr[12] <= <GND>
slave_ahb_haddr[13] <= <GND>
slave_ahb_haddr[14] <= <GND>
slave_ahb_haddr[15] <= <GND>
slave_ahb_haddr[16] <= <GND>
slave_ahb_haddr[17] <= <GND>
slave_ahb_haddr[18] <= <GND>
slave_ahb_haddr[19] <= <GND>
slave_ahb_haddr[20] <= <GND>
slave_ahb_haddr[21] <= <GND>
slave_ahb_haddr[22] <= <GND>
slave_ahb_haddr[23] <= <GND>
slave_ahb_haddr[24] <= <GND>
slave_ahb_haddr[25] <= <GND>
slave_ahb_haddr[26] <= <GND>
slave_ahb_haddr[27] <= <GND>
slave_ahb_haddr[28] <= <GND>
slave_ahb_haddr[29] <= <GND>
slave_ahb_haddr[30] <= <GND>
slave_ahb_haddr[31] <= <GND>
slave_ahb_hwdata[0] <= <GND>
slave_ahb_hwdata[1] <= <GND>
slave_ahb_hwdata[2] <= <GND>
slave_ahb_hwdata[3] <= <GND>
slave_ahb_hwdata[4] <= <GND>
slave_ahb_hwdata[5] <= <GND>
slave_ahb_hwdata[6] <= <GND>
slave_ahb_hwdata[7] <= <GND>
slave_ahb_hwdata[8] <= <GND>
slave_ahb_hwdata[9] <= <GND>
slave_ahb_hwdata[10] <= <GND>
slave_ahb_hwdata[11] <= <GND>
slave_ahb_hwdata[12] <= <GND>
slave_ahb_hwdata[13] <= <GND>
slave_ahb_hwdata[14] <= <GND>
slave_ahb_hwdata[15] <= <GND>
slave_ahb_hwdata[16] <= <GND>
slave_ahb_hwdata[17] <= <GND>
slave_ahb_hwdata[18] <= <GND>
slave_ahb_hwdata[19] <= <GND>
slave_ahb_hwdata[20] <= <GND>
slave_ahb_hwdata[21] <= <GND>
slave_ahb_hwdata[22] <= <GND>
slave_ahb_hwdata[23] <= <GND>
slave_ahb_hwdata[24] <= <GND>
slave_ahb_hwdata[25] <= <GND>
slave_ahb_hwdata[26] <= <GND>
slave_ahb_hwdata[27] <= <GND>
slave_ahb_hwdata[28] <= <GND>
slave_ahb_hwdata[29] <= <GND>
slave_ahb_hwdata[30] <= <GND>
slave_ahb_hwdata[31] <= <GND>
slave_ahb_hresp => ~NO_FANOUT~
slave_ahb_hrdata[0] => ~NO_FANOUT~
slave_ahb_hrdata[1] => ~NO_FANOUT~
slave_ahb_hrdata[2] => ~NO_FANOUT~
slave_ahb_hrdata[3] => ~NO_FANOUT~
slave_ahb_hrdata[4] => ~NO_FANOUT~
slave_ahb_hrdata[5] => ~NO_FANOUT~
slave_ahb_hrdata[6] => ~NO_FANOUT~
slave_ahb_hrdata[7] => ~NO_FANOUT~
slave_ahb_hrdata[8] => ~NO_FANOUT~
slave_ahb_hrdata[9] => ~NO_FANOUT~
slave_ahb_hrdata[10] => ~NO_FANOUT~
slave_ahb_hrdata[11] => ~NO_FANOUT~
slave_ahb_hrdata[12] => ~NO_FANOUT~
slave_ahb_hrdata[13] => ~NO_FANOUT~
slave_ahb_hrdata[14] => ~NO_FANOUT~
slave_ahb_hrdata[15] => ~NO_FANOUT~
slave_ahb_hrdata[16] => ~NO_FANOUT~
slave_ahb_hrdata[17] => ~NO_FANOUT~
slave_ahb_hrdata[18] => ~NO_FANOUT~
slave_ahb_hrdata[19] => ~NO_FANOUT~
slave_ahb_hrdata[20] => ~NO_FANOUT~
slave_ahb_hrdata[21] => ~NO_FANOUT~
slave_ahb_hrdata[22] => ~NO_FANOUT~
slave_ahb_hrdata[23] => ~NO_FANOUT~
slave_ahb_hrdata[24] => ~NO_FANOUT~
slave_ahb_hrdata[25] => ~NO_FANOUT~
slave_ahb_hrdata[26] => ~NO_FANOUT~
slave_ahb_hrdata[27] => ~NO_FANOUT~
slave_ahb_hrdata[28] => ~NO_FANOUT~
slave_ahb_hrdata[29] => ~NO_FANOUT~
slave_ahb_hrdata[30] => ~NO_FANOUT~
slave_ahb_hrdata[31] => ~NO_FANOUT~
ext_dma_DMACBREQ[0] <= multi_uart:u_uart[0].rx_dma_req[0]
ext_dma_DMACBREQ[1] <= multi_uart:u_uart[0].rx_dma_req[1]
ext_dma_DMACBREQ[2] <= multi_uart:u_uart[0].tx_dma_req[0]
ext_dma_DMACBREQ[3] <= multi_uart:u_uart[0].tx_dma_req[1]
ext_dma_DMACLBREQ[0] <= <GND>
ext_dma_DMACLBREQ[1] <= <GND>
ext_dma_DMACLBREQ[2] <= <GND>
ext_dma_DMACLBREQ[3] <= <GND>
ext_dma_DMACSREQ[0] <= <GND>
ext_dma_DMACSREQ[1] <= <GND>
ext_dma_DMACSREQ[2] <= <GND>
ext_dma_DMACSREQ[3] <= <GND>
ext_dma_DMACLSREQ[0] <= <GND>
ext_dma_DMACLSREQ[1] <= <GND>
ext_dma_DMACLSREQ[2] <= <GND>
ext_dma_DMACLSREQ[3] <= <GND>
ext_dma_DMACCLR[0] => multi_uart:u_uart[0].rx_dma_clr[0]
ext_dma_DMACCLR[1] => multi_uart:u_uart[0].rx_dma_clr[1]
ext_dma_DMACCLR[2] => multi_uart:u_uart[0].tx_dma_clr[0]
ext_dma_DMACCLR[3] => multi_uart:u_uart[0].tx_dma_clr[1]
ext_dma_DMACTC[0] => ~NO_FANOUT~
ext_dma_DMACTC[1] => ~NO_FANOUT~
ext_dma_DMACTC[2] => ~NO_FANOUT~
ext_dma_DMACTC[3] => ~NO_FANOUT~
local_int[0] <= <GND>
local_int[1] <= <GND>
local_int[2] <= <GND>
local_int[3] <= <GND>


|test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb
reset => hresp.ACLR
reset => prdata[0].ACLR
reset => prdata[1].ACLR
reset => prdata[2].ACLR
reset => prdata[3].ACLR
reset => prdata[4].ACLR
reset => prdata[5].ACLR
reset => prdata[6].ACLR
reset => prdata[7].ACLR
reset => prdata[8].ACLR
reset => prdata[9].ACLR
reset => prdata[10].ACLR
reset => prdata[11].ACLR
reset => prdata[12].ACLR
reset => prdata[13].ACLR
reset => prdata[14].ACLR
reset => prdata[15].ACLR
reset => prdata[16].ACLR
reset => prdata[17].ACLR
reset => prdata[18].ACLR
reset => prdata[19].ACLR
reset => prdata[20].ACLR
reset => prdata[21].ACLR
reset => prdata[22].ACLR
reset => prdata[23].ACLR
reset => prdata[24].ACLR
reset => prdata[25].ACLR
reset => prdata[26].ACLR
reset => prdata[27].ACLR
reset => prdata[28].ACLR
reset => prdata[29].ACLR
reset => prdata[30].ACLR
reset => prdata[31].ACLR
reset => pstrb[0].ACLR
reset => pstrb[1].ACLR
reset => pstrb[2].ACLR
reset => pstrb[3].ACLR
reset => paddr[0].ACLR
reset => paddr[1].ACLR
reset => paddr[2].ACLR
reset => paddr[3].ACLR
reset => paddr[4].ACLR
reset => paddr[5].ACLR
reset => paddr[6].ACLR
reset => paddr[7].ACLR
reset => paddr[8].ACLR
reset => paddr[9].ACLR
reset => paddr[10].ACLR
reset => paddr[11].ACLR
reset => paddr[12].ACLR
reset => pwrite.ACLR
reset => penable.ACLR
reset => psel.ACLR
reset => pdone.ACLR
reset => pvalid.ACLR
reset => hdone.PRESET
reset => hsize[0].ACLR
reset => hsize[1].ACLR
reset => hsize[2].ACLR
reset => hwrite.ACLR
reset => haddr[0].ACLR
reset => haddr[1].ACLR
reset => haddr[2].ACLR
reset => haddr[3].ACLR
reset => haddr[4].ACLR
reset => haddr[5].ACLR
reset => haddr[6].ACLR
reset => haddr[7].ACLR
reset => haddr[8].ACLR
reset => haddr[9].ACLR
reset => haddr[10].ACLR
reset => haddr[11].ACLR
reset => haddr[12].ACLR
reset => hreadyout.PRESET
reset => apbState~6.DATAIN
ahb_clock => hresp.CLK
ahb_clock => hdone.CLK
ahb_clock => hsize[0].CLK
ahb_clock => hsize[1].CLK
ahb_clock => hsize[2].CLK
ahb_clock => hwrite.CLK
ahb_clock => haddr[0].CLK
ahb_clock => haddr[1].CLK
ahb_clock => haddr[2].CLK
ahb_clock => haddr[3].CLK
ahb_clock => haddr[4].CLK
ahb_clock => haddr[5].CLK
ahb_clock => haddr[6].CLK
ahb_clock => haddr[7].CLK
ahb_clock => haddr[8].CLK
ahb_clock => haddr[9].CLK
ahb_clock => haddr[10].CLK
ahb_clock => haddr[11].CLK
ahb_clock => haddr[12].CLK
ahb_clock => hreadyout.CLK
ahb_hmastlock => ~NO_FANOUT~
ahb_htrans[0] => ~NO_FANOUT~
ahb_htrans[1] => always0.IN0
ahb_hsel => always0.IN1
ahb_hready => hresp.OUTPUTSELECT
ahb_hwrite => hwrite.DATAIN
ahb_haddr[0] => haddr[0].DATAIN
ahb_haddr[1] => haddr[1].DATAIN
ahb_haddr[2] => haddr[2].DATAIN
ahb_haddr[3] => haddr[3].DATAIN
ahb_haddr[4] => haddr[4].DATAIN
ahb_haddr[5] => haddr[5].DATAIN
ahb_haddr[6] => haddr[6].DATAIN
ahb_haddr[7] => haddr[7].DATAIN
ahb_haddr[8] => haddr[8].DATAIN
ahb_haddr[9] => haddr[9].DATAIN
ahb_haddr[10] => haddr[10].DATAIN
ahb_haddr[11] => haddr[11].DATAIN
ahb_haddr[12] => haddr[12].DATAIN
ahb_hsize[0] => hsize[0].DATAIN
ahb_hsize[1] => hsize[1].DATAIN
ahb_hsize[2] => hsize[2].DATAIN
ahb_hburst[0] => ~NO_FANOUT~
ahb_hburst[1] => ~NO_FANOUT~
ahb_hburst[2] => ~NO_FANOUT~
ahb_hprot[0] => ~NO_FANOUT~
ahb_hprot[1] => ~NO_FANOUT~
ahb_hprot[2] => ~NO_FANOUT~
ahb_hprot[3] => ~NO_FANOUT~
ahb_hwdata[0] => apb_pwdata[0].DATAIN
ahb_hwdata[1] => apb_pwdata[1].DATAIN
ahb_hwdata[2] => apb_pwdata[2].DATAIN
ahb_hwdata[3] => apb_pwdata[3].DATAIN
ahb_hwdata[4] => apb_pwdata[4].DATAIN
ahb_hwdata[5] => apb_pwdata[5].DATAIN
ahb_hwdata[6] => apb_pwdata[6].DATAIN
ahb_hwdata[7] => apb_pwdata[7].DATAIN
ahb_hwdata[8] => apb_pwdata[8].DATAIN
ahb_hwdata[9] => apb_pwdata[9].DATAIN
ahb_hwdata[10] => apb_pwdata[10].DATAIN
ahb_hwdata[11] => apb_pwdata[11].DATAIN
ahb_hwdata[12] => apb_pwdata[12].DATAIN
ahb_hwdata[13] => apb_pwdata[13].DATAIN
ahb_hwdata[14] => apb_pwdata[14].DATAIN
ahb_hwdata[15] => apb_pwdata[15].DATAIN
ahb_hwdata[16] => apb_pwdata[16].DATAIN
ahb_hwdata[17] => apb_pwdata[17].DATAIN
ahb_hwdata[18] => apb_pwdata[18].DATAIN
ahb_hwdata[19] => apb_pwdata[19].DATAIN
ahb_hwdata[20] => apb_pwdata[20].DATAIN
ahb_hwdata[21] => apb_pwdata[21].DATAIN
ahb_hwdata[22] => apb_pwdata[22].DATAIN
ahb_hwdata[23] => apb_pwdata[23].DATAIN
ahb_hwdata[24] => apb_pwdata[24].DATAIN
ahb_hwdata[25] => apb_pwdata[25].DATAIN
ahb_hwdata[26] => apb_pwdata[26].DATAIN
ahb_hwdata[27] => apb_pwdata[27].DATAIN
ahb_hwdata[28] => apb_pwdata[28].DATAIN
ahb_hwdata[29] => apb_pwdata[29].DATAIN
ahb_hwdata[30] => apb_pwdata[30].DATAIN
ahb_hwdata[31] => apb_pwdata[31].DATAIN
ahb_hrdata[0] <= prdata[0].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[1] <= prdata[1].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[2] <= prdata[2].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[3] <= prdata[3].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[4] <= prdata[4].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[5] <= prdata[5].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[6] <= prdata[6].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[7] <= prdata[7].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[8] <= prdata[8].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[9] <= prdata[9].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[10] <= prdata[10].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[11] <= prdata[11].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[12] <= prdata[12].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[13] <= prdata[13].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[14] <= prdata[14].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[15] <= prdata[15].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[16] <= prdata[16].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[17] <= prdata[17].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[18] <= prdata[18].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[19] <= prdata[19].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[20] <= prdata[20].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[21] <= prdata[21].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[22] <= prdata[22].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[23] <= prdata[23].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[24] <= prdata[24].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[25] <= prdata[25].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[26] <= prdata[26].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[27] <= prdata[27].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[28] <= prdata[28].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[29] <= prdata[29].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[30] <= prdata[30].DB_MAX_OUTPUT_PORT_TYPE
ahb_hrdata[31] <= prdata[31].DB_MAX_OUTPUT_PORT_TYPE
ahb_hreadyout <= hreadyout.DB_MAX_OUTPUT_PORT_TYPE
ahb_hresp <= hresp.DB_MAX_OUTPUT_PORT_TYPE
apb_clock => prdata[0].CLK
apb_clock => prdata[1].CLK
apb_clock => prdata[2].CLK
apb_clock => prdata[3].CLK
apb_clock => prdata[4].CLK
apb_clock => prdata[5].CLK
apb_clock => prdata[6].CLK
apb_clock => prdata[7].CLK
apb_clock => prdata[8].CLK
apb_clock => prdata[9].CLK
apb_clock => prdata[10].CLK
apb_clock => prdata[11].CLK
apb_clock => prdata[12].CLK
apb_clock => prdata[13].CLK
apb_clock => prdata[14].CLK
apb_clock => prdata[15].CLK
apb_clock => prdata[16].CLK
apb_clock => prdata[17].CLK
apb_clock => prdata[18].CLK
apb_clock => prdata[19].CLK
apb_clock => prdata[20].CLK
apb_clock => prdata[21].CLK
apb_clock => prdata[22].CLK
apb_clock => prdata[23].CLK
apb_clock => prdata[24].CLK
apb_clock => prdata[25].CLK
apb_clock => prdata[26].CLK
apb_clock => prdata[27].CLK
apb_clock => prdata[28].CLK
apb_clock => prdata[29].CLK
apb_clock => prdata[30].CLK
apb_clock => prdata[31].CLK
apb_clock => pstrb[0].CLK
apb_clock => pstrb[1].CLK
apb_clock => pstrb[2].CLK
apb_clock => pstrb[3].CLK
apb_clock => paddr[0].CLK
apb_clock => paddr[1].CLK
apb_clock => paddr[2].CLK
apb_clock => paddr[3].CLK
apb_clock => paddr[4].CLK
apb_clock => paddr[5].CLK
apb_clock => paddr[6].CLK
apb_clock => paddr[7].CLK
apb_clock => paddr[8].CLK
apb_clock => paddr[9].CLK
apb_clock => paddr[10].CLK
apb_clock => paddr[11].CLK
apb_clock => paddr[12].CLK
apb_clock => pwrite.CLK
apb_clock => penable.CLK
apb_clock => psel.CLK
apb_clock => pdone.CLK
apb_clock => pvalid.CLK
apb_clock => apbState~4.DATAIN
apb_psel <= psel.DB_MAX_OUTPUT_PORT_TYPE
apb_penable <= penable.DB_MAX_OUTPUT_PORT_TYPE
apb_pwrite <= pwrite.DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[0] <= paddr[0].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[1] <= paddr[1].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[2] <= paddr[2].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[3] <= paddr[3].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[4] <= paddr[4].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[5] <= paddr[5].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[6] <= paddr[6].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[7] <= paddr[7].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[8] <= paddr[8].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[9] <= paddr[9].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[10] <= paddr[10].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[11] <= paddr[11].DB_MAX_OUTPUT_PORT_TYPE
apb_paddr[12] <= paddr[12].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[0] <= ahb_hwdata[0].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[1] <= ahb_hwdata[1].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[2] <= ahb_hwdata[2].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[3] <= ahb_hwdata[3].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[4] <= ahb_hwdata[4].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[5] <= ahb_hwdata[5].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[6] <= ahb_hwdata[6].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[7] <= ahb_hwdata[7].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[8] <= ahb_hwdata[8].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[9] <= ahb_hwdata[9].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[10] <= ahb_hwdata[10].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[11] <= ahb_hwdata[11].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[12] <= ahb_hwdata[12].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[13] <= ahb_hwdata[13].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[14] <= ahb_hwdata[14].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[15] <= ahb_hwdata[15].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[16] <= ahb_hwdata[16].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[17] <= ahb_hwdata[17].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[18] <= ahb_hwdata[18].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[19] <= ahb_hwdata[19].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[20] <= ahb_hwdata[20].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[21] <= ahb_hwdata[21].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[22] <= ahb_hwdata[22].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[23] <= ahb_hwdata[23].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[24] <= ahb_hwdata[24].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[25] <= ahb_hwdata[25].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[26] <= ahb_hwdata[26].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[27] <= ahb_hwdata[27].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[28] <= ahb_hwdata[28].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[29] <= ahb_hwdata[29].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[30] <= ahb_hwdata[30].DB_MAX_OUTPUT_PORT_TYPE
apb_pwdata[31] <= ahb_hwdata[31].DB_MAX_OUTPUT_PORT_TYPE
apb_pstrb[0] <= pstrb[0].DB_MAX_OUTPUT_PORT_TYPE
apb_pstrb[1] <= pstrb[1].DB_MAX_OUTPUT_PORT_TYPE
apb_pstrb[2] <= pstrb[2].DB_MAX_OUTPUT_PORT_TYPE
apb_pstrb[3] <= pstrb[3].DB_MAX_OUTPUT_PORT_TYPE
apb_pprot[0] <= <VCC>
apb_pprot[1] <= <GND>
apb_pprot[2] <= <GND>
apb_pready => apb_pdone.IN1
apb_pready => apbState.OUTPUTSELECT
apb_pready => apbState.OUTPUTSELECT
apb_pready => apbState.OUTPUTSELECT
apb_pready => penable.OUTPUTSELECT
apb_pready => psel.OUTPUTSELECT
apb_pready => pwrite.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => paddr.OUTPUTSELECT
apb_pready => pstrb.OUTPUTSELECT
apb_pready => pstrb.OUTPUTSELECT
apb_pready => pstrb.OUTPUTSELECT
apb_pready => pstrb.OUTPUTSELECT
apb_pslverr => always6.IN1
apb_prdata[0] => prdata[0].DATAIN
apb_prdata[1] => prdata[1].DATAIN
apb_prdata[2] => prdata[2].DATAIN
apb_prdata[3] => prdata[3].DATAIN
apb_prdata[4] => prdata[4].DATAIN
apb_prdata[5] => prdata[5].DATAIN
apb_prdata[6] => prdata[6].DATAIN
apb_prdata[7] => prdata[7].DATAIN
apb_prdata[8] => prdata[8].DATAIN
apb_prdata[9] => prdata[9].DATAIN
apb_prdata[10] => prdata[10].DATAIN
apb_prdata[11] => prdata[11].DATAIN
apb_prdata[12] => prdata[12].DATAIN
apb_prdata[13] => prdata[13].DATAIN
apb_prdata[14] => prdata[14].DATAIN
apb_prdata[15] => prdata[15].DATAIN
apb_prdata[16] => prdata[16].DATAIN
apb_prdata[17] => prdata[17].DATAIN
apb_prdata[18] => prdata[18].DATAIN
apb_prdata[19] => prdata[19].DATAIN
apb_prdata[20] => prdata[20].DATAIN
apb_prdata[21] => prdata[21].DATAIN
apb_prdata[22] => prdata[22].DATAIN
apb_prdata[23] => prdata[23].DATAIN
apb_prdata[24] => prdata[24].DATAIN
apb_prdata[25] => prdata[25].DATAIN
apb_prdata[26] => prdata[26].DATAIN
apb_prdata[27] => prdata[27].DATAIN
apb_prdata[28] => prdata[28].DATAIN
apb_prdata[29] => prdata[29].DATAIN
apb_prdata[30] => prdata[30].DATAIN
apb_prdata[31] => prdata[31].DATAIN


|test_uart|multi_uart_ip:macro_inst|apb_mux:u_apb_mux
apb_clock => pr_select[0].CLK
apb_clock => pr_select[1].CLK
apb_resetn => pr_select[0].ACLR
apb_resetn => pr_select[1].ACLR
apb_in_psel => apb_out_psel.IN0
apb_in_psel => apb_out_psel.IN0
apb_in_psel => always0.IN0
apb_in_penable => apb_out_penable.IN0
apb_in_penable => apb_out_penable.IN0
apb_in_penable => always0.IN1
apb_in_pwrite => apb_out_pwrite[1].DATAIN
apb_in_pwrite => apb_out_pwrite[0].DATAIN
apb_in_paddr[0] => apb_out_paddr[12].DATAIN
apb_in_paddr[0] => apb_out_paddr[0].DATAIN
apb_in_paddr[1] => apb_out_paddr[13].DATAIN
apb_in_paddr[1] => apb_out_paddr[1].DATAIN
apb_in_paddr[2] => apb_out_paddr[14].DATAIN
apb_in_paddr[2] => apb_out_paddr[2].DATAIN
apb_in_paddr[3] => apb_out_paddr[15].DATAIN
apb_in_paddr[3] => apb_out_paddr[3].DATAIN
apb_in_paddr[4] => apb_out_paddr[16].DATAIN
apb_in_paddr[4] => apb_out_paddr[4].DATAIN
apb_in_paddr[5] => apb_out_paddr[17].DATAIN
apb_in_paddr[5] => apb_out_paddr[5].DATAIN
apb_in_paddr[6] => apb_out_paddr[18].DATAIN
apb_in_paddr[6] => apb_out_paddr[6].DATAIN
apb_in_paddr[7] => apb_out_paddr[19].DATAIN
apb_in_paddr[7] => apb_out_paddr[7].DATAIN
apb_in_paddr[8] => apb_out_paddr[20].DATAIN
apb_in_paddr[8] => apb_out_paddr[8].DATAIN
apb_in_paddr[9] => apb_out_paddr[21].DATAIN
apb_in_paddr[9] => apb_out_paddr[9].DATAIN
apb_in_paddr[10] => apb_out_paddr[22].DATAIN
apb_in_paddr[10] => apb_out_paddr[10].DATAIN
apb_in_paddr[11] => apb_out_paddr[23].DATAIN
apb_in_paddr[11] => apb_out_paddr[11].DATAIN
apb_in_pwdata[0] => apb_out_pwdata[32].DATAIN
apb_in_pwdata[0] => apb_out_pwdata[0].DATAIN
apb_in_pwdata[1] => apb_out_pwdata[33].DATAIN
apb_in_pwdata[1] => apb_out_pwdata[1].DATAIN
apb_in_pwdata[2] => apb_out_pwdata[34].DATAIN
apb_in_pwdata[2] => apb_out_pwdata[2].DATAIN
apb_in_pwdata[3] => apb_out_pwdata[35].DATAIN
apb_in_pwdata[3] => apb_out_pwdata[3].DATAIN
apb_in_pwdata[4] => apb_out_pwdata[36].DATAIN
apb_in_pwdata[4] => apb_out_pwdata[4].DATAIN
apb_in_pwdata[5] => apb_out_pwdata[37].DATAIN
apb_in_pwdata[5] => apb_out_pwdata[5].DATAIN
apb_in_pwdata[6] => apb_out_pwdata[38].DATAIN
apb_in_pwdata[6] => apb_out_pwdata[6].DATAIN
apb_in_pwdata[7] => apb_out_pwdata[39].DATAIN
apb_in_pwdata[7] => apb_out_pwdata[7].DATAIN
apb_in_pwdata[8] => apb_out_pwdata[40].DATAIN
apb_in_pwdata[8] => apb_out_pwdata[8].DATAIN
apb_in_pwdata[9] => apb_out_pwdata[41].DATAIN
apb_in_pwdata[9] => apb_out_pwdata[9].DATAIN
apb_in_pwdata[10] => apb_out_pwdata[42].DATAIN
apb_in_pwdata[10] => apb_out_pwdata[10].DATAIN
apb_in_pwdata[11] => apb_out_pwdata[43].DATAIN
apb_in_pwdata[11] => apb_out_pwdata[11].DATAIN
apb_in_pwdata[12] => apb_out_pwdata[44].DATAIN
apb_in_pwdata[12] => apb_out_pwdata[12].DATAIN
apb_in_pwdata[13] => apb_out_pwdata[45].DATAIN
apb_in_pwdata[13] => apb_out_pwdata[13].DATAIN
apb_in_pwdata[14] => apb_out_pwdata[46].DATAIN
apb_in_pwdata[14] => apb_out_pwdata[14].DATAIN
apb_in_pwdata[15] => apb_out_pwdata[47].DATAIN
apb_in_pwdata[15] => apb_out_pwdata[15].DATAIN
apb_in_pwdata[16] => apb_out_pwdata[48].DATAIN
apb_in_pwdata[16] => apb_out_pwdata[16].DATAIN
apb_in_pwdata[17] => apb_out_pwdata[49].DATAIN
apb_in_pwdata[17] => apb_out_pwdata[17].DATAIN
apb_in_pwdata[18] => apb_out_pwdata[50].DATAIN
apb_in_pwdata[18] => apb_out_pwdata[18].DATAIN
apb_in_pwdata[19] => apb_out_pwdata[51].DATAIN
apb_in_pwdata[19] => apb_out_pwdata[19].DATAIN
apb_in_pwdata[20] => apb_out_pwdata[52].DATAIN
apb_in_pwdata[20] => apb_out_pwdata[20].DATAIN
apb_in_pwdata[21] => apb_out_pwdata[53].DATAIN
apb_in_pwdata[21] => apb_out_pwdata[21].DATAIN
apb_in_pwdata[22] => apb_out_pwdata[54].DATAIN
apb_in_pwdata[22] => apb_out_pwdata[22].DATAIN
apb_in_pwdata[23] => apb_out_pwdata[55].DATAIN
apb_in_pwdata[23] => apb_out_pwdata[23].DATAIN
apb_in_pwdata[24] => apb_out_pwdata[56].DATAIN
apb_in_pwdata[24] => apb_out_pwdata[24].DATAIN
apb_in_pwdata[25] => apb_out_pwdata[57].DATAIN
apb_in_pwdata[25] => apb_out_pwdata[25].DATAIN
apb_in_pwdata[26] => apb_out_pwdata[58].DATAIN
apb_in_pwdata[26] => apb_out_pwdata[26].DATAIN
apb_in_pwdata[27] => apb_out_pwdata[59].DATAIN
apb_in_pwdata[27] => apb_out_pwdata[27].DATAIN
apb_in_pwdata[28] => apb_out_pwdata[60].DATAIN
apb_in_pwdata[28] => apb_out_pwdata[28].DATAIN
apb_in_pwdata[29] => apb_out_pwdata[61].DATAIN
apb_in_pwdata[29] => apb_out_pwdata[29].DATAIN
apb_in_pwdata[30] => apb_out_pwdata[62].DATAIN
apb_in_pwdata[30] => apb_out_pwdata[30].DATAIN
apb_in_pwdata[31] => apb_out_pwdata[63].DATAIN
apb_in_pwdata[31] => apb_out_pwdata[31].DATAIN
apb_in_prdata[0] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[1] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[2] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[3] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[4] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[5] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[6] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[7] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[8] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[9] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[10] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[11] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[12] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[13] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[14] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[15] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[16] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[17] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[18] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[19] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[20] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[21] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[22] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[23] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[24] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[25] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[26] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[27] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[28] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[29] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[30] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_prdata[31] <= apb_in_prdata.DB_MAX_OUTPUT_PORT_TYPE
apb_in_pready <= apb_in_pready.DB_MAX_OUTPUT_PORT_TYPE
apb_in_pslverr <= apb_in_pslverr.DB_MAX_OUTPUT_PORT_TYPE
apb_out_psel[0] <= apb_out_psel.DB_MAX_OUTPUT_PORT_TYPE
apb_out_psel[1] <= apb_out_psel.DB_MAX_OUTPUT_PORT_TYPE
apb_out_penable[0] <= apb_out_penable.DB_MAX_OUTPUT_PORT_TYPE
apb_out_penable[1] <= apb_out_penable.DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwrite[0] <= apb_in_pwrite.DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwrite[1] <= apb_in_pwrite.DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[0] <= apb_in_paddr[0].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[1] <= apb_in_paddr[1].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[2] <= apb_in_paddr[2].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[3] <= apb_in_paddr[3].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[4] <= apb_in_paddr[4].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[5] <= apb_in_paddr[5].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[6] <= apb_in_paddr[6].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[7] <= apb_in_paddr[7].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[8] <= apb_in_paddr[8].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[9] <= apb_in_paddr[9].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[10] <= apb_in_paddr[10].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[11] <= apb_in_paddr[11].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[12] <= apb_in_paddr[0].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[13] <= apb_in_paddr[1].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[14] <= apb_in_paddr[2].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[15] <= apb_in_paddr[3].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[16] <= apb_in_paddr[4].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[17] <= apb_in_paddr[5].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[18] <= apb_in_paddr[6].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[19] <= apb_in_paddr[7].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[20] <= apb_in_paddr[8].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[21] <= apb_in_paddr[9].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[22] <= apb_in_paddr[10].DB_MAX_OUTPUT_PORT_TYPE
apb_out_paddr[23] <= apb_in_paddr[11].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[0] <= apb_in_pwdata[0].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[1] <= apb_in_pwdata[1].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[2] <= apb_in_pwdata[2].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[3] <= apb_in_pwdata[3].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[4] <= apb_in_pwdata[4].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[5] <= apb_in_pwdata[5].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[6] <= apb_in_pwdata[6].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[7] <= apb_in_pwdata[7].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[8] <= apb_in_pwdata[8].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[9] <= apb_in_pwdata[9].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[10] <= apb_in_pwdata[10].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[11] <= apb_in_pwdata[11].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[12] <= apb_in_pwdata[12].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[13] <= apb_in_pwdata[13].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[14] <= apb_in_pwdata[14].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[15] <= apb_in_pwdata[15].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[16] <= apb_in_pwdata[16].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[17] <= apb_in_pwdata[17].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[18] <= apb_in_pwdata[18].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[19] <= apb_in_pwdata[19].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[20] <= apb_in_pwdata[20].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[21] <= apb_in_pwdata[21].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[22] <= apb_in_pwdata[22].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[23] <= apb_in_pwdata[23].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[24] <= apb_in_pwdata[24].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[25] <= apb_in_pwdata[25].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[26] <= apb_in_pwdata[26].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[27] <= apb_in_pwdata[27].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[28] <= apb_in_pwdata[28].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[29] <= apb_in_pwdata[29].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[30] <= apb_in_pwdata[30].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[31] <= apb_in_pwdata[31].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[32] <= apb_in_pwdata[0].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[33] <= apb_in_pwdata[1].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[34] <= apb_in_pwdata[2].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[35] <= apb_in_pwdata[3].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[36] <= apb_in_pwdata[4].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[37] <= apb_in_pwdata[5].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[38] <= apb_in_pwdata[6].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[39] <= apb_in_pwdata[7].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[40] <= apb_in_pwdata[8].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[41] <= apb_in_pwdata[9].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[42] <= apb_in_pwdata[10].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[43] <= apb_in_pwdata[11].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[44] <= apb_in_pwdata[12].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[45] <= apb_in_pwdata[13].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[46] <= apb_in_pwdata[14].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[47] <= apb_in_pwdata[15].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[48] <= apb_in_pwdata[16].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[49] <= apb_in_pwdata[17].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[50] <= apb_in_pwdata[18].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[51] <= apb_in_pwdata[19].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[52] <= apb_in_pwdata[20].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[53] <= apb_in_pwdata[21].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[54] <= apb_in_pwdata[22].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[55] <= apb_in_pwdata[23].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[56] <= apb_in_pwdata[24].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[57] <= apb_in_pwdata[25].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[58] <= apb_in_pwdata[26].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[59] <= apb_in_pwdata[27].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[60] <= apb_in_pwdata[28].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[61] <= apb_in_pwdata[29].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[62] <= apb_in_pwdata[30].DB_MAX_OUTPUT_PORT_TYPE
apb_out_pwdata[63] <= apb_in_pwdata[31].DB_MAX_OUTPUT_PORT_TYPE
apb_out_prdata[0] => apb_in_prdata.DATAB
apb_out_prdata[1] => apb_in_prdata.DATAB
apb_out_prdata[2] => apb_in_prdata.DATAB
apb_out_prdata[3] => apb_in_prdata.DATAB
apb_out_prdata[4] => apb_in_prdata.DATAB
apb_out_prdata[5] => apb_in_prdata.DATAB
apb_out_prdata[6] => apb_in_prdata.DATAB
apb_out_prdata[7] => apb_in_prdata.DATAB
apb_out_prdata[8] => apb_in_prdata.DATAB
apb_out_prdata[9] => apb_in_prdata.DATAB
apb_out_prdata[10] => apb_in_prdata.DATAB
apb_out_prdata[11] => apb_in_prdata.DATAB
apb_out_prdata[12] => apb_in_prdata.DATAB
apb_out_prdata[13] => apb_in_prdata.DATAB
apb_out_prdata[14] => apb_in_prdata.DATAB
apb_out_prdata[15] => apb_in_prdata.DATAB
apb_out_prdata[16] => apb_in_prdata.DATAB
apb_out_prdata[17] => apb_in_prdata.DATAB
apb_out_prdata[18] => apb_in_prdata.DATAB
apb_out_prdata[19] => apb_in_prdata.DATAB
apb_out_prdata[20] => apb_in_prdata.DATAB
apb_out_prdata[21] => apb_in_prdata.DATAB
apb_out_prdata[22] => apb_in_prdata.DATAB
apb_out_prdata[23] => apb_in_prdata.DATAB
apb_out_prdata[24] => apb_in_prdata.DATAB
apb_out_prdata[25] => apb_in_prdata.DATAB
apb_out_prdata[26] => apb_in_prdata.DATAB
apb_out_prdata[27] => apb_in_prdata.DATAB
apb_out_prdata[28] => apb_in_prdata.DATAB
apb_out_prdata[29] => apb_in_prdata.DATAB
apb_out_prdata[30] => apb_in_prdata.DATAB
apb_out_prdata[31] => apb_in_prdata.DATAB
apb_out_prdata[32] => apb_in_prdata.DATAB
apb_out_prdata[33] => apb_in_prdata.DATAB
apb_out_prdata[34] => apb_in_prdata.DATAB
apb_out_prdata[35] => apb_in_prdata.DATAB
apb_out_prdata[36] => apb_in_prdata.DATAB
apb_out_prdata[37] => apb_in_prdata.DATAB
apb_out_prdata[38] => apb_in_prdata.DATAB
apb_out_prdata[39] => apb_in_prdata.DATAB
apb_out_prdata[40] => apb_in_prdata.DATAB
apb_out_prdata[41] => apb_in_prdata.DATAB
apb_out_prdata[42] => apb_in_prdata.DATAB
apb_out_prdata[43] => apb_in_prdata.DATAB
apb_out_prdata[44] => apb_in_prdata.DATAB
apb_out_prdata[45] => apb_in_prdata.DATAB
apb_out_prdata[46] => apb_in_prdata.DATAB
apb_out_prdata[47] => apb_in_prdata.DATAB
apb_out_prdata[48] => apb_in_prdata.DATAB
apb_out_prdata[49] => apb_in_prdata.DATAB
apb_out_prdata[50] => apb_in_prdata.DATAB
apb_out_prdata[51] => apb_in_prdata.DATAB
apb_out_prdata[52] => apb_in_prdata.DATAB
apb_out_prdata[53] => apb_in_prdata.DATAB
apb_out_prdata[54] => apb_in_prdata.DATAB
apb_out_prdata[55] => apb_in_prdata.DATAB
apb_out_prdata[56] => apb_in_prdata.DATAB
apb_out_prdata[57] => apb_in_prdata.DATAB
apb_out_prdata[58] => apb_in_prdata.DATAB
apb_out_prdata[59] => apb_in_prdata.DATAB
apb_out_prdata[60] => apb_in_prdata.DATAB
apb_out_prdata[61] => apb_in_prdata.DATAB
apb_out_prdata[62] => apb_in_prdata.DATAB
apb_out_prdata[63] => apb_in_prdata.DATAB
apb_out_pready[0] => apb_in_pready.DATAB
apb_out_pready[1] => apb_in_pready.DATAB
apb_out_pslverr[0] => apb_in_pslverr.DATAB
apb_out_pslverr[1] => apb_in_pslverr.DATAB
apb_select[0] => apb_out_psel.IN1
apb_select[0] => apb_out_penable.IN1
apb_select[0] => pr_select[0].DATAIN
apb_select[1] => apb_out_psel.IN1
apb_select[1] => apb_out_penable.IN1
apb_select[1] => pr_select[1].DATAIN


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]
apb_clock => apb_clock.IN2
apb_resetn => apb_resetn.IN2
apb_psel => apb_psel.IN1
apb_penable => apb_penable.IN1
apb_pwrite => apb_pwrite.IN1
apb_paddr[0] => apb_paddr[0].IN1
apb_paddr[1] => apb_paddr[1].IN1
apb_paddr[2] => apb_paddr[2].IN1
apb_paddr[3] => apb_paddr[3].IN1
apb_paddr[4] => apb_paddr[4].IN1
apb_paddr[5] => apb_paddr[5].IN1
apb_paddr[6] => apb_paddr[6].IN1
apb_paddr[7] => apb_paddr[7].IN1
apb_paddr[8] => apb_paddr[8].IN1
apb_paddr[9] => apb_paddr[9].IN1
apb_paddr[10] => apb_paddr[10].IN1
apb_paddr[11] => apb_paddr[11].IN1
apb_pwdata[0] => apb_pwdata[0].IN1
apb_pwdata[1] => apb_pwdata[1].IN1
apb_pwdata[2] => apb_pwdata[2].IN1
apb_pwdata[3] => apb_pwdata[3].IN1
apb_pwdata[4] => apb_pwdata[4].IN1
apb_pwdata[5] => apb_pwdata[5].IN1
apb_pwdata[6] => apb_pwdata[6].IN1
apb_pwdata[7] => apb_pwdata[7].IN1
apb_pwdata[8] => apb_pwdata[8].IN1
apb_pwdata[9] => apb_pwdata[9].IN1
apb_pwdata[10] => apb_pwdata[10].IN1
apb_pwdata[11] => apb_pwdata[11].IN1
apb_pwdata[12] => apb_pwdata[12].IN1
apb_pwdata[13] => apb_pwdata[13].IN1
apb_pwdata[14] => apb_pwdata[14].IN1
apb_pwdata[15] => apb_pwdata[15].IN1
apb_pwdata[16] => apb_pwdata[16].IN1
apb_pwdata[17] => apb_pwdata[17].IN1
apb_pwdata[18] => apb_pwdata[18].IN1
apb_pwdata[19] => apb_pwdata[19].IN1
apb_pwdata[20] => apb_pwdata[20].IN1
apb_pwdata[21] => apb_pwdata[21].IN1
apb_pwdata[22] => apb_pwdata[22].IN1
apb_pwdata[23] => apb_pwdata[23].IN1
apb_pwdata[24] => apb_pwdata[24].IN1
apb_pwdata[25] => apb_pwdata[25].IN1
apb_pwdata[26] => apb_pwdata[26].IN1
apb_pwdata[27] => apb_pwdata[27].IN1
apb_pwdata[28] => apb_pwdata[28].IN1
apb_pwdata[29] => apb_pwdata[29].IN1
apb_pwdata[30] => apb_pwdata[30].IN1
apb_pwdata[31] => apb_pwdata[31].IN1
apb_prdata[0] <= uart_regs:u_regs.apb_prdata
apb_prdata[1] <= uart_regs:u_regs.apb_prdata
apb_prdata[2] <= uart_regs:u_regs.apb_prdata
apb_prdata[3] <= uart_regs:u_regs.apb_prdata
apb_prdata[4] <= uart_regs:u_regs.apb_prdata
apb_prdata[5] <= uart_regs:u_regs.apb_prdata
apb_prdata[6] <= uart_regs:u_regs.apb_prdata
apb_prdata[7] <= uart_regs:u_regs.apb_prdata
apb_prdata[8] <= uart_regs:u_regs.apb_prdata
apb_prdata[9] <= uart_regs:u_regs.apb_prdata
apb_prdata[10] <= uart_regs:u_regs.apb_prdata
apb_prdata[11] <= uart_regs:u_regs.apb_prdata
apb_prdata[12] <= uart_regs:u_regs.apb_prdata
apb_prdata[13] <= uart_regs:u_regs.apb_prdata
apb_prdata[14] <= uart_regs:u_regs.apb_prdata
apb_prdata[15] <= uart_regs:u_regs.apb_prdata
apb_prdata[16] <= uart_regs:u_regs.apb_prdata
apb_prdata[17] <= uart_regs:u_regs.apb_prdata
apb_prdata[18] <= uart_regs:u_regs.apb_prdata
apb_prdata[19] <= uart_regs:u_regs.apb_prdata
apb_prdata[20] <= uart_regs:u_regs.apb_prdata
apb_prdata[21] <= uart_regs:u_regs.apb_prdata
apb_prdata[22] <= uart_regs:u_regs.apb_prdata
apb_prdata[23] <= uart_regs:u_regs.apb_prdata
apb_prdata[24] <= uart_regs:u_regs.apb_prdata
apb_prdata[25] <= uart_regs:u_regs.apb_prdata
apb_prdata[26] <= uart_regs:u_regs.apb_prdata
apb_prdata[27] <= uart_regs:u_regs.apb_prdata
apb_prdata[28] <= uart_regs:u_regs.apb_prdata
apb_prdata[29] <= uart_regs:u_regs.apb_prdata
apb_prdata[30] <= uart_regs:u_regs.apb_prdata
apb_prdata[31] <= uart_regs:u_regs.apb_prdata
apb_pready <= uart_regs:u_regs.apb_pready
uart_txd[0] <= uart_tx:u_tx[0].uart_txd
uart_txd[1] <= uart_tx:u_tx[1].uart_txd
uart_txd[2] <= uart_tx:u_tx[2].uart_txd
uart_txd[3] <= uart_tx:u_tx[3].uart_txd
uart_txd[4] <= uart_tx:u_tx[4].uart_txd
uart_txd[5] <= uart_tx:u_tx[5].uart_txd
uart_rxd[0] => uart_rx:u_rx[0].uart_rxd
uart_rxd[1] => uart_rx:u_rx[1].uart_rxd
uart_rxd[2] => uart_rx:u_rx[2].uart_rxd
uart_rxd[3] => uart_rx:u_rx[3].uart_rxd
uart_rxd[4] => uart_rx:u_rx[4].uart_rxd
uart_rxd[5] => uart_rx:u_rx[5].uart_rxd
tx_dma_clr[0] => uart_tx:u_tx[0].tx_dma_clr
tx_dma_clr[1] => uart_tx:u_tx[1].tx_dma_clr
tx_dma_clr[2] => uart_tx:u_tx[2].tx_dma_clr
tx_dma_clr[3] => uart_tx:u_tx[3].tx_dma_clr
tx_dma_clr[4] => uart_tx:u_tx[4].tx_dma_clr
tx_dma_clr[5] => uart_tx:u_tx[5].tx_dma_clr
tx_dma_req[0] <= uart_tx:u_tx[0].tx_dma_req
tx_dma_req[1] <= uart_tx:u_tx[1].tx_dma_req
tx_dma_req[2] <= uart_tx:u_tx[2].tx_dma_req
tx_dma_req[3] <= uart_tx:u_tx[3].tx_dma_req
tx_dma_req[4] <= uart_tx:u_tx[4].tx_dma_req
tx_dma_req[5] <= uart_tx:u_tx[5].tx_dma_req
rx_dma_clr[0] => uart_rx:u_rx[0].rx_dma_clr
rx_dma_clr[1] => uart_rx:u_rx[1].rx_dma_clr
rx_dma_clr[2] => uart_rx:u_rx[2].rx_dma_clr
rx_dma_clr[3] => uart_rx:u_rx[3].rx_dma_clr
rx_dma_clr[4] => uart_rx:u_rx[4].rx_dma_clr
rx_dma_clr[5] => uart_rx:u_rx[5].rx_dma_clr
rx_dma_req[0] <= uart_rx:u_rx[0].rx_dma_req
rx_dma_req[1] <= uart_rx:u_rx[1].rx_dma_req
rx_dma_req[2] <= uart_rx:u_rx[2].rx_dma_req
rx_dma_req[3] <= uart_rx:u_rx[3].rx_dma_req
rx_dma_req[4] <= uart_rx:u_rx[4].rx_dma_req
rx_dma_req[5] <= uart_rx:u_rx[5].rx_dma_req
interrupts[0] <= uart_regs:u_regs.interrupts
interrupts[1] <= uart_regs:u_regs.interrupts
interrupts[2] <= uart_regs:u_regs.interrupts
interrupts[3] <= uart_regs:u_regs.interrupts
interrupts[4] <= uart_regs:u_regs.interrupts
interrupts[5] <= uart_regs:u_regs.interrupts
uart_tx_busy[0] <= tx_busy[0].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[1] <= tx_busy[1].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[2] <= tx_busy[2].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[3] <= tx_busy[3].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[4] <= tx_busy[4].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[5] <= tx_busy[5].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|baud_gen:u_baud
clk => f_del.CLK
clk => baud16~reg0.CLK
clk => f_cnt[0].CLK
clk => f_cnt[1].CLK
clk => f_cnt[2].CLK
clk => f_cnt[3].CLK
clk => f_cnt[4].CLK
clk => f_cnt[5].CLK
clk => i_cnt[0].CLK
clk => i_cnt[1].CLK
clk => i_cnt[2].CLK
clk => i_cnt[3].CLK
clk => i_cnt[4].CLK
clk => i_cnt[5].CLK
clk => i_cnt[6].CLK
clk => i_cnt[7].CLK
clk => i_cnt[8].CLK
clk => i_cnt[9].CLK
clk => i_cnt[10].CLK
clk => i_cnt[11].CLK
clk => i_cnt[12].CLK
clk => i_cnt[13].CLK
clk => i_cnt[14].CLK
clk => i_cnt[15].CLK
rstn => i_cnt[0].PRESET
rstn => i_cnt[1].ACLR
rstn => i_cnt[2].ACLR
rstn => i_cnt[3].ACLR
rstn => i_cnt[4].ACLR
rstn => i_cnt[5].ACLR
rstn => i_cnt[6].ACLR
rstn => i_cnt[7].ACLR
rstn => i_cnt[8].ACLR
rstn => i_cnt[9].ACLR
rstn => i_cnt[10].ACLR
rstn => i_cnt[11].ACLR
rstn => i_cnt[12].ACLR
rstn => i_cnt[13].ACLR
rstn => i_cnt[14].ACLR
rstn => i_cnt[15].ACLR
rstn => baud16~reg0.ACLR
rstn => f_cnt[0].ACLR
rstn => f_cnt[1].ACLR
rstn => f_cnt[2].ACLR
rstn => f_cnt[3].ACLR
rstn => f_cnt[4].ACLR
rstn => f_cnt[5].ACLR
rstn => f_del.ACLR
ibrd[0] => i_cnt.DATAB
ibrd[1] => i_cnt.DATAB
ibrd[2] => i_cnt.DATAB
ibrd[3] => i_cnt.DATAB
ibrd[4] => i_cnt.DATAB
ibrd[5] => i_cnt.DATAB
ibrd[6] => i_cnt.DATAB
ibrd[7] => i_cnt.DATAB
ibrd[8] => i_cnt.DATAB
ibrd[9] => i_cnt.DATAB
ibrd[10] => i_cnt.DATAB
ibrd[11] => i_cnt.DATAB
ibrd[12] => i_cnt.DATAB
ibrd[13] => i_cnt.DATAB
ibrd[14] => i_cnt.DATAB
ibrd[15] => i_cnt.DATAB
fbrd[0] => LessThan0.IN6
fbrd[1] => LessThan0.IN5
fbrd[2] => LessThan0.IN4
fbrd[3] => LessThan0.IN3
fbrd[4] => LessThan0.IN2
fbrd[5] => LessThan0.IN1
stop => always0.IN1
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => always2.IN1
baud16 <= baud16~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs
apb_clock => apb_prdata[0]~reg0.CLK
apb_clock => apb_prdata[1]~reg0.CLK
apb_clock => apb_prdata[2]~reg0.CLK
apb_clock => apb_prdata[3]~reg0.CLK
apb_clock => apb_prdata[4]~reg0.CLK
apb_clock => apb_prdata[5]~reg0.CLK
apb_clock => apb_prdata[6]~reg0.CLK
apb_clock => apb_prdata[7]~reg0.CLK
apb_clock => apb_prdata[8]~reg0.CLK
apb_clock => apb_prdata[9]~reg0.CLK
apb_clock => apb_prdata[10]~reg0.CLK
apb_clock => apb_prdata[11]~reg0.CLK
apb_clock => apb_prdata[12]~reg0.CLK
apb_clock => apb_prdata[13]~reg0.CLK
apb_clock => apb_prdata[14]~reg0.CLK
apb_clock => apb_prdata[15]~reg0.CLK
apb_clock => apb_prdata[16]~reg0.CLK
apb_clock => apb_prdata[17]~reg0.CLK
apb_clock => apb_prdata[18]~reg0.CLK
apb_clock => apb_prdata[19]~reg0.CLK
apb_clock => apb_prdata[20]~reg0.CLK
apb_clock => apb_prdata[21]~reg0.CLK
apb_clock => apb_prdata[22]~reg0.CLK
apb_clock => apb_prdata[23]~reg0.CLK
apb_clock => apb_prdata[24]~reg0.CLK
apb_clock => apb_prdata[25]~reg0.CLK
apb_clock => apb_prdata[26]~reg0.CLK
apb_clock => apb_prdata[27]~reg0.CLK
apb_clock => apb_prdata[28]~reg0.CLK
apb_clock => apb_prdata[29]~reg0.CLK
apb_clock => apb_prdata[30]~reg0.CLK
apb_clock => apb_prdata[31]~reg0.CLK
apb_clock => status_reg[0].CLK
apb_clock => status_reg[1].CLK
apb_clock => status_reg[2].CLK
apb_clock => status_reg[3].CLK
apb_clock => status_reg[4].CLK
apb_clock => rx_reg[0].CLK
apb_clock => rx_reg[1].CLK
apb_clock => rx_reg[2].CLK
apb_clock => rx_reg[3].CLK
apb_clock => rx_reg[4].CLK
apb_clock => rx_reg[5].CLK
apb_clock => rx_reg[6].CLK
apb_clock => rx_reg[7].CLK
apb_clock => interrupts[0]~reg0.CLK
apb_clock => interrupts[1]~reg0.CLK
apb_clock => interrupts[2]~reg0.CLK
apb_clock => interrupts[3]~reg0.CLK
apb_clock => interrupts[4]~reg0.CLK
apb_clock => interrupts[5]~reg0.CLK
apb_clock => tx_dma_en[0]~reg0.CLK
apb_clock => tx_dma_en[1]~reg0.CLK
apb_clock => tx_dma_en[2]~reg0.CLK
apb_clock => tx_dma_en[3]~reg0.CLK
apb_clock => tx_dma_en[4]~reg0.CLK
apb_clock => tx_dma_en[5]~reg0.CLK
apb_clock => rx_dma_en[0]~reg0.CLK
apb_clock => rx_dma_en[1]~reg0.CLK
apb_clock => rx_dma_en[2]~reg0.CLK
apb_clock => rx_dma_en[3]~reg0.CLK
apb_clock => rx_dma_en[4]~reg0.CLK
apb_clock => rx_dma_en[5]~reg0.CLK
apb_clock => overrun_error_ie[0].CLK
apb_clock => overrun_error_ie[1].CLK
apb_clock => overrun_error_ie[2].CLK
apb_clock => overrun_error_ie[3].CLK
apb_clock => overrun_error_ie[4].CLK
apb_clock => overrun_error_ie[5].CLK
apb_clock => break_error_ie[0].CLK
apb_clock => break_error_ie[1].CLK
apb_clock => break_error_ie[2].CLK
apb_clock => break_error_ie[3].CLK
apb_clock => break_error_ie[4].CLK
apb_clock => break_error_ie[5].CLK
apb_clock => parity_error_ie[0].CLK
apb_clock => parity_error_ie[1].CLK
apb_clock => parity_error_ie[2].CLK
apb_clock => parity_error_ie[3].CLK
apb_clock => parity_error_ie[4].CLK
apb_clock => parity_error_ie[5].CLK
apb_clock => framing_error_ie[0].CLK
apb_clock => framing_error_ie[1].CLK
apb_clock => framing_error_ie[2].CLK
apb_clock => framing_error_ie[3].CLK
apb_clock => framing_error_ie[4].CLK
apb_clock => framing_error_ie[5].CLK
apb_clock => rx_idle_ie[0].CLK
apb_clock => rx_idle_ie[1].CLK
apb_clock => rx_idle_ie[2].CLK
apb_clock => rx_idle_ie[3].CLK
apb_clock => rx_idle_ie[4].CLK
apb_clock => rx_idle_ie[5].CLK
apb_clock => tx_complete_ie[0].CLK
apb_clock => tx_complete_ie[1].CLK
apb_clock => tx_complete_ie[2].CLK
apb_clock => tx_complete_ie[3].CLK
apb_clock => tx_complete_ie[4].CLK
apb_clock => tx_complete_ie[5].CLK
apb_clock => tx_not_full_ie[0].CLK
apb_clock => tx_not_full_ie[1].CLK
apb_clock => tx_not_full_ie[2].CLK
apb_clock => tx_not_full_ie[3].CLK
apb_clock => tx_not_full_ie[4].CLK
apb_clock => tx_not_full_ie[5].CLK
apb_clock => rx_not_empty_ie[0].CLK
apb_clock => rx_not_empty_ie[1].CLK
apb_clock => rx_not_empty_ie[2].CLK
apb_clock => rx_not_empty_ie[3].CLK
apb_clock => rx_not_empty_ie[4].CLK
apb_clock => rx_not_empty_ie[5].CLK
apb_clock => uart_en~reg0.CLK
apb_clock => lcr_pen~reg0.CLK
apb_clock => lcr_eps~reg0.CLK
apb_clock => lcr_stp2~reg0.CLK
apb_clock => lcr_sps~reg0.CLK
apb_clock => rx_read[0]~reg0.CLK
apb_clock => rx_read[1]~reg0.CLK
apb_clock => rx_read[2]~reg0.CLK
apb_clock => rx_read[3]~reg0.CLK
apb_clock => rx_read[4]~reg0.CLK
apb_clock => rx_read[5]~reg0.CLK
apb_clock => tx_write[0]~reg0.CLK
apb_clock => tx_write[1]~reg0.CLK
apb_clock => tx_write[2]~reg0.CLK
apb_clock => tx_write[3]~reg0.CLK
apb_clock => tx_write[4]~reg0.CLK
apb_clock => tx_write[5]~reg0.CLK
apb_clock => fbrd[0]~reg0.CLK
apb_clock => fbrd[1]~reg0.CLK
apb_clock => fbrd[2]~reg0.CLK
apb_clock => fbrd[3]~reg0.CLK
apb_clock => fbrd[4]~reg0.CLK
apb_clock => fbrd[5]~reg0.CLK
apb_clock => ibrd[0]~reg0.CLK
apb_clock => ibrd[1]~reg0.CLK
apb_clock => ibrd[2]~reg0.CLK
apb_clock => ibrd[3]~reg0.CLK
apb_clock => ibrd[4]~reg0.CLK
apb_clock => ibrd[5]~reg0.CLK
apb_clock => ibrd[6]~reg0.CLK
apb_clock => ibrd[7]~reg0.CLK
apb_clock => ibrd[8]~reg0.CLK
apb_clock => ibrd[9]~reg0.CLK
apb_clock => ibrd[10]~reg0.CLK
apb_clock => ibrd[11]~reg0.CLK
apb_clock => ibrd[12]~reg0.CLK
apb_clock => ibrd[13]~reg0.CLK
apb_clock => ibrd[14]~reg0.CLK
apb_clock => ibrd[15]~reg0.CLK
apb_clock => apb_pready~reg0.CLK
apb_resetn => apb_prdata[0]~reg0.ACLR
apb_resetn => apb_prdata[1]~reg0.ACLR
apb_resetn => apb_prdata[2]~reg0.ACLR
apb_resetn => apb_prdata[3]~reg0.ACLR
apb_resetn => apb_prdata[4]~reg0.ACLR
apb_resetn => apb_prdata[5]~reg0.ACLR
apb_resetn => apb_prdata[6]~reg0.ACLR
apb_resetn => apb_prdata[7]~reg0.ACLR
apb_resetn => apb_prdata[8]~reg0.ACLR
apb_resetn => apb_prdata[9]~reg0.ACLR
apb_resetn => apb_prdata[10]~reg0.ACLR
apb_resetn => apb_prdata[11]~reg0.ACLR
apb_resetn => apb_prdata[12]~reg0.ACLR
apb_resetn => apb_prdata[13]~reg0.ACLR
apb_resetn => apb_prdata[14]~reg0.ACLR
apb_resetn => apb_prdata[15]~reg0.ACLR
apb_resetn => apb_prdata[16]~reg0.ACLR
apb_resetn => apb_prdata[17]~reg0.ACLR
apb_resetn => apb_prdata[18]~reg0.ACLR
apb_resetn => apb_prdata[19]~reg0.ACLR
apb_resetn => apb_prdata[20]~reg0.ACLR
apb_resetn => apb_prdata[21]~reg0.ACLR
apb_resetn => apb_prdata[22]~reg0.ACLR
apb_resetn => apb_prdata[23]~reg0.ACLR
apb_resetn => apb_prdata[24]~reg0.ACLR
apb_resetn => apb_prdata[25]~reg0.ACLR
apb_resetn => apb_prdata[26]~reg0.ACLR
apb_resetn => apb_prdata[27]~reg0.ACLR
apb_resetn => apb_prdata[28]~reg0.ACLR
apb_resetn => apb_prdata[29]~reg0.ACLR
apb_resetn => apb_prdata[30]~reg0.ACLR
apb_resetn => apb_prdata[31]~reg0.ACLR
apb_resetn => apb_pready~reg0.PRESET
apb_resetn => uart_en~reg0.ACLR
apb_resetn => ibrd[0]~reg0.ACLR
apb_resetn => ibrd[1]~reg0.ACLR
apb_resetn => ibrd[2]~reg0.ACLR
apb_resetn => ibrd[3]~reg0.ACLR
apb_resetn => ibrd[4]~reg0.ACLR
apb_resetn => ibrd[5]~reg0.ACLR
apb_resetn => ibrd[6]~reg0.ACLR
apb_resetn => ibrd[7]~reg0.ACLR
apb_resetn => ibrd[8]~reg0.ACLR
apb_resetn => ibrd[9]~reg0.ACLR
apb_resetn => ibrd[10]~reg0.ACLR
apb_resetn => ibrd[11]~reg0.ACLR
apb_resetn => ibrd[12]~reg0.ACLR
apb_resetn => ibrd[13]~reg0.ACLR
apb_resetn => ibrd[14]~reg0.ACLR
apb_resetn => ibrd[15]~reg0.ACLR
apb_resetn => fbrd[0]~reg0.ACLR
apb_resetn => fbrd[1]~reg0.ACLR
apb_resetn => fbrd[2]~reg0.ACLR
apb_resetn => fbrd[3]~reg0.ACLR
apb_resetn => fbrd[4]~reg0.ACLR
apb_resetn => fbrd[5]~reg0.ACLR
apb_resetn => tx_write[0]~reg0.ACLR
apb_resetn => tx_write[1]~reg0.ACLR
apb_resetn => tx_write[2]~reg0.ACLR
apb_resetn => tx_write[3]~reg0.ACLR
apb_resetn => tx_write[4]~reg0.ACLR
apb_resetn => tx_write[5]~reg0.ACLR
apb_resetn => rx_read[0]~reg0.ACLR
apb_resetn => rx_read[1]~reg0.ACLR
apb_resetn => rx_read[2]~reg0.ACLR
apb_resetn => rx_read[3]~reg0.ACLR
apb_resetn => rx_read[4]~reg0.ACLR
apb_resetn => rx_read[5]~reg0.ACLR
apb_resetn => lcr_pen~reg0.ACLR
apb_resetn => lcr_eps~reg0.ACLR
apb_resetn => lcr_stp2~reg0.ACLR
apb_resetn => lcr_sps~reg0.ACLR
apb_resetn => tx_dma_en[0]~reg0.ACLR
apb_resetn => tx_dma_en[1]~reg0.ACLR
apb_resetn => tx_dma_en[2]~reg0.ACLR
apb_resetn => tx_dma_en[3]~reg0.ACLR
apb_resetn => tx_dma_en[4]~reg0.ACLR
apb_resetn => tx_dma_en[5]~reg0.ACLR
apb_resetn => rx_dma_en[0]~reg0.ACLR
apb_resetn => rx_dma_en[1]~reg0.ACLR
apb_resetn => rx_dma_en[2]~reg0.ACLR
apb_resetn => rx_dma_en[3]~reg0.ACLR
apb_resetn => rx_dma_en[4]~reg0.ACLR
apb_resetn => rx_dma_en[5]~reg0.ACLR
apb_resetn => interrupts[0]~reg0.ACLR
apb_resetn => interrupts[1]~reg0.ACLR
apb_resetn => interrupts[2]~reg0.ACLR
apb_resetn => interrupts[3]~reg0.ACLR
apb_resetn => interrupts[4]~reg0.ACLR
apb_resetn => interrupts[5]~reg0.ACLR
apb_resetn => overrun_error_ie[0].ACLR
apb_resetn => overrun_error_ie[1].ACLR
apb_resetn => overrun_error_ie[2].ACLR
apb_resetn => overrun_error_ie[3].ACLR
apb_resetn => overrun_error_ie[4].ACLR
apb_resetn => overrun_error_ie[5].ACLR
apb_resetn => break_error_ie[0].ACLR
apb_resetn => break_error_ie[1].ACLR
apb_resetn => break_error_ie[2].ACLR
apb_resetn => break_error_ie[3].ACLR
apb_resetn => break_error_ie[4].ACLR
apb_resetn => break_error_ie[5].ACLR
apb_resetn => parity_error_ie[0].ACLR
apb_resetn => parity_error_ie[1].ACLR
apb_resetn => parity_error_ie[2].ACLR
apb_resetn => parity_error_ie[3].ACLR
apb_resetn => parity_error_ie[4].ACLR
apb_resetn => parity_error_ie[5].ACLR
apb_resetn => framing_error_ie[0].ACLR
apb_resetn => framing_error_ie[1].ACLR
apb_resetn => framing_error_ie[2].ACLR
apb_resetn => framing_error_ie[3].ACLR
apb_resetn => framing_error_ie[4].ACLR
apb_resetn => framing_error_ie[5].ACLR
apb_resetn => rx_idle_ie[0].ACLR
apb_resetn => rx_idle_ie[1].ACLR
apb_resetn => rx_idle_ie[2].ACLR
apb_resetn => rx_idle_ie[3].ACLR
apb_resetn => rx_idle_ie[4].ACLR
apb_resetn => rx_idle_ie[5].ACLR
apb_resetn => tx_complete_ie[0].ACLR
apb_resetn => tx_complete_ie[1].ACLR
apb_resetn => tx_complete_ie[2].ACLR
apb_resetn => tx_complete_ie[3].ACLR
apb_resetn => tx_complete_ie[4].ACLR
apb_resetn => tx_complete_ie[5].ACLR
apb_resetn => tx_not_full_ie[0].ACLR
apb_resetn => tx_not_full_ie[1].ACLR
apb_resetn => tx_not_full_ie[2].ACLR
apb_resetn => tx_not_full_ie[3].ACLR
apb_resetn => tx_not_full_ie[4].ACLR
apb_resetn => tx_not_full_ie[5].ACLR
apb_resetn => rx_not_empty_ie[0].ACLR
apb_resetn => rx_not_empty_ie[1].ACLR
apb_resetn => rx_not_empty_ie[2].ACLR
apb_resetn => rx_not_empty_ie[3].ACLR
apb_resetn => rx_not_empty_ie[4].ACLR
apb_resetn => rx_not_empty_ie[5].ACLR
apb_psel => comb.IN0
apb_psel => comb.IN0
apb_penable => comb.IN1
apb_penable => comb.IN1
apb_pwrite => apb_write.IN1
apb_pwrite => apb_read1.IN1
apb_pwrite => apb_read0.IN1
apb_paddr[0] => ~NO_FANOUT~
apb_paddr[1] => ~NO_FANOUT~
apb_paddr[2] => Decoder1.IN5
apb_paddr[2] => Equal0.IN1
apb_paddr[2] => Equal1.IN7
apb_paddr[2] => Equal2.IN7
apb_paddr[2] => Equal3.IN2
apb_paddr[2] => Equal4.IN7
apb_paddr[2] => Equal5.IN7
apb_paddr[2] => Equal6.IN7
apb_paddr[2] => Equal7.IN0
apb_paddr[2] => Equal8.IN1
apb_paddr[3] => Decoder1.IN4
apb_paddr[3] => Equal0.IN7
apb_paddr[3] => Equal1.IN1
apb_paddr[3] => Equal2.IN6
apb_paddr[3] => Equal3.IN1
apb_paddr[3] => Equal4.IN6
apb_paddr[3] => Equal5.IN2
apb_paddr[3] => Equal6.IN1
apb_paddr[3] => Equal7.IN7
apb_paddr[3] => Equal8.IN7
apb_paddr[4] => Decoder1.IN3
apb_paddr[4] => Equal0.IN6
apb_paddr[4] => Equal1.IN6
apb_paddr[4] => Equal2.IN5
apb_paddr[4] => Equal3.IN7
apb_paddr[4] => Equal4.IN1
apb_paddr[4] => Equal5.IN1
apb_paddr[4] => Equal6.IN6
apb_paddr[4] => Equal7.IN6
apb_paddr[4] => Equal8.IN6
apb_paddr[5] => Decoder1.IN2
apb_paddr[5] => Equal0.IN0
apb_paddr[5] => Equal1.IN0
apb_paddr[5] => Equal2.IN4
apb_paddr[5] => Equal3.IN0
apb_paddr[5] => Equal4.IN0
apb_paddr[5] => Equal5.IN0
apb_paddr[5] => Equal6.IN5
apb_paddr[5] => Equal7.IN5
apb_paddr[5] => Equal8.IN5
apb_paddr[6] => Decoder1.IN1
apb_paddr[6] => Equal0.IN5
apb_paddr[6] => Equal1.IN5
apb_paddr[6] => Equal2.IN3
apb_paddr[6] => Equal3.IN6
apb_paddr[6] => Equal4.IN5
apb_paddr[6] => Equal5.IN6
apb_paddr[6] => Equal6.IN0
apb_paddr[6] => Equal7.IN4
apb_paddr[6] => Equal8.IN0
apb_paddr[7] => Decoder1.IN0
apb_paddr[7] => Equal0.IN4
apb_paddr[7] => Equal1.IN4
apb_paddr[7] => Equal2.IN2
apb_paddr[7] => Equal3.IN5
apb_paddr[7] => Equal4.IN4
apb_paddr[7] => Equal5.IN5
apb_paddr[7] => Equal6.IN4
apb_paddr[7] => Equal7.IN3
apb_paddr[7] => Equal8.IN4
apb_paddr[8] => ShiftLeft0.IN9
apb_paddr[8] => Decoder0.IN2
apb_paddr[8] => Mux0.IN69
apb_paddr[8] => Mux1.IN69
apb_paddr[8] => Mux2.IN69
apb_paddr[8] => Mux3.IN69
apb_paddr[8] => Mux4.IN69
apb_paddr[8] => Mux5.IN69
apb_paddr[8] => Mux6.IN69
apb_paddr[8] => Mux7.IN69
apb_paddr[8] => Mux8.IN10
apb_paddr[8] => Mux9.IN10
apb_paddr[8] => Mux10.IN10
apb_paddr[8] => Mux11.IN10
apb_paddr[8] => Mux12.IN10
apb_paddr[8] => Mux13.IN10
apb_paddr[8] => Mux14.IN10
apb_paddr[8] => Mux15.IN10
apb_paddr[8] => Mux16.IN10
apb_paddr[8] => Mux17.IN10
apb_paddr[8] => Mux18.IN10
apb_paddr[8] => Mux19.IN10
apb_paddr[8] => Mux20.IN10
apb_paddr[8] => Mux21.IN10
apb_paddr[8] => Mux22.IN10
apb_paddr[8] => Mux23.IN10
apb_paddr[8] => Mux24.IN10
apb_paddr[8] => Mux25.IN10
apb_paddr[8] => Mux26.IN10
apb_paddr[8] => Mux27.IN10
apb_paddr[8] => Mux28.IN10
apb_paddr[8] => ShiftLeft1.IN35
apb_paddr[9] => ShiftLeft0.IN8
apb_paddr[9] => Decoder0.IN1
apb_paddr[9] => Mux0.IN68
apb_paddr[9] => Mux1.IN68
apb_paddr[9] => Mux2.IN68
apb_paddr[9] => Mux3.IN68
apb_paddr[9] => Mux4.IN68
apb_paddr[9] => Mux5.IN68
apb_paddr[9] => Mux6.IN68
apb_paddr[9] => Mux7.IN68
apb_paddr[9] => Mux8.IN9
apb_paddr[9] => Mux9.IN9
apb_paddr[9] => Mux10.IN9
apb_paddr[9] => Mux11.IN9
apb_paddr[9] => Mux12.IN9
apb_paddr[9] => Mux13.IN9
apb_paddr[9] => Mux14.IN9
apb_paddr[9] => Mux15.IN9
apb_paddr[9] => Mux16.IN9
apb_paddr[9] => Mux17.IN9
apb_paddr[9] => Mux18.IN9
apb_paddr[9] => Mux19.IN9
apb_paddr[9] => Mux20.IN9
apb_paddr[9] => Mux21.IN9
apb_paddr[9] => Mux22.IN9
apb_paddr[9] => Mux23.IN9
apb_paddr[9] => Mux24.IN9
apb_paddr[9] => Mux25.IN9
apb_paddr[9] => Mux26.IN9
apb_paddr[9] => Mux27.IN9
apb_paddr[9] => Mux28.IN9
apb_paddr[9] => ShiftLeft1.IN34
apb_paddr[10] => ShiftLeft0.IN7
apb_paddr[10] => Decoder0.IN0
apb_paddr[10] => Mux0.IN67
apb_paddr[10] => Mux1.IN67
apb_paddr[10] => Mux2.IN67
apb_paddr[10] => Mux3.IN67
apb_paddr[10] => Mux4.IN67
apb_paddr[10] => Mux5.IN67
apb_paddr[10] => Mux6.IN67
apb_paddr[10] => Mux7.IN67
apb_paddr[10] => Mux8.IN8
apb_paddr[10] => Mux9.IN8
apb_paddr[10] => Mux10.IN8
apb_paddr[10] => Mux11.IN8
apb_paddr[10] => Mux12.IN8
apb_paddr[10] => Mux13.IN8
apb_paddr[10] => Mux14.IN8
apb_paddr[10] => Mux15.IN8
apb_paddr[10] => Mux16.IN8
apb_paddr[10] => Mux17.IN8
apb_paddr[10] => Mux18.IN8
apb_paddr[10] => Mux19.IN8
apb_paddr[10] => Mux20.IN8
apb_paddr[10] => Mux21.IN8
apb_paddr[10] => Mux22.IN8
apb_paddr[10] => Mux23.IN8
apb_paddr[10] => Mux24.IN8
apb_paddr[10] => Mux25.IN8
apb_paddr[10] => Mux26.IN8
apb_paddr[10] => Mux27.IN8
apb_paddr[10] => Mux28.IN8
apb_paddr[10] => ShiftLeft1.IN33
apb_paddr[11] => ~NO_FANOUT~
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => ibrd[0]~reg0.DATAIN
apb_pwdata[0] => fbrd[0]~reg0.DATAIN
apb_pwdata[0] => uart_en~reg0.DATAIN
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => ibrd[1]~reg0.DATAIN
apb_pwdata[1] => fbrd[1]~reg0.DATAIN
apb_pwdata[1] => lcr_pen~reg0.DATAIN
apb_pwdata[2] => ibrd[2]~reg0.DATAIN
apb_pwdata[2] => fbrd[2]~reg0.DATAIN
apb_pwdata[2] => lcr_eps~reg0.DATAIN
apb_pwdata[3] => ibrd[3]~reg0.DATAIN
apb_pwdata[3] => fbrd[3]~reg0.DATAIN
apb_pwdata[3] => lcr_stp2~reg0.DATAIN
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => ibrd[4]~reg0.DATAIN
apb_pwdata[4] => fbrd[4]~reg0.DATAIN
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => ibrd[5]~reg0.DATAIN
apb_pwdata[5] => fbrd[5]~reg0.DATAIN
apb_pwdata[6] => ibrd[6]~reg0.DATAIN
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => ibrd[7]~reg0.DATAIN
apb_pwdata[7] => lcr_sps~reg0.DATAIN
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => ibrd[8]~reg0.DATAIN
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => ibrd[9]~reg0.DATAIN
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => ibrd[10]~reg0.DATAIN
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => ibrd[11]~reg0.DATAIN
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => ibrd[12]~reg0.DATAIN
apb_pwdata[13] => ibrd[13]~reg0.DATAIN
apb_pwdata[14] => ibrd[14]~reg0.DATAIN
apb_pwdata[15] => ibrd[15]~reg0.DATAIN
apb_pwdata[16] => ~NO_FANOUT~
apb_pwdata[17] => ~NO_FANOUT~
apb_pwdata[18] => ~NO_FANOUT~
apb_pwdata[19] => ~NO_FANOUT~
apb_pwdata[20] => ~NO_FANOUT~
apb_pwdata[21] => ~NO_FANOUT~
apb_pwdata[22] => ~NO_FANOUT~
apb_pwdata[23] => ~NO_FANOUT~
apb_pwdata[24] => ~NO_FANOUT~
apb_pwdata[25] => ~NO_FANOUT~
apb_pwdata[26] => ~NO_FANOUT~
apb_pwdata[27] => ~NO_FANOUT~
apb_pwdata[28] => ~NO_FANOUT~
apb_pwdata[29] => ~NO_FANOUT~
apb_pwdata[30] => ~NO_FANOUT~
apb_pwdata[31] => ~NO_FANOUT~
apb_prdata[0] <= apb_prdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[1] <= apb_prdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[2] <= apb_prdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[3] <= apb_prdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[4] <= apb_prdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[5] <= apb_prdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[6] <= apb_prdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[7] <= apb_prdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[8] <= apb_prdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[9] <= apb_prdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[10] <= apb_prdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[11] <= apb_prdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[12] <= apb_prdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[13] <= apb_prdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[14] <= apb_prdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[15] <= apb_prdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[16] <= apb_prdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[17] <= apb_prdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[18] <= apb_prdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[19] <= apb_prdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[20] <= apb_prdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[21] <= apb_prdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[22] <= apb_prdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[23] <= apb_prdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[24] <= apb_prdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[25] <= apb_prdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[26] <= apb_prdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[27] <= apb_prdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[28] <= apb_prdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[29] <= apb_prdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[30] <= apb_prdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[31] <= apb_prdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_pready <= apb_pready~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_en <= uart_en~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[0] <= ibrd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[1] <= ibrd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[2] <= ibrd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[3] <= ibrd[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[4] <= ibrd[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[5] <= ibrd[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[6] <= ibrd[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[7] <= ibrd[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[8] <= ibrd[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[9] <= ibrd[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[10] <= ibrd[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[11] <= ibrd[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[12] <= ibrd[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[13] <= ibrd[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[14] <= ibrd[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[15] <= ibrd[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[0] <= fbrd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[1] <= fbrd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[2] <= fbrd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[3] <= fbrd[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[4] <= fbrd[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[5] <= fbrd[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[0] <= tx_write[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[1] <= tx_write[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[2] <= tx_write[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[3] <= tx_write[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[4] <= tx_write[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[5] <= tx_write[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[0] <= rx_read[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[1] <= rx_read[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[2] <= rx_read[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[3] <= rx_read[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[4] <= rx_read[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[5] <= rx_read[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[0] => Mux0.IN59
rx_data[1] => Mux1.IN59
rx_data[2] => Mux2.IN59
rx_data[3] => Mux3.IN59
rx_data[4] => Mux4.IN59
rx_data[5] => Mux5.IN59
rx_data[6] => Mux6.IN59
rx_data[7] => Mux7.IN59
rx_data[8] => Mux0.IN51
rx_data[9] => Mux1.IN51
rx_data[10] => Mux2.IN51
rx_data[11] => Mux3.IN51
rx_data[12] => Mux4.IN51
rx_data[13] => Mux5.IN51
rx_data[14] => Mux6.IN51
rx_data[15] => Mux7.IN51
rx_data[16] => Mux0.IN43
rx_data[17] => Mux1.IN43
rx_data[18] => Mux2.IN43
rx_data[19] => Mux3.IN43
rx_data[20] => Mux4.IN43
rx_data[21] => Mux5.IN43
rx_data[22] => Mux6.IN43
rx_data[23] => Mux7.IN43
rx_data[24] => Mux0.IN35
rx_data[25] => Mux1.IN35
rx_data[26] => Mux2.IN35
rx_data[27] => Mux3.IN35
rx_data[28] => Mux4.IN35
rx_data[29] => Mux5.IN35
rx_data[30] => Mux6.IN35
rx_data[31] => Mux7.IN35
rx_data[32] => Mux0.IN27
rx_data[33] => Mux1.IN27
rx_data[34] => Mux2.IN27
rx_data[35] => Mux3.IN27
rx_data[36] => Mux4.IN27
rx_data[37] => Mux5.IN27
rx_data[38] => Mux6.IN27
rx_data[39] => Mux7.IN27
rx_data[40] => Mux0.IN19
rx_data[41] => Mux1.IN19
rx_data[42] => Mux2.IN19
rx_data[43] => Mux3.IN19
rx_data[44] => Mux4.IN19
rx_data[45] => Mux5.IN19
rx_data[46] => Mux6.IN19
rx_data[47] => Mux7.IN19
tx_full[0] => Mux10.IN7
tx_full[0] => interrupts.IN1
tx_full[1] => Mux10.IN6
tx_full[1] => interrupts.IN1
tx_full[2] => Mux10.IN5
tx_full[2] => interrupts.IN1
tx_full[3] => Mux10.IN4
tx_full[3] => interrupts.IN1
tx_full[4] => Mux10.IN3
tx_full[4] => interrupts.IN1
tx_full[5] => Mux10.IN2
tx_full[5] => interrupts.IN1
tx_empty[0] => Mux8.IN7
tx_empty[1] => Mux8.IN6
tx_empty[2] => Mux8.IN5
tx_empty[3] => Mux8.IN4
tx_empty[4] => Mux8.IN3
tx_empty[5] => Mux8.IN2
tx_busy[0] => Mux12.IN7
tx_busy[1] => Mux12.IN6
tx_busy[2] => Mux12.IN5
tx_busy[3] => Mux12.IN4
tx_busy[4] => Mux12.IN3
tx_busy[5] => Mux12.IN2
tx_complete[0] => interrupts.IN1
tx_complete[0] => Mux13.IN7
tx_complete[1] => interrupts.IN1
tx_complete[1] => Mux13.IN6
tx_complete[2] => interrupts.IN1
tx_complete[2] => Mux13.IN5
tx_complete[3] => interrupts.IN1
tx_complete[3] => Mux13.IN4
tx_complete[4] => interrupts.IN1
tx_complete[4] => Mux13.IN3
tx_complete[5] => interrupts.IN1
tx_complete[5] => Mux13.IN2
rx_full[0] => Mux9.IN7
rx_full[1] => Mux9.IN6
rx_full[2] => Mux9.IN5
rx_full[3] => Mux9.IN4
rx_full[4] => Mux9.IN3
rx_full[5] => Mux9.IN2
rx_empty[0] => Mux11.IN7
rx_empty[0] => interrupts.IN1
rx_empty[1] => Mux11.IN6
rx_empty[1] => interrupts.IN1
rx_empty[2] => Mux11.IN5
rx_empty[2] => interrupts.IN1
rx_empty[3] => Mux11.IN4
rx_empty[3] => interrupts.IN1
rx_empty[4] => Mux11.IN3
rx_empty[4] => interrupts.IN1
rx_empty[5] => Mux11.IN2
rx_empty[5] => interrupts.IN1
rx_idle[0] => interrupts.IN1
rx_idle[0] => Mux14.IN7
rx_idle[1] => interrupts.IN1
rx_idle[1] => Mux14.IN6
rx_idle[2] => interrupts.IN1
rx_idle[2] => Mux14.IN5
rx_idle[3] => interrupts.IN1
rx_idle[3] => Mux14.IN4
rx_idle[4] => interrupts.IN1
rx_idle[4] => Mux14.IN3
rx_idle[5] => interrupts.IN1
rx_idle[5] => Mux14.IN2
framing_error[0] => interrupts.IN1
framing_error[0] => Mux18.IN7
framing_error[1] => interrupts.IN1
framing_error[1] => Mux18.IN6
framing_error[2] => interrupts.IN1
framing_error[2] => Mux18.IN5
framing_error[3] => interrupts.IN1
framing_error[3] => Mux18.IN4
framing_error[4] => interrupts.IN1
framing_error[4] => Mux18.IN3
framing_error[5] => interrupts.IN1
framing_error[5] => Mux18.IN2
parity_error[0] => interrupts.IN1
parity_error[0] => Mux17.IN7
parity_error[1] => interrupts.IN1
parity_error[1] => Mux17.IN6
parity_error[2] => interrupts.IN1
parity_error[2] => Mux17.IN5
parity_error[3] => interrupts.IN1
parity_error[3] => Mux17.IN4
parity_error[4] => interrupts.IN1
parity_error[4] => Mux17.IN3
parity_error[5] => interrupts.IN1
parity_error[5] => Mux17.IN2
break_error[0] => interrupts.IN1
break_error[0] => Mux16.IN7
break_error[1] => interrupts.IN1
break_error[1] => Mux16.IN6
break_error[2] => interrupts.IN1
break_error[2] => Mux16.IN5
break_error[3] => interrupts.IN1
break_error[3] => Mux16.IN4
break_error[4] => interrupts.IN1
break_error[4] => Mux16.IN3
break_error[5] => interrupts.IN1
break_error[5] => Mux16.IN2
overrun_error[0] => interrupts.IN1
overrun_error[0] => Mux15.IN7
overrun_error[1] => interrupts.IN1
overrun_error[1] => Mux15.IN6
overrun_error[2] => interrupts.IN1
overrun_error[2] => Mux15.IN5
overrun_error[3] => interrupts.IN1
overrun_error[3] => Mux15.IN4
overrun_error[4] => interrupts.IN1
overrun_error[4] => Mux15.IN3
overrun_error[5] => interrupts.IN1
overrun_error[5] => Mux15.IN2
clear_flags[0] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[1] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[2] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[3] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[4] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[5] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
lcr_sps <= lcr_sps~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcr_stp2 <= lcr_stp2~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcr_eps <= lcr_eps~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcr_pen <= lcr_pen~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[0] <= rx_dma_en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[1] <= rx_dma_en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[2] <= rx_dma_en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[3] <= rx_dma_en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[4] <= rx_dma_en[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[5] <= rx_dma_en[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[0] <= tx_dma_en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[1] <= tx_dma_en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[2] <= tx_dma_en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[3] <= tx_dma_en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[4] <= tx_dma_en[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[5] <= tx_dma_en[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[0] <= interrupts[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[1] <= interrupts[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[2] <= interrupts[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[3] <= interrupts[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[4] <= interrupts[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[5] <= interrupts[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]
apb_clock => apb_clock.IN2
apb_resetn => apb_resetn.IN2
apb_psel => apb_psel.IN1
apb_penable => apb_penable.IN1
apb_pwrite => apb_pwrite.IN1
apb_paddr[0] => apb_paddr[0].IN1
apb_paddr[1] => apb_paddr[1].IN1
apb_paddr[2] => apb_paddr[2].IN1
apb_paddr[3] => apb_paddr[3].IN1
apb_paddr[4] => apb_paddr[4].IN1
apb_paddr[5] => apb_paddr[5].IN1
apb_paddr[6] => apb_paddr[6].IN1
apb_paddr[7] => apb_paddr[7].IN1
apb_paddr[8] => apb_paddr[8].IN1
apb_paddr[9] => apb_paddr[9].IN1
apb_paddr[10] => apb_paddr[10].IN1
apb_paddr[11] => apb_paddr[11].IN1
apb_pwdata[0] => apb_pwdata[0].IN1
apb_pwdata[1] => apb_pwdata[1].IN1
apb_pwdata[2] => apb_pwdata[2].IN1
apb_pwdata[3] => apb_pwdata[3].IN1
apb_pwdata[4] => apb_pwdata[4].IN1
apb_pwdata[5] => apb_pwdata[5].IN1
apb_pwdata[6] => apb_pwdata[6].IN1
apb_pwdata[7] => apb_pwdata[7].IN1
apb_pwdata[8] => apb_pwdata[8].IN1
apb_pwdata[9] => apb_pwdata[9].IN1
apb_pwdata[10] => apb_pwdata[10].IN1
apb_pwdata[11] => apb_pwdata[11].IN1
apb_pwdata[12] => apb_pwdata[12].IN1
apb_pwdata[13] => apb_pwdata[13].IN1
apb_pwdata[14] => apb_pwdata[14].IN1
apb_pwdata[15] => apb_pwdata[15].IN1
apb_pwdata[16] => apb_pwdata[16].IN1
apb_pwdata[17] => apb_pwdata[17].IN1
apb_pwdata[18] => apb_pwdata[18].IN1
apb_pwdata[19] => apb_pwdata[19].IN1
apb_pwdata[20] => apb_pwdata[20].IN1
apb_pwdata[21] => apb_pwdata[21].IN1
apb_pwdata[22] => apb_pwdata[22].IN1
apb_pwdata[23] => apb_pwdata[23].IN1
apb_pwdata[24] => apb_pwdata[24].IN1
apb_pwdata[25] => apb_pwdata[25].IN1
apb_pwdata[26] => apb_pwdata[26].IN1
apb_pwdata[27] => apb_pwdata[27].IN1
apb_pwdata[28] => apb_pwdata[28].IN1
apb_pwdata[29] => apb_pwdata[29].IN1
apb_pwdata[30] => apb_pwdata[30].IN1
apb_pwdata[31] => apb_pwdata[31].IN1
apb_prdata[0] <= uart_regs:u_regs.apb_prdata
apb_prdata[1] <= uart_regs:u_regs.apb_prdata
apb_prdata[2] <= uart_regs:u_regs.apb_prdata
apb_prdata[3] <= uart_regs:u_regs.apb_prdata
apb_prdata[4] <= uart_regs:u_regs.apb_prdata
apb_prdata[5] <= uart_regs:u_regs.apb_prdata
apb_prdata[6] <= uart_regs:u_regs.apb_prdata
apb_prdata[7] <= uart_regs:u_regs.apb_prdata
apb_prdata[8] <= uart_regs:u_regs.apb_prdata
apb_prdata[9] <= uart_regs:u_regs.apb_prdata
apb_prdata[10] <= uart_regs:u_regs.apb_prdata
apb_prdata[11] <= uart_regs:u_regs.apb_prdata
apb_prdata[12] <= uart_regs:u_regs.apb_prdata
apb_prdata[13] <= uart_regs:u_regs.apb_prdata
apb_prdata[14] <= uart_regs:u_regs.apb_prdata
apb_prdata[15] <= uart_regs:u_regs.apb_prdata
apb_prdata[16] <= uart_regs:u_regs.apb_prdata
apb_prdata[17] <= uart_regs:u_regs.apb_prdata
apb_prdata[18] <= uart_regs:u_regs.apb_prdata
apb_prdata[19] <= uart_regs:u_regs.apb_prdata
apb_prdata[20] <= uart_regs:u_regs.apb_prdata
apb_prdata[21] <= uart_regs:u_regs.apb_prdata
apb_prdata[22] <= uart_regs:u_regs.apb_prdata
apb_prdata[23] <= uart_regs:u_regs.apb_prdata
apb_prdata[24] <= uart_regs:u_regs.apb_prdata
apb_prdata[25] <= uart_regs:u_regs.apb_prdata
apb_prdata[26] <= uart_regs:u_regs.apb_prdata
apb_prdata[27] <= uart_regs:u_regs.apb_prdata
apb_prdata[28] <= uart_regs:u_regs.apb_prdata
apb_prdata[29] <= uart_regs:u_regs.apb_prdata
apb_prdata[30] <= uart_regs:u_regs.apb_prdata
apb_prdata[31] <= uart_regs:u_regs.apb_prdata
apb_pready <= uart_regs:u_regs.apb_pready
uart_txd[0] <= uart_tx:u_tx[0].uart_txd
uart_txd[1] <= uart_tx:u_tx[1].uart_txd
uart_txd[2] <= uart_tx:u_tx[2].uart_txd
uart_txd[3] <= uart_tx:u_tx[3].uart_txd
uart_txd[4] <= uart_tx:u_tx[4].uart_txd
uart_txd[5] <= uart_tx:u_tx[5].uart_txd
uart_rxd[0] => uart_rx:u_rx[0].uart_rxd
uart_rxd[1] => uart_rx:u_rx[1].uart_rxd
uart_rxd[2] => uart_rx:u_rx[2].uart_rxd
uart_rxd[3] => uart_rx:u_rx[3].uart_rxd
uart_rxd[4] => uart_rx:u_rx[4].uart_rxd
uart_rxd[5] => uart_rx:u_rx[5].uart_rxd
tx_dma_clr[0] => uart_tx:u_tx[0].tx_dma_clr
tx_dma_clr[1] => uart_tx:u_tx[1].tx_dma_clr
tx_dma_clr[2] => uart_tx:u_tx[2].tx_dma_clr
tx_dma_clr[3] => uart_tx:u_tx[3].tx_dma_clr
tx_dma_clr[4] => uart_tx:u_tx[4].tx_dma_clr
tx_dma_clr[5] => uart_tx:u_tx[5].tx_dma_clr
tx_dma_req[0] <= uart_tx:u_tx[0].tx_dma_req
tx_dma_req[1] <= uart_tx:u_tx[1].tx_dma_req
tx_dma_req[2] <= uart_tx:u_tx[2].tx_dma_req
tx_dma_req[3] <= uart_tx:u_tx[3].tx_dma_req
tx_dma_req[4] <= uart_tx:u_tx[4].tx_dma_req
tx_dma_req[5] <= uart_tx:u_tx[5].tx_dma_req
rx_dma_clr[0] => uart_rx:u_rx[0].rx_dma_clr
rx_dma_clr[1] => uart_rx:u_rx[1].rx_dma_clr
rx_dma_clr[2] => uart_rx:u_rx[2].rx_dma_clr
rx_dma_clr[3] => uart_rx:u_rx[3].rx_dma_clr
rx_dma_clr[4] => uart_rx:u_rx[4].rx_dma_clr
rx_dma_clr[5] => uart_rx:u_rx[5].rx_dma_clr
rx_dma_req[0] <= uart_rx:u_rx[0].rx_dma_req
rx_dma_req[1] <= uart_rx:u_rx[1].rx_dma_req
rx_dma_req[2] <= uart_rx:u_rx[2].rx_dma_req
rx_dma_req[3] <= uart_rx:u_rx[3].rx_dma_req
rx_dma_req[4] <= uart_rx:u_rx[4].rx_dma_req
rx_dma_req[5] <= uart_rx:u_rx[5].rx_dma_req
interrupts[0] <= uart_regs:u_regs.interrupts
interrupts[1] <= uart_regs:u_regs.interrupts
interrupts[2] <= uart_regs:u_regs.interrupts
interrupts[3] <= uart_regs:u_regs.interrupts
interrupts[4] <= uart_regs:u_regs.interrupts
interrupts[5] <= uart_regs:u_regs.interrupts
uart_tx_busy[0] <= tx_busy[0].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[1] <= tx_busy[1].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[2] <= tx_busy[2].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[3] <= tx_busy[3].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[4] <= tx_busy[4].DB_MAX_OUTPUT_PORT_TYPE
uart_tx_busy[5] <= tx_busy[5].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|baud_gen:u_baud
clk => f_del.CLK
clk => baud16~reg0.CLK
clk => f_cnt[0].CLK
clk => f_cnt[1].CLK
clk => f_cnt[2].CLK
clk => f_cnt[3].CLK
clk => f_cnt[4].CLK
clk => f_cnt[5].CLK
clk => i_cnt[0].CLK
clk => i_cnt[1].CLK
clk => i_cnt[2].CLK
clk => i_cnt[3].CLK
clk => i_cnt[4].CLK
clk => i_cnt[5].CLK
clk => i_cnt[6].CLK
clk => i_cnt[7].CLK
clk => i_cnt[8].CLK
clk => i_cnt[9].CLK
clk => i_cnt[10].CLK
clk => i_cnt[11].CLK
clk => i_cnt[12].CLK
clk => i_cnt[13].CLK
clk => i_cnt[14].CLK
clk => i_cnt[15].CLK
rstn => i_cnt[0].PRESET
rstn => i_cnt[1].ACLR
rstn => i_cnt[2].ACLR
rstn => i_cnt[3].ACLR
rstn => i_cnt[4].ACLR
rstn => i_cnt[5].ACLR
rstn => i_cnt[6].ACLR
rstn => i_cnt[7].ACLR
rstn => i_cnt[8].ACLR
rstn => i_cnt[9].ACLR
rstn => i_cnt[10].ACLR
rstn => i_cnt[11].ACLR
rstn => i_cnt[12].ACLR
rstn => i_cnt[13].ACLR
rstn => i_cnt[14].ACLR
rstn => i_cnt[15].ACLR
rstn => baud16~reg0.ACLR
rstn => f_cnt[0].ACLR
rstn => f_cnt[1].ACLR
rstn => f_cnt[2].ACLR
rstn => f_cnt[3].ACLR
rstn => f_cnt[4].ACLR
rstn => f_cnt[5].ACLR
rstn => f_del.ACLR
ibrd[0] => i_cnt.DATAB
ibrd[1] => i_cnt.DATAB
ibrd[2] => i_cnt.DATAB
ibrd[3] => i_cnt.DATAB
ibrd[4] => i_cnt.DATAB
ibrd[5] => i_cnt.DATAB
ibrd[6] => i_cnt.DATAB
ibrd[7] => i_cnt.DATAB
ibrd[8] => i_cnt.DATAB
ibrd[9] => i_cnt.DATAB
ibrd[10] => i_cnt.DATAB
ibrd[11] => i_cnt.DATAB
ibrd[12] => i_cnt.DATAB
ibrd[13] => i_cnt.DATAB
ibrd[14] => i_cnt.DATAB
ibrd[15] => i_cnt.DATAB
fbrd[0] => LessThan0.IN6
fbrd[1] => LessThan0.IN5
fbrd[2] => LessThan0.IN4
fbrd[3] => LessThan0.IN3
fbrd[4] => LessThan0.IN2
fbrd[5] => LessThan0.IN1
stop => always0.IN1
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => f_cnt.OUTPUTSELECT
stop => always2.IN1
baud16 <= baud16~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs
apb_clock => apb_prdata[0]~reg0.CLK
apb_clock => apb_prdata[1]~reg0.CLK
apb_clock => apb_prdata[2]~reg0.CLK
apb_clock => apb_prdata[3]~reg0.CLK
apb_clock => apb_prdata[4]~reg0.CLK
apb_clock => apb_prdata[5]~reg0.CLK
apb_clock => apb_prdata[6]~reg0.CLK
apb_clock => apb_prdata[7]~reg0.CLK
apb_clock => apb_prdata[8]~reg0.CLK
apb_clock => apb_prdata[9]~reg0.CLK
apb_clock => apb_prdata[10]~reg0.CLK
apb_clock => apb_prdata[11]~reg0.CLK
apb_clock => apb_prdata[12]~reg0.CLK
apb_clock => apb_prdata[13]~reg0.CLK
apb_clock => apb_prdata[14]~reg0.CLK
apb_clock => apb_prdata[15]~reg0.CLK
apb_clock => apb_prdata[16]~reg0.CLK
apb_clock => apb_prdata[17]~reg0.CLK
apb_clock => apb_prdata[18]~reg0.CLK
apb_clock => apb_prdata[19]~reg0.CLK
apb_clock => apb_prdata[20]~reg0.CLK
apb_clock => apb_prdata[21]~reg0.CLK
apb_clock => apb_prdata[22]~reg0.CLK
apb_clock => apb_prdata[23]~reg0.CLK
apb_clock => apb_prdata[24]~reg0.CLK
apb_clock => apb_prdata[25]~reg0.CLK
apb_clock => apb_prdata[26]~reg0.CLK
apb_clock => apb_prdata[27]~reg0.CLK
apb_clock => apb_prdata[28]~reg0.CLK
apb_clock => apb_prdata[29]~reg0.CLK
apb_clock => apb_prdata[30]~reg0.CLK
apb_clock => apb_prdata[31]~reg0.CLK
apb_clock => status_reg[0].CLK
apb_clock => status_reg[1].CLK
apb_clock => status_reg[2].CLK
apb_clock => status_reg[3].CLK
apb_clock => status_reg[4].CLK
apb_clock => rx_reg[0].CLK
apb_clock => rx_reg[1].CLK
apb_clock => rx_reg[2].CLK
apb_clock => rx_reg[3].CLK
apb_clock => rx_reg[4].CLK
apb_clock => rx_reg[5].CLK
apb_clock => rx_reg[6].CLK
apb_clock => rx_reg[7].CLK
apb_clock => interrupts[0]~reg0.CLK
apb_clock => interrupts[1]~reg0.CLK
apb_clock => interrupts[2]~reg0.CLK
apb_clock => interrupts[3]~reg0.CLK
apb_clock => interrupts[4]~reg0.CLK
apb_clock => interrupts[5]~reg0.CLK
apb_clock => tx_dma_en[0]~reg0.CLK
apb_clock => tx_dma_en[1]~reg0.CLK
apb_clock => tx_dma_en[2]~reg0.CLK
apb_clock => tx_dma_en[3]~reg0.CLK
apb_clock => tx_dma_en[4]~reg0.CLK
apb_clock => tx_dma_en[5]~reg0.CLK
apb_clock => rx_dma_en[0]~reg0.CLK
apb_clock => rx_dma_en[1]~reg0.CLK
apb_clock => rx_dma_en[2]~reg0.CLK
apb_clock => rx_dma_en[3]~reg0.CLK
apb_clock => rx_dma_en[4]~reg0.CLK
apb_clock => rx_dma_en[5]~reg0.CLK
apb_clock => overrun_error_ie[0].CLK
apb_clock => overrun_error_ie[1].CLK
apb_clock => overrun_error_ie[2].CLK
apb_clock => overrun_error_ie[3].CLK
apb_clock => overrun_error_ie[4].CLK
apb_clock => overrun_error_ie[5].CLK
apb_clock => break_error_ie[0].CLK
apb_clock => break_error_ie[1].CLK
apb_clock => break_error_ie[2].CLK
apb_clock => break_error_ie[3].CLK
apb_clock => break_error_ie[4].CLK
apb_clock => break_error_ie[5].CLK
apb_clock => parity_error_ie[0].CLK
apb_clock => parity_error_ie[1].CLK
apb_clock => parity_error_ie[2].CLK
apb_clock => parity_error_ie[3].CLK
apb_clock => parity_error_ie[4].CLK
apb_clock => parity_error_ie[5].CLK
apb_clock => framing_error_ie[0].CLK
apb_clock => framing_error_ie[1].CLK
apb_clock => framing_error_ie[2].CLK
apb_clock => framing_error_ie[3].CLK
apb_clock => framing_error_ie[4].CLK
apb_clock => framing_error_ie[5].CLK
apb_clock => rx_idle_ie[0].CLK
apb_clock => rx_idle_ie[1].CLK
apb_clock => rx_idle_ie[2].CLK
apb_clock => rx_idle_ie[3].CLK
apb_clock => rx_idle_ie[4].CLK
apb_clock => rx_idle_ie[5].CLK
apb_clock => tx_complete_ie[0].CLK
apb_clock => tx_complete_ie[1].CLK
apb_clock => tx_complete_ie[2].CLK
apb_clock => tx_complete_ie[3].CLK
apb_clock => tx_complete_ie[4].CLK
apb_clock => tx_complete_ie[5].CLK
apb_clock => tx_not_full_ie[0].CLK
apb_clock => tx_not_full_ie[1].CLK
apb_clock => tx_not_full_ie[2].CLK
apb_clock => tx_not_full_ie[3].CLK
apb_clock => tx_not_full_ie[4].CLK
apb_clock => tx_not_full_ie[5].CLK
apb_clock => rx_not_empty_ie[0].CLK
apb_clock => rx_not_empty_ie[1].CLK
apb_clock => rx_not_empty_ie[2].CLK
apb_clock => rx_not_empty_ie[3].CLK
apb_clock => rx_not_empty_ie[4].CLK
apb_clock => rx_not_empty_ie[5].CLK
apb_clock => uart_en~reg0.CLK
apb_clock => lcr_pen~reg0.CLK
apb_clock => lcr_eps~reg0.CLK
apb_clock => lcr_stp2~reg0.CLK
apb_clock => lcr_sps~reg0.CLK
apb_clock => rx_read[0]~reg0.CLK
apb_clock => rx_read[1]~reg0.CLK
apb_clock => rx_read[2]~reg0.CLK
apb_clock => rx_read[3]~reg0.CLK
apb_clock => rx_read[4]~reg0.CLK
apb_clock => rx_read[5]~reg0.CLK
apb_clock => tx_write[0]~reg0.CLK
apb_clock => tx_write[1]~reg0.CLK
apb_clock => tx_write[2]~reg0.CLK
apb_clock => tx_write[3]~reg0.CLK
apb_clock => tx_write[4]~reg0.CLK
apb_clock => tx_write[5]~reg0.CLK
apb_clock => fbrd[0]~reg0.CLK
apb_clock => fbrd[1]~reg0.CLK
apb_clock => fbrd[2]~reg0.CLK
apb_clock => fbrd[3]~reg0.CLK
apb_clock => fbrd[4]~reg0.CLK
apb_clock => fbrd[5]~reg0.CLK
apb_clock => ibrd[0]~reg0.CLK
apb_clock => ibrd[1]~reg0.CLK
apb_clock => ibrd[2]~reg0.CLK
apb_clock => ibrd[3]~reg0.CLK
apb_clock => ibrd[4]~reg0.CLK
apb_clock => ibrd[5]~reg0.CLK
apb_clock => ibrd[6]~reg0.CLK
apb_clock => ibrd[7]~reg0.CLK
apb_clock => ibrd[8]~reg0.CLK
apb_clock => ibrd[9]~reg0.CLK
apb_clock => ibrd[10]~reg0.CLK
apb_clock => ibrd[11]~reg0.CLK
apb_clock => ibrd[12]~reg0.CLK
apb_clock => ibrd[13]~reg0.CLK
apb_clock => ibrd[14]~reg0.CLK
apb_clock => ibrd[15]~reg0.CLK
apb_clock => apb_pready~reg0.CLK
apb_resetn => apb_prdata[0]~reg0.ACLR
apb_resetn => apb_prdata[1]~reg0.ACLR
apb_resetn => apb_prdata[2]~reg0.ACLR
apb_resetn => apb_prdata[3]~reg0.ACLR
apb_resetn => apb_prdata[4]~reg0.ACLR
apb_resetn => apb_prdata[5]~reg0.ACLR
apb_resetn => apb_prdata[6]~reg0.ACLR
apb_resetn => apb_prdata[7]~reg0.ACLR
apb_resetn => apb_prdata[8]~reg0.ACLR
apb_resetn => apb_prdata[9]~reg0.ACLR
apb_resetn => apb_prdata[10]~reg0.ACLR
apb_resetn => apb_prdata[11]~reg0.ACLR
apb_resetn => apb_prdata[12]~reg0.ACLR
apb_resetn => apb_prdata[13]~reg0.ACLR
apb_resetn => apb_prdata[14]~reg0.ACLR
apb_resetn => apb_prdata[15]~reg0.ACLR
apb_resetn => apb_prdata[16]~reg0.ACLR
apb_resetn => apb_prdata[17]~reg0.ACLR
apb_resetn => apb_prdata[18]~reg0.ACLR
apb_resetn => apb_prdata[19]~reg0.ACLR
apb_resetn => apb_prdata[20]~reg0.ACLR
apb_resetn => apb_prdata[21]~reg0.ACLR
apb_resetn => apb_prdata[22]~reg0.ACLR
apb_resetn => apb_prdata[23]~reg0.ACLR
apb_resetn => apb_prdata[24]~reg0.ACLR
apb_resetn => apb_prdata[25]~reg0.ACLR
apb_resetn => apb_prdata[26]~reg0.ACLR
apb_resetn => apb_prdata[27]~reg0.ACLR
apb_resetn => apb_prdata[28]~reg0.ACLR
apb_resetn => apb_prdata[29]~reg0.ACLR
apb_resetn => apb_prdata[30]~reg0.ACLR
apb_resetn => apb_prdata[31]~reg0.ACLR
apb_resetn => apb_pready~reg0.PRESET
apb_resetn => uart_en~reg0.ACLR
apb_resetn => ibrd[0]~reg0.ACLR
apb_resetn => ibrd[1]~reg0.ACLR
apb_resetn => ibrd[2]~reg0.ACLR
apb_resetn => ibrd[3]~reg0.ACLR
apb_resetn => ibrd[4]~reg0.ACLR
apb_resetn => ibrd[5]~reg0.ACLR
apb_resetn => ibrd[6]~reg0.ACLR
apb_resetn => ibrd[7]~reg0.ACLR
apb_resetn => ibrd[8]~reg0.ACLR
apb_resetn => ibrd[9]~reg0.ACLR
apb_resetn => ibrd[10]~reg0.ACLR
apb_resetn => ibrd[11]~reg0.ACLR
apb_resetn => ibrd[12]~reg0.ACLR
apb_resetn => ibrd[13]~reg0.ACLR
apb_resetn => ibrd[14]~reg0.ACLR
apb_resetn => ibrd[15]~reg0.ACLR
apb_resetn => fbrd[0]~reg0.ACLR
apb_resetn => fbrd[1]~reg0.ACLR
apb_resetn => fbrd[2]~reg0.ACLR
apb_resetn => fbrd[3]~reg0.ACLR
apb_resetn => fbrd[4]~reg0.ACLR
apb_resetn => fbrd[5]~reg0.ACLR
apb_resetn => tx_write[0]~reg0.ACLR
apb_resetn => tx_write[1]~reg0.ACLR
apb_resetn => tx_write[2]~reg0.ACLR
apb_resetn => tx_write[3]~reg0.ACLR
apb_resetn => tx_write[4]~reg0.ACLR
apb_resetn => tx_write[5]~reg0.ACLR
apb_resetn => rx_read[0]~reg0.ACLR
apb_resetn => rx_read[1]~reg0.ACLR
apb_resetn => rx_read[2]~reg0.ACLR
apb_resetn => rx_read[3]~reg0.ACLR
apb_resetn => rx_read[4]~reg0.ACLR
apb_resetn => rx_read[5]~reg0.ACLR
apb_resetn => lcr_pen~reg0.ACLR
apb_resetn => lcr_eps~reg0.ACLR
apb_resetn => lcr_stp2~reg0.ACLR
apb_resetn => lcr_sps~reg0.ACLR
apb_resetn => tx_dma_en[0]~reg0.ACLR
apb_resetn => tx_dma_en[1]~reg0.ACLR
apb_resetn => tx_dma_en[2]~reg0.ACLR
apb_resetn => tx_dma_en[3]~reg0.ACLR
apb_resetn => tx_dma_en[4]~reg0.ACLR
apb_resetn => tx_dma_en[5]~reg0.ACLR
apb_resetn => rx_dma_en[0]~reg0.ACLR
apb_resetn => rx_dma_en[1]~reg0.ACLR
apb_resetn => rx_dma_en[2]~reg0.ACLR
apb_resetn => rx_dma_en[3]~reg0.ACLR
apb_resetn => rx_dma_en[4]~reg0.ACLR
apb_resetn => rx_dma_en[5]~reg0.ACLR
apb_resetn => interrupts[0]~reg0.ACLR
apb_resetn => interrupts[1]~reg0.ACLR
apb_resetn => interrupts[2]~reg0.ACLR
apb_resetn => interrupts[3]~reg0.ACLR
apb_resetn => interrupts[4]~reg0.ACLR
apb_resetn => interrupts[5]~reg0.ACLR
apb_resetn => overrun_error_ie[0].ACLR
apb_resetn => overrun_error_ie[1].ACLR
apb_resetn => overrun_error_ie[2].ACLR
apb_resetn => overrun_error_ie[3].ACLR
apb_resetn => overrun_error_ie[4].ACLR
apb_resetn => overrun_error_ie[5].ACLR
apb_resetn => break_error_ie[0].ACLR
apb_resetn => break_error_ie[1].ACLR
apb_resetn => break_error_ie[2].ACLR
apb_resetn => break_error_ie[3].ACLR
apb_resetn => break_error_ie[4].ACLR
apb_resetn => break_error_ie[5].ACLR
apb_resetn => parity_error_ie[0].ACLR
apb_resetn => parity_error_ie[1].ACLR
apb_resetn => parity_error_ie[2].ACLR
apb_resetn => parity_error_ie[3].ACLR
apb_resetn => parity_error_ie[4].ACLR
apb_resetn => parity_error_ie[5].ACLR
apb_resetn => framing_error_ie[0].ACLR
apb_resetn => framing_error_ie[1].ACLR
apb_resetn => framing_error_ie[2].ACLR
apb_resetn => framing_error_ie[3].ACLR
apb_resetn => framing_error_ie[4].ACLR
apb_resetn => framing_error_ie[5].ACLR
apb_resetn => rx_idle_ie[0].ACLR
apb_resetn => rx_idle_ie[1].ACLR
apb_resetn => rx_idle_ie[2].ACLR
apb_resetn => rx_idle_ie[3].ACLR
apb_resetn => rx_idle_ie[4].ACLR
apb_resetn => rx_idle_ie[5].ACLR
apb_resetn => tx_complete_ie[0].ACLR
apb_resetn => tx_complete_ie[1].ACLR
apb_resetn => tx_complete_ie[2].ACLR
apb_resetn => tx_complete_ie[3].ACLR
apb_resetn => tx_complete_ie[4].ACLR
apb_resetn => tx_complete_ie[5].ACLR
apb_resetn => tx_not_full_ie[0].ACLR
apb_resetn => tx_not_full_ie[1].ACLR
apb_resetn => tx_not_full_ie[2].ACLR
apb_resetn => tx_not_full_ie[3].ACLR
apb_resetn => tx_not_full_ie[4].ACLR
apb_resetn => tx_not_full_ie[5].ACLR
apb_resetn => rx_not_empty_ie[0].ACLR
apb_resetn => rx_not_empty_ie[1].ACLR
apb_resetn => rx_not_empty_ie[2].ACLR
apb_resetn => rx_not_empty_ie[3].ACLR
apb_resetn => rx_not_empty_ie[4].ACLR
apb_resetn => rx_not_empty_ie[5].ACLR
apb_psel => comb.IN0
apb_psel => comb.IN0
apb_penable => comb.IN1
apb_penable => comb.IN1
apb_pwrite => apb_write.IN1
apb_pwrite => apb_read1.IN1
apb_pwrite => apb_read0.IN1
apb_paddr[0] => ~NO_FANOUT~
apb_paddr[1] => ~NO_FANOUT~
apb_paddr[2] => Decoder1.IN5
apb_paddr[2] => Equal0.IN1
apb_paddr[2] => Equal1.IN7
apb_paddr[2] => Equal2.IN7
apb_paddr[2] => Equal3.IN2
apb_paddr[2] => Equal4.IN7
apb_paddr[2] => Equal5.IN7
apb_paddr[2] => Equal6.IN7
apb_paddr[2] => Equal7.IN0
apb_paddr[2] => Equal8.IN1
apb_paddr[3] => Decoder1.IN4
apb_paddr[3] => Equal0.IN7
apb_paddr[3] => Equal1.IN1
apb_paddr[3] => Equal2.IN6
apb_paddr[3] => Equal3.IN1
apb_paddr[3] => Equal4.IN6
apb_paddr[3] => Equal5.IN2
apb_paddr[3] => Equal6.IN1
apb_paddr[3] => Equal7.IN7
apb_paddr[3] => Equal8.IN7
apb_paddr[4] => Decoder1.IN3
apb_paddr[4] => Equal0.IN6
apb_paddr[4] => Equal1.IN6
apb_paddr[4] => Equal2.IN5
apb_paddr[4] => Equal3.IN7
apb_paddr[4] => Equal4.IN1
apb_paddr[4] => Equal5.IN1
apb_paddr[4] => Equal6.IN6
apb_paddr[4] => Equal7.IN6
apb_paddr[4] => Equal8.IN6
apb_paddr[5] => Decoder1.IN2
apb_paddr[5] => Equal0.IN0
apb_paddr[5] => Equal1.IN0
apb_paddr[5] => Equal2.IN4
apb_paddr[5] => Equal3.IN0
apb_paddr[5] => Equal4.IN0
apb_paddr[5] => Equal5.IN0
apb_paddr[5] => Equal6.IN5
apb_paddr[5] => Equal7.IN5
apb_paddr[5] => Equal8.IN5
apb_paddr[6] => Decoder1.IN1
apb_paddr[6] => Equal0.IN5
apb_paddr[6] => Equal1.IN5
apb_paddr[6] => Equal2.IN3
apb_paddr[6] => Equal3.IN6
apb_paddr[6] => Equal4.IN5
apb_paddr[6] => Equal5.IN6
apb_paddr[6] => Equal6.IN0
apb_paddr[6] => Equal7.IN4
apb_paddr[6] => Equal8.IN0
apb_paddr[7] => Decoder1.IN0
apb_paddr[7] => Equal0.IN4
apb_paddr[7] => Equal1.IN4
apb_paddr[7] => Equal2.IN2
apb_paddr[7] => Equal3.IN5
apb_paddr[7] => Equal4.IN4
apb_paddr[7] => Equal5.IN5
apb_paddr[7] => Equal6.IN4
apb_paddr[7] => Equal7.IN3
apb_paddr[7] => Equal8.IN4
apb_paddr[8] => ShiftLeft0.IN9
apb_paddr[8] => Decoder0.IN2
apb_paddr[8] => Mux0.IN69
apb_paddr[8] => Mux1.IN69
apb_paddr[8] => Mux2.IN69
apb_paddr[8] => Mux3.IN69
apb_paddr[8] => Mux4.IN69
apb_paddr[8] => Mux5.IN69
apb_paddr[8] => Mux6.IN69
apb_paddr[8] => Mux7.IN69
apb_paddr[8] => Mux8.IN10
apb_paddr[8] => Mux9.IN10
apb_paddr[8] => Mux10.IN10
apb_paddr[8] => Mux11.IN10
apb_paddr[8] => Mux12.IN10
apb_paddr[8] => Mux13.IN10
apb_paddr[8] => Mux14.IN10
apb_paddr[8] => Mux15.IN10
apb_paddr[8] => Mux16.IN10
apb_paddr[8] => Mux17.IN10
apb_paddr[8] => Mux18.IN10
apb_paddr[8] => Mux19.IN10
apb_paddr[8] => Mux20.IN10
apb_paddr[8] => Mux21.IN10
apb_paddr[8] => Mux22.IN10
apb_paddr[8] => Mux23.IN10
apb_paddr[8] => Mux24.IN10
apb_paddr[8] => Mux25.IN10
apb_paddr[8] => Mux26.IN10
apb_paddr[8] => Mux27.IN10
apb_paddr[8] => Mux28.IN10
apb_paddr[8] => ShiftLeft1.IN35
apb_paddr[9] => ShiftLeft0.IN8
apb_paddr[9] => Decoder0.IN1
apb_paddr[9] => Mux0.IN68
apb_paddr[9] => Mux1.IN68
apb_paddr[9] => Mux2.IN68
apb_paddr[9] => Mux3.IN68
apb_paddr[9] => Mux4.IN68
apb_paddr[9] => Mux5.IN68
apb_paddr[9] => Mux6.IN68
apb_paddr[9] => Mux7.IN68
apb_paddr[9] => Mux8.IN9
apb_paddr[9] => Mux9.IN9
apb_paddr[9] => Mux10.IN9
apb_paddr[9] => Mux11.IN9
apb_paddr[9] => Mux12.IN9
apb_paddr[9] => Mux13.IN9
apb_paddr[9] => Mux14.IN9
apb_paddr[9] => Mux15.IN9
apb_paddr[9] => Mux16.IN9
apb_paddr[9] => Mux17.IN9
apb_paddr[9] => Mux18.IN9
apb_paddr[9] => Mux19.IN9
apb_paddr[9] => Mux20.IN9
apb_paddr[9] => Mux21.IN9
apb_paddr[9] => Mux22.IN9
apb_paddr[9] => Mux23.IN9
apb_paddr[9] => Mux24.IN9
apb_paddr[9] => Mux25.IN9
apb_paddr[9] => Mux26.IN9
apb_paddr[9] => Mux27.IN9
apb_paddr[9] => Mux28.IN9
apb_paddr[9] => ShiftLeft1.IN34
apb_paddr[10] => ShiftLeft0.IN7
apb_paddr[10] => Decoder0.IN0
apb_paddr[10] => Mux0.IN67
apb_paddr[10] => Mux1.IN67
apb_paddr[10] => Mux2.IN67
apb_paddr[10] => Mux3.IN67
apb_paddr[10] => Mux4.IN67
apb_paddr[10] => Mux5.IN67
apb_paddr[10] => Mux6.IN67
apb_paddr[10] => Mux7.IN67
apb_paddr[10] => Mux8.IN8
apb_paddr[10] => Mux9.IN8
apb_paddr[10] => Mux10.IN8
apb_paddr[10] => Mux11.IN8
apb_paddr[10] => Mux12.IN8
apb_paddr[10] => Mux13.IN8
apb_paddr[10] => Mux14.IN8
apb_paddr[10] => Mux15.IN8
apb_paddr[10] => Mux16.IN8
apb_paddr[10] => Mux17.IN8
apb_paddr[10] => Mux18.IN8
apb_paddr[10] => Mux19.IN8
apb_paddr[10] => Mux20.IN8
apb_paddr[10] => Mux21.IN8
apb_paddr[10] => Mux22.IN8
apb_paddr[10] => Mux23.IN8
apb_paddr[10] => Mux24.IN8
apb_paddr[10] => Mux25.IN8
apb_paddr[10] => Mux26.IN8
apb_paddr[10] => Mux27.IN8
apb_paddr[10] => Mux28.IN8
apb_paddr[10] => ShiftLeft1.IN33
apb_paddr[11] => ~NO_FANOUT~
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => rx_dma_en.DATAB
apb_pwdata[0] => ibrd[0]~reg0.DATAIN
apb_pwdata[0] => fbrd[0]~reg0.DATAIN
apb_pwdata[0] => uart_en~reg0.DATAIN
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => tx_dma_en.DATAB
apb_pwdata[1] => ibrd[1]~reg0.DATAIN
apb_pwdata[1] => fbrd[1]~reg0.DATAIN
apb_pwdata[1] => lcr_pen~reg0.DATAIN
apb_pwdata[2] => ibrd[2]~reg0.DATAIN
apb_pwdata[2] => fbrd[2]~reg0.DATAIN
apb_pwdata[2] => lcr_eps~reg0.DATAIN
apb_pwdata[3] => ibrd[3]~reg0.DATAIN
apb_pwdata[3] => fbrd[3]~reg0.DATAIN
apb_pwdata[3] => lcr_stp2~reg0.DATAIN
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => rx_not_empty_ie.DATAB
apb_pwdata[4] => ibrd[4]~reg0.DATAIN
apb_pwdata[4] => fbrd[4]~reg0.DATAIN
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => tx_not_full_ie.DATAB
apb_pwdata[5] => ibrd[5]~reg0.DATAIN
apb_pwdata[5] => fbrd[5]~reg0.DATAIN
apb_pwdata[6] => ibrd[6]~reg0.DATAIN
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => framing_error_ie.DATAB
apb_pwdata[7] => ibrd[7]~reg0.DATAIN
apb_pwdata[7] => lcr_sps~reg0.DATAIN
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => parity_error_ie.DATAB
apb_pwdata[8] => ibrd[8]~reg0.DATAIN
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => break_error_ie.DATAB
apb_pwdata[9] => ibrd[9]~reg0.DATAIN
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => overrun_error_ie.DATAB
apb_pwdata[10] => ibrd[10]~reg0.DATAIN
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => rx_idle_ie.DATAB
apb_pwdata[11] => ibrd[11]~reg0.DATAIN
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => tx_complete_ie.DATAB
apb_pwdata[12] => ibrd[12]~reg0.DATAIN
apb_pwdata[13] => ibrd[13]~reg0.DATAIN
apb_pwdata[14] => ibrd[14]~reg0.DATAIN
apb_pwdata[15] => ibrd[15]~reg0.DATAIN
apb_pwdata[16] => ~NO_FANOUT~
apb_pwdata[17] => ~NO_FANOUT~
apb_pwdata[18] => ~NO_FANOUT~
apb_pwdata[19] => ~NO_FANOUT~
apb_pwdata[20] => ~NO_FANOUT~
apb_pwdata[21] => ~NO_FANOUT~
apb_pwdata[22] => ~NO_FANOUT~
apb_pwdata[23] => ~NO_FANOUT~
apb_pwdata[24] => ~NO_FANOUT~
apb_pwdata[25] => ~NO_FANOUT~
apb_pwdata[26] => ~NO_FANOUT~
apb_pwdata[27] => ~NO_FANOUT~
apb_pwdata[28] => ~NO_FANOUT~
apb_pwdata[29] => ~NO_FANOUT~
apb_pwdata[30] => ~NO_FANOUT~
apb_pwdata[31] => ~NO_FANOUT~
apb_prdata[0] <= apb_prdata[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[1] <= apb_prdata[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[2] <= apb_prdata[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[3] <= apb_prdata[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[4] <= apb_prdata[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[5] <= apb_prdata[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[6] <= apb_prdata[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[7] <= apb_prdata[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[8] <= apb_prdata[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[9] <= apb_prdata[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[10] <= apb_prdata[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[11] <= apb_prdata[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[12] <= apb_prdata[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[13] <= apb_prdata[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[14] <= apb_prdata[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[15] <= apb_prdata[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[16] <= apb_prdata[16]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[17] <= apb_prdata[17]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[18] <= apb_prdata[18]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[19] <= apb_prdata[19]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[20] <= apb_prdata[20]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[21] <= apb_prdata[21]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[22] <= apb_prdata[22]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[23] <= apb_prdata[23]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[24] <= apb_prdata[24]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[25] <= apb_prdata[25]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[26] <= apb_prdata[26]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[27] <= apb_prdata[27]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[28] <= apb_prdata[28]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[29] <= apb_prdata[29]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[30] <= apb_prdata[30]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_prdata[31] <= apb_prdata[31]~reg0.DB_MAX_OUTPUT_PORT_TYPE
apb_pready <= apb_pready~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_en <= uart_en~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[0] <= ibrd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[1] <= ibrd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[2] <= ibrd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[3] <= ibrd[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[4] <= ibrd[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[5] <= ibrd[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[6] <= ibrd[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[7] <= ibrd[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[8] <= ibrd[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[9] <= ibrd[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[10] <= ibrd[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[11] <= ibrd[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[12] <= ibrd[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[13] <= ibrd[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[14] <= ibrd[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ibrd[15] <= ibrd[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[0] <= fbrd[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[1] <= fbrd[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[2] <= fbrd[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[3] <= fbrd[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[4] <= fbrd[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
fbrd[5] <= fbrd[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[0] <= tx_write[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[1] <= tx_write[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[2] <= tx_write[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[3] <= tx_write[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[4] <= tx_write[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_write[5] <= tx_write[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[0] <= rx_read[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[1] <= rx_read[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[2] <= rx_read[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[3] <= rx_read[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[4] <= rx_read[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_read[5] <= rx_read[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_data[0] => Mux0.IN59
rx_data[1] => Mux1.IN59
rx_data[2] => Mux2.IN59
rx_data[3] => Mux3.IN59
rx_data[4] => Mux4.IN59
rx_data[5] => Mux5.IN59
rx_data[6] => Mux6.IN59
rx_data[7] => Mux7.IN59
rx_data[8] => Mux0.IN51
rx_data[9] => Mux1.IN51
rx_data[10] => Mux2.IN51
rx_data[11] => Mux3.IN51
rx_data[12] => Mux4.IN51
rx_data[13] => Mux5.IN51
rx_data[14] => Mux6.IN51
rx_data[15] => Mux7.IN51
rx_data[16] => Mux0.IN43
rx_data[17] => Mux1.IN43
rx_data[18] => Mux2.IN43
rx_data[19] => Mux3.IN43
rx_data[20] => Mux4.IN43
rx_data[21] => Mux5.IN43
rx_data[22] => Mux6.IN43
rx_data[23] => Mux7.IN43
rx_data[24] => Mux0.IN35
rx_data[25] => Mux1.IN35
rx_data[26] => Mux2.IN35
rx_data[27] => Mux3.IN35
rx_data[28] => Mux4.IN35
rx_data[29] => Mux5.IN35
rx_data[30] => Mux6.IN35
rx_data[31] => Mux7.IN35
rx_data[32] => Mux0.IN27
rx_data[33] => Mux1.IN27
rx_data[34] => Mux2.IN27
rx_data[35] => Mux3.IN27
rx_data[36] => Mux4.IN27
rx_data[37] => Mux5.IN27
rx_data[38] => Mux6.IN27
rx_data[39] => Mux7.IN27
rx_data[40] => Mux0.IN19
rx_data[41] => Mux1.IN19
rx_data[42] => Mux2.IN19
rx_data[43] => Mux3.IN19
rx_data[44] => Mux4.IN19
rx_data[45] => Mux5.IN19
rx_data[46] => Mux6.IN19
rx_data[47] => Mux7.IN19
tx_full[0] => Mux10.IN7
tx_full[0] => interrupts.IN1
tx_full[1] => Mux10.IN6
tx_full[1] => interrupts.IN1
tx_full[2] => Mux10.IN5
tx_full[2] => interrupts.IN1
tx_full[3] => Mux10.IN4
tx_full[3] => interrupts.IN1
tx_full[4] => Mux10.IN3
tx_full[4] => interrupts.IN1
tx_full[5] => Mux10.IN2
tx_full[5] => interrupts.IN1
tx_empty[0] => Mux8.IN7
tx_empty[1] => Mux8.IN6
tx_empty[2] => Mux8.IN5
tx_empty[3] => Mux8.IN4
tx_empty[4] => Mux8.IN3
tx_empty[5] => Mux8.IN2
tx_busy[0] => Mux12.IN7
tx_busy[1] => Mux12.IN6
tx_busy[2] => Mux12.IN5
tx_busy[3] => Mux12.IN4
tx_busy[4] => Mux12.IN3
tx_busy[5] => Mux12.IN2
tx_complete[0] => interrupts.IN1
tx_complete[0] => Mux13.IN7
tx_complete[1] => interrupts.IN1
tx_complete[1] => Mux13.IN6
tx_complete[2] => interrupts.IN1
tx_complete[2] => Mux13.IN5
tx_complete[3] => interrupts.IN1
tx_complete[3] => Mux13.IN4
tx_complete[4] => interrupts.IN1
tx_complete[4] => Mux13.IN3
tx_complete[5] => interrupts.IN1
tx_complete[5] => Mux13.IN2
rx_full[0] => Mux9.IN7
rx_full[1] => Mux9.IN6
rx_full[2] => Mux9.IN5
rx_full[3] => Mux9.IN4
rx_full[4] => Mux9.IN3
rx_full[5] => Mux9.IN2
rx_empty[0] => Mux11.IN7
rx_empty[0] => interrupts.IN1
rx_empty[1] => Mux11.IN6
rx_empty[1] => interrupts.IN1
rx_empty[2] => Mux11.IN5
rx_empty[2] => interrupts.IN1
rx_empty[3] => Mux11.IN4
rx_empty[3] => interrupts.IN1
rx_empty[4] => Mux11.IN3
rx_empty[4] => interrupts.IN1
rx_empty[5] => Mux11.IN2
rx_empty[5] => interrupts.IN1
rx_idle[0] => interrupts.IN1
rx_idle[0] => Mux14.IN7
rx_idle[1] => interrupts.IN1
rx_idle[1] => Mux14.IN6
rx_idle[2] => interrupts.IN1
rx_idle[2] => Mux14.IN5
rx_idle[3] => interrupts.IN1
rx_idle[3] => Mux14.IN4
rx_idle[4] => interrupts.IN1
rx_idle[4] => Mux14.IN3
rx_idle[5] => interrupts.IN1
rx_idle[5] => Mux14.IN2
framing_error[0] => interrupts.IN1
framing_error[0] => Mux18.IN7
framing_error[1] => interrupts.IN1
framing_error[1] => Mux18.IN6
framing_error[2] => interrupts.IN1
framing_error[2] => Mux18.IN5
framing_error[3] => interrupts.IN1
framing_error[3] => Mux18.IN4
framing_error[4] => interrupts.IN1
framing_error[4] => Mux18.IN3
framing_error[5] => interrupts.IN1
framing_error[5] => Mux18.IN2
parity_error[0] => interrupts.IN1
parity_error[0] => Mux17.IN7
parity_error[1] => interrupts.IN1
parity_error[1] => Mux17.IN6
parity_error[2] => interrupts.IN1
parity_error[2] => Mux17.IN5
parity_error[3] => interrupts.IN1
parity_error[3] => Mux17.IN4
parity_error[4] => interrupts.IN1
parity_error[4] => Mux17.IN3
parity_error[5] => interrupts.IN1
parity_error[5] => Mux17.IN2
break_error[0] => interrupts.IN1
break_error[0] => Mux16.IN7
break_error[1] => interrupts.IN1
break_error[1] => Mux16.IN6
break_error[2] => interrupts.IN1
break_error[2] => Mux16.IN5
break_error[3] => interrupts.IN1
break_error[3] => Mux16.IN4
break_error[4] => interrupts.IN1
break_error[4] => Mux16.IN3
break_error[5] => interrupts.IN1
break_error[5] => Mux16.IN2
overrun_error[0] => interrupts.IN1
overrun_error[0] => Mux15.IN7
overrun_error[1] => interrupts.IN1
overrun_error[1] => Mux15.IN6
overrun_error[2] => interrupts.IN1
overrun_error[2] => Mux15.IN5
overrun_error[3] => interrupts.IN1
overrun_error[3] => Mux15.IN4
overrun_error[4] => interrupts.IN1
overrun_error[4] => Mux15.IN3
overrun_error[5] => interrupts.IN1
overrun_error[5] => Mux15.IN2
clear_flags[0] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[1] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[2] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[3] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[4] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
clear_flags[5] <= clear_flags.DB_MAX_OUTPUT_PORT_TYPE
lcr_sps <= lcr_sps~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcr_stp2 <= lcr_stp2~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcr_eps <= lcr_eps~reg0.DB_MAX_OUTPUT_PORT_TYPE
lcr_pen <= lcr_pen~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[0] <= rx_dma_en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[1] <= rx_dma_en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[2] <= rx_dma_en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[3] <= rx_dma_en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[4] <= rx_dma_en[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en[5] <= rx_dma_en[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[0] <= tx_dma_en[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[1] <= tx_dma_en[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[2] <= tx_dma_en[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[3] <= tx_dma_en[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[4] <= tx_dma_en[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en[5] <= tx_dma_en[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[0] <= interrupts[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[1] <= interrupts[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[2] <= interrupts[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[3] <= interrupts[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[4] <= interrupts[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
interrupts[5] <= interrupts[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]
clk => clk.IN1
rstn => rstn.IN1
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => tx_baud_cnt.OUTPUTSELECT
baud16 => always6.IN1
tx_write => tx_write.IN1
tx_data[0] => tx_data[0].IN1
tx_data[1] => tx_data[1].IN1
tx_data[2] => tx_data[2].IN1
tx_data[3] => tx_data[3].IN1
tx_data[4] => tx_data[4].IN1
tx_data[5] => tx_data[5].IN1
tx_data[6] => tx_data[6].IN1
tx_data[7] => tx_data[7].IN1
lcr_sps => always2.IN1
lcr_stp2 => tx_stop_cnt.DATAB
lcr_eps => tx_parity.DATAB
lcr_pen => tx_state.DATAB
lcr_pen => tx_state.DATAB
tx_clear => always7.IN1
tx_full <= sync_fifo:tx_fifo.full
tx_empty <= sync_fifo:tx_fifo.empty
tx_busy <= tx_busy.DB_MAX_OUTPUT_PORT_TYPE
tx_complete <= tx_complete~reg0.DB_MAX_OUTPUT_PORT_TYPE
tx_dma_en => always8.IN0
tx_dma_clr => always8.IN1
tx_dma_req <= tx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
uart_txd <= uart_txd~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]
clk => clk.IN1
rstn => rstn.IN1
baud16 => rx_sample.IN1
baud16 => always2.IN1
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_baud_cnt.OUTPUTSELECT
baud16 => rx_in[4].ENA
baud16 => rx_in[3].ENA
baud16 => rx_in[2].ENA
baud16 => rx_in[1].ENA
baud16 => rx_in[0].ENA
uart_rxd => rx_in[0].DATAIN
lcr_sps => always5.IN1
lcr_stp2 => Add3.IN4
lcr_eps => rx_parity.DATAB
lcr_pen => rx_state.DATAB
lcr_pen => Add2.IN0
lcr_pen => rx_state.DATAB
rx_read => rx_read.IN1
rx_clear => rx_idle_en.OUTPUTSELECT
rx_clear => rx_idle.OUTPUTSELECT
rx_clear => framing_error.OUTPUTSELECT
rx_clear => parity_error.OUTPUTSELECT
rx_clear => break_error.OUTPUTSELECT
rx_clear => overrun_error.OUTPUTSELECT
rx_full <= sync_fifo:rx_fifo.full
rx_empty <= sync_fifo:rx_fifo.empty
rx_data[0] <= sync_fifo:rx_fifo.dout
rx_data[1] <= sync_fifo:rx_fifo.dout
rx_data[2] <= sync_fifo:rx_fifo.dout
rx_data[3] <= sync_fifo:rx_fifo.dout
rx_data[4] <= sync_fifo:rx_fifo.dout
rx_data[5] <= sync_fifo:rx_fifo.dout
rx_data[6] <= sync_fifo:rx_fifo.dout
rx_data[7] <= sync_fifo:rx_fifo.dout
rx_idle <= rx_idle~reg0.DB_MAX_OUTPUT_PORT_TYPE
rx_dma_en => always13.IN0
rx_dma_clr => always13.IN1
rx_dma_req <= rx_dma_req~reg0.DB_MAX_OUTPUT_PORT_TYPE
framing_error <= framing_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
parity_error <= parity_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
break_error <= break_error~reg0.DB_MAX_OUTPUT_PORT_TYPE
overrun_error <= overrun_error~reg0.DB_MAX_OUTPUT_PORT_TYPE


|test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo
clk => fifo[1][0].CLK
clk => fifo[1][1].CLK
clk => fifo[1][2].CLK
clk => fifo[1][3].CLK
clk => fifo[1][4].CLK
clk => fifo[1][5].CLK
clk => fifo[1][6].CLK
clk => fifo[1][7].CLK
clk => counter[0].CLK
rstn => counter[0].ACLR
wren => wrreq.IN1
rden => rdreq.IN1
din[0] => fifo[1][0].DATAIN
din[1] => fifo[1][1].DATAIN
din[2] => fifo[1][2].DATAIN
din[3] => fifo[1][3].DATAIN
din[4] => fifo[1][4].DATAIN
din[5] => fifo[1][5].DATAIN
din[6] => fifo[1][6].DATAIN
din[7] => fifo[1][7].DATAIN
dout[0] <= fifo[1][0].DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= fifo[1][1].DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= fifo[1][2].DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= fifo[1][3].DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= fifo[1][4].DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= fifo[1][5].DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= fifo[1][6].DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= fifo[1][7].DB_MAX_OUTPUT_PORT_TYPE
full <= counter[0].DB_MAX_OUTPUT_PORT_TYPE
empty <= counter[0].DB_MAX_OUTPUT_PORT_TYPE


|test_uart|alta_rv32:rv32
sys_clk => ~NO_FANOUT~
mem_ahb_hready <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hreadyout => ~NO_FANOUT~
mem_ahb_htrans[0] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_htrans[1] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hsize[0] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hsize[1] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hsize[2] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hburst[0] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hburst[1] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hburst[2] <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwrite <= mem_ahb_hresp.DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[0] <= mem_ahb_hrdata[0].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[1] <= mem_ahb_hrdata[1].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[2] <= mem_ahb_hrdata[2].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[3] <= mem_ahb_hrdata[3].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[4] <= mem_ahb_hrdata[4].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[5] <= mem_ahb_hrdata[5].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[6] <= mem_ahb_hrdata[6].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[7] <= mem_ahb_hrdata[7].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[8] <= mem_ahb_hrdata[8].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[9] <= mem_ahb_hrdata[9].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[10] <= mem_ahb_hrdata[10].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[11] <= mem_ahb_hrdata[11].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[12] <= mem_ahb_hrdata[12].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[13] <= mem_ahb_hrdata[13].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[14] <= mem_ahb_hrdata[14].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[15] <= mem_ahb_hrdata[15].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[16] <= mem_ahb_hrdata[16].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[17] <= mem_ahb_hrdata[17].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[18] <= mem_ahb_hrdata[18].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[19] <= mem_ahb_hrdata[19].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[20] <= mem_ahb_hrdata[20].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[21] <= mem_ahb_hrdata[21].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[22] <= mem_ahb_hrdata[22].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[23] <= mem_ahb_hrdata[23].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[24] <= mem_ahb_hrdata[24].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[25] <= mem_ahb_hrdata[25].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[26] <= mem_ahb_hrdata[26].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[27] <= mem_ahb_hrdata[27].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[28] <= mem_ahb_hrdata[28].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[29] <= mem_ahb_hrdata[29].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[30] <= mem_ahb_hrdata[30].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_haddr[31] <= mem_ahb_hrdata[31].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[0] <= mem_ahb_hrdata[0].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[1] <= mem_ahb_hrdata[1].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[2] <= mem_ahb_hrdata[2].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[3] <= mem_ahb_hrdata[3].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[4] <= mem_ahb_hrdata[4].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[5] <= mem_ahb_hrdata[5].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[6] <= mem_ahb_hrdata[6].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[7] <= mem_ahb_hrdata[7].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[8] <= mem_ahb_hrdata[8].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[9] <= mem_ahb_hrdata[9].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[10] <= mem_ahb_hrdata[10].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[11] <= mem_ahb_hrdata[11].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[12] <= mem_ahb_hrdata[12].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[13] <= mem_ahb_hrdata[13].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[14] <= mem_ahb_hrdata[14].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[15] <= mem_ahb_hrdata[15].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[16] <= mem_ahb_hrdata[16].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[17] <= mem_ahb_hrdata[17].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[18] <= mem_ahb_hrdata[18].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[19] <= mem_ahb_hrdata[19].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[20] <= mem_ahb_hrdata[20].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[21] <= mem_ahb_hrdata[21].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[22] <= mem_ahb_hrdata[22].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[23] <= mem_ahb_hrdata[23].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[24] <= mem_ahb_hrdata[24].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[25] <= mem_ahb_hrdata[25].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[26] <= mem_ahb_hrdata[26].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[27] <= mem_ahb_hrdata[27].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[28] <= mem_ahb_hrdata[28].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[29] <= mem_ahb_hrdata[29].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[30] <= mem_ahb_hrdata[30].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hwdata[31] <= mem_ahb_hrdata[31].DB_MAX_OUTPUT_PORT_TYPE
mem_ahb_hresp => mem_ahb_hwrite.DATAIN
mem_ahb_hresp => mem_ahb_hready.DATAIN
mem_ahb_hresp => mem_ahb_htrans[1].DATAIN
mem_ahb_hresp => mem_ahb_htrans[0].DATAIN
mem_ahb_hresp => mem_ahb_hsize[2].DATAIN
mem_ahb_hresp => mem_ahb_hsize[1].DATAIN
mem_ahb_hresp => mem_ahb_hsize[0].DATAIN
mem_ahb_hresp => mem_ahb_hburst[2].DATAIN
mem_ahb_hresp => mem_ahb_hburst[1].DATAIN
mem_ahb_hresp => mem_ahb_hburst[0].DATAIN
mem_ahb_hrdata[0] => mem_ahb_hwdata[0].DATAIN
mem_ahb_hrdata[0] => mem_ahb_haddr[0].DATAIN
mem_ahb_hrdata[1] => mem_ahb_hwdata[1].DATAIN
mem_ahb_hrdata[1] => mem_ahb_haddr[1].DATAIN
mem_ahb_hrdata[2] => mem_ahb_hwdata[2].DATAIN
mem_ahb_hrdata[2] => mem_ahb_haddr[2].DATAIN
mem_ahb_hrdata[3] => mem_ahb_hwdata[3].DATAIN
mem_ahb_hrdata[3] => mem_ahb_haddr[3].DATAIN
mem_ahb_hrdata[4] => mem_ahb_hwdata[4].DATAIN
mem_ahb_hrdata[4] => mem_ahb_haddr[4].DATAIN
mem_ahb_hrdata[5] => mem_ahb_hwdata[5].DATAIN
mem_ahb_hrdata[5] => mem_ahb_haddr[5].DATAIN
mem_ahb_hrdata[6] => mem_ahb_hwdata[6].DATAIN
mem_ahb_hrdata[6] => mem_ahb_haddr[6].DATAIN
mem_ahb_hrdata[7] => mem_ahb_hwdata[7].DATAIN
mem_ahb_hrdata[7] => mem_ahb_haddr[7].DATAIN
mem_ahb_hrdata[8] => mem_ahb_hwdata[8].DATAIN
mem_ahb_hrdata[8] => mem_ahb_haddr[8].DATAIN
mem_ahb_hrdata[9] => mem_ahb_hwdata[9].DATAIN
mem_ahb_hrdata[9] => mem_ahb_haddr[9].DATAIN
mem_ahb_hrdata[10] => mem_ahb_hwdata[10].DATAIN
mem_ahb_hrdata[10] => mem_ahb_haddr[10].DATAIN
mem_ahb_hrdata[11] => mem_ahb_hwdata[11].DATAIN
mem_ahb_hrdata[11] => mem_ahb_haddr[11].DATAIN
mem_ahb_hrdata[12] => mem_ahb_hwdata[12].DATAIN
mem_ahb_hrdata[12] => mem_ahb_haddr[12].DATAIN
mem_ahb_hrdata[13] => mem_ahb_hwdata[13].DATAIN
mem_ahb_hrdata[13] => mem_ahb_haddr[13].DATAIN
mem_ahb_hrdata[14] => mem_ahb_hwdata[14].DATAIN
mem_ahb_hrdata[14] => mem_ahb_haddr[14].DATAIN
mem_ahb_hrdata[15] => mem_ahb_hwdata[15].DATAIN
mem_ahb_hrdata[15] => mem_ahb_haddr[15].DATAIN
mem_ahb_hrdata[16] => mem_ahb_hwdata[16].DATAIN
mem_ahb_hrdata[16] => mem_ahb_haddr[16].DATAIN
mem_ahb_hrdata[17] => mem_ahb_hwdata[17].DATAIN
mem_ahb_hrdata[17] => mem_ahb_haddr[17].DATAIN
mem_ahb_hrdata[18] => mem_ahb_hwdata[18].DATAIN
mem_ahb_hrdata[18] => mem_ahb_haddr[18].DATAIN
mem_ahb_hrdata[19] => mem_ahb_hwdata[19].DATAIN
mem_ahb_hrdata[19] => mem_ahb_haddr[19].DATAIN
mem_ahb_hrdata[20] => mem_ahb_hwdata[20].DATAIN
mem_ahb_hrdata[20] => mem_ahb_haddr[20].DATAIN
mem_ahb_hrdata[21] => mem_ahb_hwdata[21].DATAIN
mem_ahb_hrdata[21] => mem_ahb_haddr[21].DATAIN
mem_ahb_hrdata[22] => mem_ahb_hwdata[22].DATAIN
mem_ahb_hrdata[22] => mem_ahb_haddr[22].DATAIN
mem_ahb_hrdata[23] => mem_ahb_hwdata[23].DATAIN
mem_ahb_hrdata[23] => mem_ahb_haddr[23].DATAIN
mem_ahb_hrdata[24] => mem_ahb_hwdata[24].DATAIN
mem_ahb_hrdata[24] => mem_ahb_haddr[24].DATAIN
mem_ahb_hrdata[25] => mem_ahb_hwdata[25].DATAIN
mem_ahb_hrdata[25] => mem_ahb_haddr[25].DATAIN
mem_ahb_hrdata[26] => mem_ahb_hwdata[26].DATAIN
mem_ahb_hrdata[26] => mem_ahb_haddr[26].DATAIN
mem_ahb_hrdata[27] => mem_ahb_hwdata[27].DATAIN
mem_ahb_hrdata[27] => mem_ahb_haddr[27].DATAIN
mem_ahb_hrdata[28] => mem_ahb_hwdata[28].DATAIN
mem_ahb_hrdata[28] => mem_ahb_haddr[28].DATAIN
mem_ahb_hrdata[29] => mem_ahb_hwdata[29].DATAIN
mem_ahb_hrdata[29] => mem_ahb_haddr[29].DATAIN
mem_ahb_hrdata[30] => mem_ahb_hwdata[30].DATAIN
mem_ahb_hrdata[30] => mem_ahb_haddr[30].DATAIN
mem_ahb_hrdata[31] => mem_ahb_hwdata[31].DATAIN
mem_ahb_hrdata[31] => mem_ahb_haddr[31].DATAIN
slave_ahb_hsel => slave_ahb_hresp.DATAIN
slave_ahb_hsel => slave_ahb_hreadyout.DATAIN
slave_ahb_hready => ~NO_FANOUT~
slave_ahb_hreadyout <= slave_ahb_hsel.DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_htrans[0] => ~NO_FANOUT~
slave_ahb_htrans[1] => ~NO_FANOUT~
slave_ahb_hsize[0] => ~NO_FANOUT~
slave_ahb_hsize[1] => ~NO_FANOUT~
slave_ahb_hsize[2] => ~NO_FANOUT~
slave_ahb_hburst[0] => ~NO_FANOUT~
slave_ahb_hburst[1] => ~NO_FANOUT~
slave_ahb_hburst[2] => ~NO_FANOUT~
slave_ahb_hwrite => ~NO_FANOUT~
slave_ahb_haddr[0] => slave_ahb_hrdata[0].DATAIN
slave_ahb_haddr[1] => slave_ahb_hrdata[1].DATAIN
slave_ahb_haddr[2] => slave_ahb_hrdata[2].DATAIN
slave_ahb_haddr[3] => slave_ahb_hrdata[3].DATAIN
slave_ahb_haddr[4] => slave_ahb_hrdata[4].DATAIN
slave_ahb_haddr[5] => slave_ahb_hrdata[5].DATAIN
slave_ahb_haddr[6] => slave_ahb_hrdata[6].DATAIN
slave_ahb_haddr[7] => slave_ahb_hrdata[7].DATAIN
slave_ahb_haddr[8] => slave_ahb_hrdata[8].DATAIN
slave_ahb_haddr[9] => slave_ahb_hrdata[9].DATAIN
slave_ahb_haddr[10] => slave_ahb_hrdata[10].DATAIN
slave_ahb_haddr[11] => slave_ahb_hrdata[11].DATAIN
slave_ahb_haddr[12] => slave_ahb_hrdata[12].DATAIN
slave_ahb_haddr[13] => slave_ahb_hrdata[13].DATAIN
slave_ahb_haddr[14] => slave_ahb_hrdata[14].DATAIN
slave_ahb_haddr[15] => slave_ahb_hrdata[15].DATAIN
slave_ahb_haddr[16] => slave_ahb_hrdata[16].DATAIN
slave_ahb_haddr[17] => slave_ahb_hrdata[17].DATAIN
slave_ahb_haddr[18] => slave_ahb_hrdata[18].DATAIN
slave_ahb_haddr[19] => slave_ahb_hrdata[19].DATAIN
slave_ahb_haddr[20] => slave_ahb_hrdata[20].DATAIN
slave_ahb_haddr[21] => slave_ahb_hrdata[21].DATAIN
slave_ahb_haddr[22] => slave_ahb_hrdata[22].DATAIN
slave_ahb_haddr[23] => slave_ahb_hrdata[23].DATAIN
slave_ahb_haddr[24] => slave_ahb_hrdata[24].DATAIN
slave_ahb_haddr[25] => slave_ahb_hrdata[25].DATAIN
slave_ahb_haddr[26] => slave_ahb_hrdata[26].DATAIN
slave_ahb_haddr[27] => slave_ahb_hrdata[27].DATAIN
slave_ahb_haddr[28] => slave_ahb_hrdata[28].DATAIN
slave_ahb_haddr[29] => slave_ahb_hrdata[29].DATAIN
slave_ahb_haddr[30] => slave_ahb_hrdata[30].DATAIN
slave_ahb_haddr[31] => slave_ahb_hrdata[31].DATAIN
slave_ahb_hwdata[0] => ~NO_FANOUT~
slave_ahb_hwdata[1] => ~NO_FANOUT~
slave_ahb_hwdata[2] => ~NO_FANOUT~
slave_ahb_hwdata[3] => ~NO_FANOUT~
slave_ahb_hwdata[4] => ~NO_FANOUT~
slave_ahb_hwdata[5] => ~NO_FANOUT~
slave_ahb_hwdata[6] => ~NO_FANOUT~
slave_ahb_hwdata[7] => ~NO_FANOUT~
slave_ahb_hwdata[8] => ~NO_FANOUT~
slave_ahb_hwdata[9] => ~NO_FANOUT~
slave_ahb_hwdata[10] => ~NO_FANOUT~
slave_ahb_hwdata[11] => ~NO_FANOUT~
slave_ahb_hwdata[12] => ~NO_FANOUT~
slave_ahb_hwdata[13] => ~NO_FANOUT~
slave_ahb_hwdata[14] => ~NO_FANOUT~
slave_ahb_hwdata[15] => ~NO_FANOUT~
slave_ahb_hwdata[16] => ~NO_FANOUT~
slave_ahb_hwdata[17] => ~NO_FANOUT~
slave_ahb_hwdata[18] => ~NO_FANOUT~
slave_ahb_hwdata[19] => ~NO_FANOUT~
slave_ahb_hwdata[20] => ~NO_FANOUT~
slave_ahb_hwdata[21] => ~NO_FANOUT~
slave_ahb_hwdata[22] => ~NO_FANOUT~
slave_ahb_hwdata[23] => ~NO_FANOUT~
slave_ahb_hwdata[24] => ~NO_FANOUT~
slave_ahb_hwdata[25] => ~NO_FANOUT~
slave_ahb_hwdata[26] => ~NO_FANOUT~
slave_ahb_hwdata[27] => ~NO_FANOUT~
slave_ahb_hwdata[28] => ~NO_FANOUT~
slave_ahb_hwdata[29] => ~NO_FANOUT~
slave_ahb_hwdata[30] => ~NO_FANOUT~
slave_ahb_hwdata[31] => ~NO_FANOUT~
slave_ahb_hresp <= slave_ahb_hsel.DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[0] <= slave_ahb_haddr[0].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[1] <= slave_ahb_haddr[1].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[2] <= slave_ahb_haddr[2].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[3] <= slave_ahb_haddr[3].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[4] <= slave_ahb_haddr[4].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[5] <= slave_ahb_haddr[5].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[6] <= slave_ahb_haddr[6].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[7] <= slave_ahb_haddr[7].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[8] <= slave_ahb_haddr[8].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[9] <= slave_ahb_haddr[9].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[10] <= slave_ahb_haddr[10].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[11] <= slave_ahb_haddr[11].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[12] <= slave_ahb_haddr[12].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[13] <= slave_ahb_haddr[13].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[14] <= slave_ahb_haddr[14].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[15] <= slave_ahb_haddr[15].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[16] <= slave_ahb_haddr[16].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[17] <= slave_ahb_haddr[17].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[18] <= slave_ahb_haddr[18].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[19] <= slave_ahb_haddr[19].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[20] <= slave_ahb_haddr[20].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[21] <= slave_ahb_haddr[21].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[22] <= slave_ahb_haddr[22].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[23] <= slave_ahb_haddr[23].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[24] <= slave_ahb_haddr[24].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[25] <= slave_ahb_haddr[25].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[26] <= slave_ahb_haddr[26].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[27] <= slave_ahb_haddr[27].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[28] <= slave_ahb_haddr[28].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[29] <= slave_ahb_haddr[29].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[30] <= slave_ahb_haddr[30].DB_MAX_OUTPUT_PORT_TYPE
slave_ahb_hrdata[31] <= slave_ahb_haddr[31].DB_MAX_OUTPUT_PORT_TYPE
gpio0_io_in[0] => ~NO_FANOUT~
gpio0_io_in[1] => ~NO_FANOUT~
gpio0_io_in[2] => ~NO_FANOUT~
gpio0_io_in[3] => ~NO_FANOUT~
gpio0_io_in[4] => ~NO_FANOUT~
gpio0_io_in[5] => ~NO_FANOUT~
gpio0_io_in[6] => ~NO_FANOUT~
gpio0_io_in[7] => ~NO_FANOUT~
gpio0_io_out_data[0] <= <GND>
gpio0_io_out_data[1] <= <GND>
gpio0_io_out_data[2] <= <GND>
gpio0_io_out_data[3] <= <GND>
gpio0_io_out_data[4] <= <GND>
gpio0_io_out_data[5] <= <GND>
gpio0_io_out_data[6] <= <GND>
gpio0_io_out_data[7] <= <GND>
gpio0_io_out_en[0] <= <GND>
gpio0_io_out_en[1] <= <GND>
gpio0_io_out_en[2] <= <GND>
gpio0_io_out_en[3] <= <GND>
gpio0_io_out_en[4] <= <GND>
gpio0_io_out_en[5] <= <GND>
gpio0_io_out_en[6] <= <GND>
gpio0_io_out_en[7] <= <GND>
gpio1_io_in[0] => ~NO_FANOUT~
gpio1_io_in[1] => ~NO_FANOUT~
gpio1_io_in[2] => ~NO_FANOUT~
gpio1_io_in[3] => ~NO_FANOUT~
gpio1_io_in[4] => ~NO_FANOUT~
gpio1_io_in[5] => ~NO_FANOUT~
gpio1_io_in[6] => ~NO_FANOUT~
gpio1_io_in[7] => ~NO_FANOUT~
gpio1_io_out_data[0] <= <GND>
gpio1_io_out_data[1] <= <GND>
gpio1_io_out_data[2] <= <GND>
gpio1_io_out_data[3] <= <GND>
gpio1_io_out_data[4] <= <GND>
gpio1_io_out_data[5] <= <GND>
gpio1_io_out_data[6] <= <GND>
gpio1_io_out_data[7] <= <GND>
gpio1_io_out_en[0] <= <GND>
gpio1_io_out_en[1] <= <GND>
gpio1_io_out_en[2] <= <GND>
gpio1_io_out_en[3] <= <GND>
gpio1_io_out_en[4] <= <GND>
gpio1_io_out_en[5] <= <GND>
gpio1_io_out_en[6] <= <GND>
gpio1_io_out_en[7] <= <GND>
sys_ctrl_clkSource[0] <= usb0_xcvr_clk.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_clkSource[1] <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_hseEnable <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_hseBypass <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_pllEnable <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_pllReady => sys_ctrl_standby.DATAIN
sys_ctrl_pllReady => sys_ctrl_clkSource[1].DATAIN
sys_ctrl_pllReady => sys_ctrl_hseEnable.DATAIN
sys_ctrl_pllReady => sys_ctrl_hseBypass.DATAIN
sys_ctrl_pllReady => sys_ctrl_pllEnable.DATAIN
sys_ctrl_pllReady => sys_ctrl_sleep.DATAIN
sys_ctrl_pllReady => sys_ctrl_stop.DATAIN
sys_ctrl_sleep <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_stop <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
sys_ctrl_standby <= sys_ctrl_pllReady.DB_MAX_OUTPUT_PORT_TYPE
gpio2_io_in[0] => ~NO_FANOUT~
gpio2_io_in[1] => ~NO_FANOUT~
gpio2_io_in[2] => ~NO_FANOUT~
gpio2_io_in[3] => ~NO_FANOUT~
gpio2_io_in[4] => ~NO_FANOUT~
gpio2_io_in[5] => ~NO_FANOUT~
gpio2_io_in[6] => ~NO_FANOUT~
gpio2_io_in[7] => ~NO_FANOUT~
gpio2_io_out_data[0] <= <GND>
gpio2_io_out_data[1] <= <GND>
gpio2_io_out_data[2] <= <GND>
gpio2_io_out_data[3] <= <GND>
gpio2_io_out_data[4] <= <GND>
gpio2_io_out_data[5] <= <GND>
gpio2_io_out_data[6] <= <GND>
gpio2_io_out_data[7] <= <GND>
gpio2_io_out_en[0] <= <GND>
gpio2_io_out_en[1] <= <GND>
gpio2_io_out_en[2] <= <GND>
gpio2_io_out_en[3] <= <GND>
gpio2_io_out_en[4] <= <GND>
gpio2_io_out_en[5] <= <GND>
gpio2_io_out_en[6] <= <GND>
gpio2_io_out_en[7] <= <GND>
gpio3_io_in[0] => ~NO_FANOUT~
gpio3_io_in[1] => ~NO_FANOUT~
gpio3_io_in[2] => ~NO_FANOUT~
gpio3_io_in[3] => ~NO_FANOUT~
gpio3_io_in[4] => ~NO_FANOUT~
gpio3_io_in[5] => ~NO_FANOUT~
gpio3_io_in[6] => ~NO_FANOUT~
gpio3_io_in[7] => ~NO_FANOUT~
gpio3_io_out_data[0] <= <GND>
gpio3_io_out_data[1] <= <GND>
gpio3_io_out_data[2] <= <GND>
gpio3_io_out_data[3] <= <GND>
gpio3_io_out_data[4] <= <GND>
gpio3_io_out_data[5] <= <GND>
gpio3_io_out_data[6] <= <GND>
gpio3_io_out_data[7] <= <GND>
gpio3_io_out_en[0] <= <GND>
gpio3_io_out_en[1] <= <GND>
gpio3_io_out_en[2] <= <GND>
gpio3_io_out_en[3] <= <GND>
gpio3_io_out_en[4] <= <GND>
gpio3_io_out_en[5] <= <GND>
gpio3_io_out_en[6] <= <GND>
gpio3_io_out_en[7] <= <GND>
gpio4_io_in[0] => ~NO_FANOUT~
gpio4_io_in[1] => ~NO_FANOUT~
gpio4_io_in[2] => ~NO_FANOUT~
gpio4_io_in[3] => ~NO_FANOUT~
gpio4_io_in[4] => ~NO_FANOUT~
gpio4_io_in[5] => ~NO_FANOUT~
gpio4_io_in[6] => ~NO_FANOUT~
gpio4_io_in[7] => ~NO_FANOUT~
gpio4_io_out_data[0] <= <GND>
gpio4_io_out_data[1] <= <GND>
gpio4_io_out_data[2] <= <GND>
gpio4_io_out_data[3] <= <GND>
gpio4_io_out_data[4] <= <GND>
gpio4_io_out_data[5] <= <GND>
gpio4_io_out_data[6] <= <GND>
gpio4_io_out_data[7] <= <GND>
gpio4_io_out_en[0] <= <GND>
gpio4_io_out_en[1] <= <GND>
gpio4_io_out_en[2] <= <GND>
gpio4_io_out_en[3] <= <GND>
gpio4_io_out_en[4] <= <GND>
gpio4_io_out_en[5] <= <GND>
gpio4_io_out_en[6] <= <GND>
gpio4_io_out_en[7] <= <GND>
gpio5_io_in[0] => ~NO_FANOUT~
gpio5_io_in[1] => ~NO_FANOUT~
gpio5_io_in[2] => ~NO_FANOUT~
gpio5_io_in[3] => ~NO_FANOUT~
gpio5_io_in[4] => ~NO_FANOUT~
gpio5_io_in[5] => ~NO_FANOUT~
gpio5_io_in[6] => ~NO_FANOUT~
gpio5_io_in[7] => ~NO_FANOUT~
gpio5_io_out_data[0] <= <GND>
gpio5_io_out_data[1] <= <GND>
gpio5_io_out_data[2] <= <GND>
gpio5_io_out_data[3] <= <GND>
gpio5_io_out_data[4] <= <GND>
gpio5_io_out_data[5] <= <GND>
gpio5_io_out_data[6] <= <GND>
gpio5_io_out_data[7] <= <GND>
gpio5_io_out_en[0] <= <GND>
gpio5_io_out_en[1] <= <GND>
gpio5_io_out_en[2] <= <GND>
gpio5_io_out_en[3] <= <GND>
gpio5_io_out_en[4] <= <GND>
gpio5_io_out_en[5] <= <GND>
gpio5_io_out_en[6] <= <GND>
gpio5_io_out_en[7] <= <GND>
gpio6_io_in[0] => ~NO_FANOUT~
gpio6_io_in[1] => ~NO_FANOUT~
gpio6_io_in[2] => ~NO_FANOUT~
gpio6_io_in[3] => ~NO_FANOUT~
gpio6_io_in[4] => ~NO_FANOUT~
gpio6_io_in[5] => ~NO_FANOUT~
gpio6_io_in[6] => ~NO_FANOUT~
gpio6_io_in[7] => ~NO_FANOUT~
gpio6_io_out_data[0] <= <GND>
gpio6_io_out_data[1] <= <GND>
gpio6_io_out_data[2] <= <GND>
gpio6_io_out_data[3] <= <GND>
gpio6_io_out_data[4] <= <GND>
gpio6_io_out_data[5] <= <GND>
gpio6_io_out_data[6] <= <GND>
gpio6_io_out_data[7] <= <GND>
gpio6_io_out_en[0] <= <GND>
gpio6_io_out_en[1] <= <GND>
gpio6_io_out_en[2] <= <GND>
gpio6_io_out_en[3] <= <GND>
gpio6_io_out_en[4] <= <GND>
gpio6_io_out_en[5] <= <GND>
gpio6_io_out_en[6] <= <GND>
gpio6_io_out_en[7] <= <GND>
gpio7_io_in[0] => ~NO_FANOUT~
gpio7_io_in[1] => ~NO_FANOUT~
gpio7_io_in[2] => ~NO_FANOUT~
gpio7_io_in[3] => ~NO_FANOUT~
gpio7_io_in[4] => ~NO_FANOUT~
gpio7_io_in[5] => ~NO_FANOUT~
gpio7_io_in[6] => ~NO_FANOUT~
gpio7_io_in[7] => ~NO_FANOUT~
gpio7_io_out_data[0] <= <GND>
gpio7_io_out_data[1] <= <GND>
gpio7_io_out_data[2] <= <GND>
gpio7_io_out_data[3] <= <GND>
gpio7_io_out_data[4] <= <GND>
gpio7_io_out_data[5] <= <GND>
gpio7_io_out_data[6] <= <GND>
gpio7_io_out_data[7] <= <GND>
gpio7_io_out_en[0] <= <GND>
gpio7_io_out_en[1] <= <GND>
gpio7_io_out_en[2] <= <GND>
gpio7_io_out_en[3] <= <GND>
gpio7_io_out_en[4] <= <GND>
gpio7_io_out_en[5] <= <GND>
gpio7_io_out_en[6] <= <GND>
gpio7_io_out_en[7] <= <GND>
gpio8_io_in[0] => ~NO_FANOUT~
gpio8_io_in[1] => ~NO_FANOUT~
gpio8_io_in[2] => ~NO_FANOUT~
gpio8_io_in[3] => ~NO_FANOUT~
gpio8_io_in[4] => ~NO_FANOUT~
gpio8_io_in[5] => ~NO_FANOUT~
gpio8_io_in[6] => ~NO_FANOUT~
gpio8_io_in[7] => ~NO_FANOUT~
gpio8_io_out_data[0] <= <GND>
gpio8_io_out_data[1] <= <GND>
gpio8_io_out_data[2] <= <GND>
gpio8_io_out_data[3] <= <GND>
gpio8_io_out_data[4] <= <GND>
gpio8_io_out_data[5] <= <GND>
gpio8_io_out_data[6] <= <GND>
gpio8_io_out_data[7] <= <GND>
gpio8_io_out_en[0] <= <GND>
gpio8_io_out_en[1] <= <GND>
gpio8_io_out_en[2] <= <GND>
gpio8_io_out_en[3] <= <GND>
gpio8_io_out_en[4] <= <GND>
gpio8_io_out_en[5] <= <GND>
gpio8_io_out_en[6] <= <GND>
gpio8_io_out_en[7] <= <GND>
gpio9_io_in[0] => ~NO_FANOUT~
gpio9_io_in[1] => ~NO_FANOUT~
gpio9_io_in[2] => ~NO_FANOUT~
gpio9_io_in[3] => ~NO_FANOUT~
gpio9_io_in[4] => ~NO_FANOUT~
gpio9_io_in[5] => ~NO_FANOUT~
gpio9_io_in[6] => ~NO_FANOUT~
gpio9_io_in[7] => ~NO_FANOUT~
gpio9_io_out_data[0] <= <GND>
gpio9_io_out_data[1] <= <GND>
gpio9_io_out_data[2] <= <GND>
gpio9_io_out_data[3] <= <GND>
gpio9_io_out_data[4] <= <GND>
gpio9_io_out_data[5] <= <GND>
gpio9_io_out_data[6] <= <GND>
gpio9_io_out_data[7] <= <GND>
gpio9_io_out_en[0] <= <GND>
gpio9_io_out_en[1] <= <GND>
gpio9_io_out_en[2] <= <GND>
gpio9_io_out_en[3] <= <GND>
gpio9_io_out_en[4] <= <GND>
gpio9_io_out_en[5] <= <GND>
gpio9_io_out_en[6] <= <GND>
gpio9_io_out_en[7] <= <GND>
ext_resetn => resetn_out.DATAIN
resetn_out <= ext_resetn.DB_MAX_OUTPUT_PORT_TYPE
dmactive <= <GND>
swj_JTAGNSW <= <GND>
swj_JTAGSTATE[0] <= <GND>
swj_JTAGSTATE[1] <= <GND>
swj_JTAGSTATE[2] <= <GND>
swj_JTAGSTATE[3] <= <GND>
swj_JTAGIR[0] <= <GND>
swj_JTAGIR[1] <= <GND>
swj_JTAGIR[2] <= <GND>
swj_JTAGIR[3] <= <GND>
ext_int[0] => ~NO_FANOUT~
ext_int[1] => ~NO_FANOUT~
ext_int[2] => ~NO_FANOUT~
ext_int[3] => ~NO_FANOUT~
ext_int[4] => ~NO_FANOUT~
ext_int[5] => ~NO_FANOUT~
ext_int[6] => ~NO_FANOUT~
ext_int[7] => ~NO_FANOUT~
ext_dma_DMACBREQ[0] => ext_dma_DMACTC[0].DATAIN
ext_dma_DMACBREQ[0] => ext_dma_DMACCLR[0].DATAIN
ext_dma_DMACBREQ[1] => ext_dma_DMACTC[1].DATAIN
ext_dma_DMACBREQ[1] => ext_dma_DMACCLR[1].DATAIN
ext_dma_DMACBREQ[2] => ext_dma_DMACTC[2].DATAIN
ext_dma_DMACBREQ[2] => ext_dma_DMACCLR[2].DATAIN
ext_dma_DMACBREQ[3] => ext_dma_DMACTC[3].DATAIN
ext_dma_DMACBREQ[3] => ext_dma_DMACCLR[3].DATAIN
ext_dma_DMACLBREQ[0] => ~NO_FANOUT~
ext_dma_DMACLBREQ[1] => ~NO_FANOUT~
ext_dma_DMACLBREQ[2] => ~NO_FANOUT~
ext_dma_DMACLBREQ[3] => ~NO_FANOUT~
ext_dma_DMACSREQ[0] => ~NO_FANOUT~
ext_dma_DMACSREQ[1] => ~NO_FANOUT~
ext_dma_DMACSREQ[2] => ~NO_FANOUT~
ext_dma_DMACSREQ[3] => ~NO_FANOUT~
ext_dma_DMACLSREQ[0] => ~NO_FANOUT~
ext_dma_DMACLSREQ[1] => ~NO_FANOUT~
ext_dma_DMACLSREQ[2] => ~NO_FANOUT~
ext_dma_DMACLSREQ[3] => ~NO_FANOUT~
ext_dma_DMACCLR[0] <= ext_dma_DMACBREQ[0].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACCLR[1] <= ext_dma_DMACBREQ[1].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACCLR[2] <= ext_dma_DMACBREQ[2].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACCLR[3] <= ext_dma_DMACBREQ[3].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACTC[0] <= ext_dma_DMACBREQ[0].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACTC[1] <= ext_dma_DMACBREQ[1].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACTC[2] <= ext_dma_DMACBREQ[2].DB_MAX_OUTPUT_PORT_TYPE
ext_dma_DMACTC[3] <= ext_dma_DMACBREQ[3].DB_MAX_OUTPUT_PORT_TYPE
local_int[0] => ~NO_FANOUT~
local_int[1] => ~NO_FANOUT~
local_int[2] => ~NO_FANOUT~
local_int[3] => ~NO_FANOUT~
test_mode[0] => ~NO_FANOUT~
test_mode[1] => ~NO_FANOUT~
usb0_xcvr_clk => sys_ctrl_clkSource[0].DATAIN
usb0_id => ~NO_FANOUT~