2006_APP/logic/alta_db/hold_summary.rpt

=== User constraints ===

Clock transfer report:
  Worst  hold:   0.615, with clock PIN_HSE
  Worst  hold:   0.615, with clock PIN_HSI
  Worst  hold:   0.615, with clock pll_inst|auto_generated|pll1|clk[0]
  Worst  hold:   0.606, with clock pll_inst|auto_generated|pll1|clk[3]
  Worst  hold:   1.740, from clock pll_inst|auto_generated|pll1|clk[0] to pll_inst|auto_generated|pll1|clk[3]
  Worst  hold:   0.818, from clock pll_inst|auto_generated|pll1|clk[3] to pll_inst|auto_generated|pll1|clk[0]

=== Auto constraints ===
Coverage report
  User constraints covered 9470 connections out of 9603 total, coverage: 98.6%
  Auto constraints covered 9470 connections out of 9603 total, coverage: 98.6%


Hold from macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] to macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3], clock pll_inst|auto_generated|pll1|clk[3], constraint 0.000, skew 0.066, data 0.572
  Slack:   0.606
    Arrival Time:    1.296
        0.000    0.000   R                         Launch Clock Edge
      Launch Clock Path:
        0.000    0.000   RR                        test_uart|PIN_HSE =>                      PIN_HSE~input|padio 
        1.309    1.309   RR                      PIN_HSE~input|padio =>                    PIN_HSE~input|combout 
        1.536    0.227   RR                    PIN_HSE~input|combout =>       pll_inst|auto_generated|pll1|clkin 
      Compensation Path:
       -2.400   -3.936   RR       pll_inst|auto_generated|pll1|clkfb =>    pll_inst|auto_generated|pll1|clkfbout 
       -2.400   -0.000   RR    pll_inst|auto_generated|pll1|clkfbout =>       pll_inst|auto_generated|pll1|clkfb 
      Compensation Path End
       -1.420    0.980   RR       pll_inst|auto_generated|pll1|clkin =>     pll_inst|auto_generated|pll1|clkout3 D
       -1.065    0.355   RR     pll_inst|auto_generated|pll1|clkout3 =>                       bus_clk_gclk|inclk D
       -1.065    0.000   RR                       bus_clk_gclk|inclk =>                      bus_clk_gclk|outclk 
        0.445    1.510   RR                      bus_clk_gclk|outclk =>               clken_ctrl_X44_Y3_N0|ClkIn 
        0.593    0.148   RR               clken_ctrl_X44_Y3_N0|ClkIn =>              clken_ctrl_X44_Y3_N0|ClkOut 
        0.724    0.131   RR              clken_ctrl_X44_Y3_N0|ClkOut => macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3]|Clk 
      Data Path:
        0.939    0.215   RR macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3]|Clk => macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3]|Q D
        1.296    0.357   RR macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3]|Q => macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3]|C E
    Required Time:   0.690
        0.000    0.000   R                          Latch Clock Edge
      Latch Clock Path:
        0.000    0.000   RR                        test_uart|PIN_HSE =>                      PIN_HSE~input|padio 
        1.309    1.309   RR                      PIN_HSE~input|padio =>                    PIN_HSE~input|combout 
        1.546    0.237   RR                    PIN_HSE~input|combout =>       pll_inst|auto_generated|pll1|clkin 
      Compensation Path:
       -2.390   -3.936   RR       pll_inst|auto_generated|pll1|clkfb =>    pll_inst|auto_generated|pll1|clkfbout 
       -2.390   -0.000   RR    pll_inst|auto_generated|pll1|clkfbout =>       pll_inst|auto_generated|pll1|clkfb 
      Compensation Path End
       -1.410    0.980   RR       pll_inst|auto_generated|pll1|clkin =>     pll_inst|auto_generated|pll1|clkout3 D
       -1.042    0.368   RR     pll_inst|auto_generated|pll1|clkout3 =>                       bus_clk_gclk|inclk D
       -1.042    0.000   RR                       bus_clk_gclk|inclk =>                      bus_clk_gclk|outclk 
        0.509    1.551   RR                      bus_clk_gclk|outclk =>               clken_ctrl_X44_Y3_N1|ClkIn 
        0.657    0.148   RR               clken_ctrl_X44_Y3_N1|ClkIn =>              clken_ctrl_X44_Y3_N1|ClkOut 
        0.790    0.133   RR              clken_ctrl_X44_Y3_N1|ClkOut => macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3]|Clk 
        0.713   -0.077   R                                      Hold
        0.690   -0.023                               Clock Variation