Analysis & Synthesis report for test_uart Tue Jul 15 16:26:14 2025 Quartus II 64-Bit Version 13.0.0 Build 156 04/24/2013 SJ Full Version --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Analysis & Synthesis Summary 3. Analysis & Synthesis Settings 4. Parallel Compilation 5. Analysis & Synthesis Source Files Read 6. Partition Status Summary 7. Partition for Top-Level Resource Utilization by Entity 8. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state 9. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state 10. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state 11. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state 12. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state 13. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state 14. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state 15. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state 16. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state 17. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state 18. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state 19. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state 20. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state 21. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state 22. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state 23. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state 24. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state 25. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state 26. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state 27. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state 28. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state 29. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state 30. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state 31. State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state 32. State Machine - |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|apbState 33. Registers Removed During Synthesis 34. Removed Registers Triggering Further Register Optimizations 35. Multiplexer Restructuring Statistics (Restructuring Performed) 36. Source assignments for Top-level Entity: |test_uart 37. Parameter Settings for User Entity Instance: altpll:pll_inst 38. Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst 39. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst 40. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb 41. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|apb_mux:u_apb_mux 42. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0] 43. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs 44. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0] 45. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo 46. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1] 47. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo 48. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2] 49. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo 50. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3] 51. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo 52. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4] 53. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo 54. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5] 55. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo 56. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0] 57. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo 58. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1] 59. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo 60. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2] 61. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo 62. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3] 63. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo 64. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4] 65. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo 66. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5] 67. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo 68. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1] 69. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs 70. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0] 71. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo 72. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1] 73. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo 74. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2] 75. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo 76. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3] 77. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo 78. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4] 79. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo 80. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5] 81. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo 82. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0] 83. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo 84. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1] 85. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo 86. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2] 87. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo 88. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3] 89. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo 90. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4] 91. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo 92. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5] 93. Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo 94. Partition Dependent Files 95. Partition "rv32" Resource Utilization by Entity 96. Parameter Settings for User Entity Instance: alta_rv32:rv32 97. Partition Dependent Files 98. Port Connectivity Checks: "alta_rv32:rv32" 99. Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[1]" 100. Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[0]" 101. Port Connectivity Checks: "multi_uart_ip:macro_inst|apb_mux:u_apb_mux" 102. Port Connectivity Checks: "multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb" 103. Port Connectivity Checks: "multi_uart_ip:macro_inst" 104. Port Connectivity Checks: "alta_gclksw:gclksw_inst" 105. Elapsed Time Per Partition 106. Analysis & Synthesis Messages 107. Analysis & Synthesis Suppressed Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 1991-2013 Altera Corporation Your use of Altera Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Altera Program License Subscription Agreement, Altera MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Altera and sold by Altera or its authorized distributors. Please refer to the applicable agreement for further details. +----------------------------------------------------------------------------------+ ; Analysis & Synthesis Summary ; +------------------------------------+---------------------------------------------+ ; Analysis & Synthesis Status ; Successful - Tue Jul 15 16:26:14 2025 ; ; Quartus II 64-Bit Version ; 13.0.0 Build 156 04/24/2013 SJ Full Version ; ; Revision Name ; test_uart ; ; Top-level Entity Name ; test_uart ; ; Family ; Cyclone IV E ; ; Total logic elements ; N/A until Partition Merge ; ; Total combinational functions ; N/A until Partition Merge ; ; Dedicated logic registers ; N/A until Partition Merge ; ; Total registers ; N/A until Partition Merge ; ; Total pins ; N/A until Partition Merge ; ; Total virtual pins ; N/A until Partition Merge ; ; Total memory bits ; N/A until Partition Merge ; ; Embedded Multiplier 9-bit elements ; N/A until Partition Merge ; ; Total PLLs ; N/A until Partition Merge ; +------------------------------------+---------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Settings ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Option ; Setting ; Default Value ; +----------------------------------------------------------------------------+--------------------+--------------------+ ; Device ; EP4CE75F29C8 ; ; ; Top-level entity name ; test_uart ; test_uart ; ; Family name ; Cyclone IV E ; Cyclone V ; ; Maximum processors allowed for parallel compilation ; All ; ; ; Maximum DSP Block Usage ; 0 ; -1 (Unlimited) ; ; Auto Open-Drain Pins ; Off ; On ; ; Perform WYSIWYG Primitive Resynthesis ; On ; Off ; ; Maximum Number of M4K/M9K/M20K/M10K Memory Blocks ; 4 ; -1 (Unlimited) ; ; Use smart compilation ; Off ; Off ; ; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; ; Enable compact report table ; Off ; Off ; ; Restructure Multiplexers ; Auto ; Auto ; ; Create Debugging Nodes for IP Cores ; Off ; Off ; ; Preserve fewer node names ; On ; On ; ; Disable OpenCore Plus hardware evaluation ; Off ; Off ; ; Verilog Version ; Verilog_2001 ; Verilog_2001 ; ; VHDL Version ; VHDL_1993 ; VHDL_1993 ; ; State Machine Processing ; Auto ; Auto ; ; Safe State Machine ; Off ; Off ; ; Extract Verilog State Machines ; On ; On ; ; Extract VHDL State Machines ; On ; On ; ; Ignore Verilog initial constructs ; Off ; Off ; ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ; ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ; ; Add Pass-Through Logic to Inferred RAMs ; On ; On ; ; Infer RAMs from Raw Logic ; On ; On ; ; Parallel Synthesis ; On ; On ; ; DSP Block Balancing ; Auto ; Auto ; ; NOT Gate Push-Back ; On ; On ; ; Power-Up Don't Care ; On ; On ; ; Remove Redundant Logic Cells ; Off ; Off ; ; Remove Duplicate Registers ; On ; On ; ; Ignore CARRY Buffers ; Off ; Off ; ; Ignore CASCADE Buffers ; Off ; Off ; ; Ignore GLOBAL Buffers ; Off ; Off ; ; Ignore ROW GLOBAL Buffers ; Off ; Off ; ; Ignore LCELL Buffers ; Off ; Off ; ; Ignore SOFT Buffers ; On ; On ; ; Limit AHDL Integers to 32 Bits ; Off ; Off ; ; Optimization Technique ; Balanced ; Balanced ; ; Carry Chain Length ; 70 ; 70 ; ; Auto Carry Chains ; On ; On ; ; Auto ROM Replacement ; On ; On ; ; Auto RAM Replacement ; On ; On ; ; Auto DSP Block Replacement ; On ; On ; ; Auto Shift Register Replacement ; Auto ; Auto ; ; Allow Shift Register Merging across Hierarchies ; Auto ; Auto ; ; Auto Clock Enable Replacement ; On ; On ; ; Strict RAM Replacement ; Off ; Off ; ; Allow Synchronous Control Signals ; On ; On ; ; Force Use of Synchronous Clear Signals ; Off ; Off ; ; Auto RAM Block Balancing ; On ; On ; ; Auto RAM to Logic Cell Conversion ; Off ; Off ; ; Auto Resource Sharing ; Off ; Off ; ; Allow Any RAM Size For Recognition ; Off ; Off ; ; Allow Any ROM Size For Recognition ; Off ; Off ; ; Allow Any Shift Register Size For Recognition ; Off ; Off ; ; Use LogicLock Constraints during Resource Balancing ; On ; On ; ; Ignore translate_off and synthesis_off directives ; Off ; Off ; ; Timing-Driven Synthesis ; On ; On ; ; Report Parameter Settings ; On ; On ; ; Report Source Assignments ; On ; On ; ; Report Connectivity Checks ; On ; On ; ; Ignore Maximum Fan-Out Assignments ; Off ; Off ; ; Synchronization Register Chain Length ; 2 ; 2 ; ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ; ; HDL message level ; Level2 ; Level2 ; ; Suppress Register Optimization Related Messages ; Off ; Off ; ; Number of Removed Registers Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Swept Nodes Reported in Synthesis Report ; 5000 ; 5000 ; ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ; ; Clock MUX Protection ; On ; On ; ; Auto Gated Clock Conversion ; Off ; Off ; ; Block Design Naming ; Auto ; Auto ; ; SDC constraint protection ; Off ; Off ; ; Synthesis Effort ; Auto ; Auto ; ; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ; ; Pre-Mapping Resynthesis Optimization ; Off ; Off ; ; Analysis & Synthesis Message Level ; Medium ; Medium ; ; Disable Register Merging Across Hierarchies ; Auto ; Auto ; ; Resource Aware Inference For Block RAM ; On ; On ; ; Synthesis Seed ; 1 ; 1 ; +----------------------------------------------------------------------------+--------------------+--------------------+ +------------------------------------------+ ; Parallel Compilation ; +----------------------------+-------------+ ; Processors ; Number ; +----------------------------+-------------+ ; Number detected on machine ; 8 ; ; Maximum allowed ; 4 ; ; ; ; ; Average used ; 1.89 ; ; Maximum used ; 2 ; ; ; ; ; Usage by Processor ; % Time Used ; ; Processor 1 ; 100.0% ; ; Processor 2 ; 88.9% ; ; Processors 3-8 ; 0.0% ; +----------------------------+-------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Analysis & Synthesis Source Files Read ; +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+ ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ; Library ; +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+ ; test_uart.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/test_uart.v ; ; ; multi_uart_ip.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip.v ; ; ; multi_uart_ip/baud_gen.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/baud_gen.v ; ; ; multi_uart_ip/multi_uart.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/multi_uart.v ; ; ; multi_uart_ip/sync_fifo.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/sync_fifo.v ; ; ; multi_uart_ip/uart_regs.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/uart_regs.v ; ; ; multi_uart_ip/uart_rx.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/uart_rx.v ; ; ; multi_uart_ip/uart_tx.v ; yes ; User Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/multi_uart_ip/uart_tx.v ; ; ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; yes ; User Verilog HDL File ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; ; ; altpll.tdf ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/altpll.tdf ; ; ; aglobal130.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/aglobal130.inc ; ; ; stratix_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratix_pll.inc ; ; ; stratixii_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/stratixii_pll.inc ; ; ; cycloneii_pll.inc ; yes ; Megafunction ; c:/altera/13.0/quartus/libraries/megafunctions/cycloneii_pll.inc ; ; ; db/altpll_9g32.tdf ; yes ; Auto-Generated Megafunction ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/db/altpll_9g32.tdf ; ; ; ahb2apb.v ; yes ; Auto-Found Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/ahb2apb.v ; ; ; apb_mux.v ; yes ; Auto-Found Verilog HDL File ; D:/LYW/NEW_DECODE/2006_APP_s2/logic/apb_mux.v ; ; +---------------------------------------------------------------------------------+-----------------+------------------------------+---------------------------------------------------------------------------------+---------+ +-----------------------------------------------------------+ ; Partition Status Summary ; +----------------+-------------+----------------------------+ ; Partition Name ; Synthesized ; Reason ; +----------------+-------------+----------------------------+ ; rv32 ; yes ; netlist type = Source File ; ; Top ; yes ; netlist type = Source File ; +----------------+-------------+----------------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Partition for Top-Level Resource Utilization by Entity ; +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+--------------+ ; |test_uart ; 1889 (127) ; 1303 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart ; work ; ; |alta_gclksw:gclksw_inst| ; 0 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|alta_gclksw:gclksw_inst ; work ; ; |altpll:pll_inst| ; 0 (0) ; 1 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|altpll:pll_inst ; work ; ; |altpll_9g32:auto_generated| ; 0 (0) ; 1 (1) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|altpll:pll_inst|altpll_9g32:auto_generated ; work ; ; |multi_uart_ip:macro_inst| ; 1762 (27) ; 1302 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst ; work ; ; |ahb2apb:u_ahb2apb| ; 13 (13) ; 47 (47) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb ; work ; ; |apb_mux:u_apb_mux| ; 19 (19) ; 2 (2) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|apb_mux:u_apb_mux ; work ; ; |multi_uart:u_uart[0]| ; 859 (0) ; 624 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0] ; work ; ; |baud_gen:u_baud| ; 35 (35) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|baud_gen:u_baud ; work ; ; |uart_regs:u_regs| ; 247 (247) ; 134 (134) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs ; work ; ; |uart_rx:u_rx[0]| ; 55 (53) ; 44 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[1]| ; 55 (53) ; 44 (35) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[2]| ; 54 (52) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[3]| ; 54 (52) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[4]| ; 54 (52) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[5]| ; 57 (55) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ; work ; ; |uart_tx:u_tx[0]| ; 42 (40) ; 35 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[1]| ; 42 (40) ; 35 (26) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[2]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[3]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[4]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[5]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ; work ; ; |multi_uart:u_uart[1]| ; 844 (0) ; 620 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1] ; work ; ; |baud_gen:u_baud| ; 35 (35) ; 24 (24) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|baud_gen:u_baud ; work ; ; |uart_regs:u_regs| ; 232 (232) ; 134 (134) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs ; work ; ; |uart_rx:u_rx[0]| ; 54 (52) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[1]| ; 55 (53) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[2]| ; 56 (54) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[3]| ; 54 (52) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[4]| ; 54 (52) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ; work ; ; |uart_rx:u_rx[5]| ; 57 (55) ; 43 (34) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5] ; work ; ; |sync_fifo:rx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ; work ; ; |uart_tx:u_tx[0]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[1]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[2]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[3]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[4]| ; 42 (40) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ; work ; ; |uart_tx:u_tx[5]| ; 41 (39) ; 34 (25) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5] ; work ; ; |sync_fifo:tx_fifo| ; 2 (2) ; 9 (9) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ; work ; +------------------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+--------------------------------------------------------------------------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; rx_state.UART_PARITY ; rx_state.UART_DATA ; rx_state.UART_START ; rx_state.UART_IDLE ; rx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; rx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; rx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; rx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; rx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; rx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +----------------------------------------------------------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; Name ; tx_state.UART_PARITY ; tx_state.UART_DATA ; tx_state.UART_START ; tx_state.UART_IDLE ; tx_state.UART_STOP ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ ; tx_state.UART_IDLE ; 0 ; 0 ; 0 ; 0 ; 0 ; ; tx_state.UART_START ; 0 ; 0 ; 1 ; 1 ; 0 ; ; tx_state.UART_DATA ; 0 ; 1 ; 0 ; 1 ; 0 ; ; tx_state.UART_PARITY ; 1 ; 0 ; 0 ; 1 ; 0 ; ; tx_state.UART_STOP ; 0 ; 0 ; 0 ; 1 ; 1 ; +----------------------+----------------------+--------------------+---------------------+--------------------+--------------------+ Encoding Type: One-Hot +--------------------------------------------------------------------------------+ ; State Machine - |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|apbState ; +--------------------+------------------+--------------------+-------------------+ ; Name ; apbState.apbIdle ; apbState.apbAccess ; apbState.apbSetup ; +--------------------+------------------+--------------------+-------------------+ ; apbState.apbIdle ; 0 ; 0 ; 0 ; ; apbState.apbSetup ; 1 ; 0 ; 1 ; ; apbState.apbAccess ; 1 ; 1 ; 0 ; +--------------------+------------------+--------------------+-------------------+ +------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Registers Removed During Synthesis ; +-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+ ; Register name ; Reason for Removal ; +-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+ ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[16..31] ; Stuck at GND due to stuck port data_in ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[16..31] ; Stuck at GND due to stuck port data_in ; ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[16..31] ; Stuck at GND due to stuck port data_in ; ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|hresp ; Stuck at GND due to stuck port data_in ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state~4 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_state~5 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state~7 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_state~8 ; Lost fanout ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|status_reg[3] ; Merged with multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|status_reg[1] ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|status_reg[3] ; Merged with multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|status_reg[1] ; ; Total Number of Removed Registers = 99 ; ; +-----------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+ +-------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Removed Registers Triggering Further Register Optimizations ; +-------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------+ ; Register name ; Reason for Removal ; Registers Removed due to This Register ; +-------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------+ ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[31] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[31] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[30] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[30] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[29] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[29] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[28] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[28] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[27] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[27] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[26] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[26] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[25] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[25] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[24] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[24] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[23] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[23] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[22] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[22] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[21] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[21] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[20] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[20] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[19] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[19] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[18] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[18] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[17] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[17] ; ; ; due to stuck port data_in ; ; ; multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[16] ; Stuck at GND ; multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|prdata[16] ; ; ; due to stuck port data_in ; ; +-------------------------------------------------------------------------------+---------------------------+-------------------------------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Multiplexer Restructuring Statistics (Restructuring Performed) ; +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------+ ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ; +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------+ ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_data_cnt[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|tx_shift_reg[3] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_data_cnt[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|tx_shift_reg[4] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_data_cnt[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|tx_shift_reg[2] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_data_cnt[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|tx_shift_reg[7] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_data_cnt[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|tx_shift_reg[7] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_data_cnt[2] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|tx_shift_reg[5] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_data_cnt[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|tx_shift_reg[5] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_data_cnt[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|tx_shift_reg[3] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_data_cnt[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|tx_shift_reg[3] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_data_cnt[0] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|tx_shift_reg[5] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_data_cnt[1] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|tx_shift_reg[7] ; ; 3:1 ; 3 bits ; 6 LEs ; 3 LEs ; 3 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_data_cnt[1] ; ; 3:1 ; 8 bits ; 16 LEs ; 8 LEs ; 8 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|tx_shift_reg[2] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|rx_data_cnt[2] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|rx_data_cnt[1] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|rx_data_cnt[0] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|rx_data_cnt[2] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|rx_data_cnt[1] ; ; 4:1 ; 3 bits ; 6 LEs ; 6 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|rx_data_cnt[1] ; ; 8:1 ; 16 bits ; 80 LEs ; 64 LEs ; 16 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|rx_reg[5] ; ; 6:1 ; 10 bits ; 40 LEs ; 40 LEs ; 0 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|status_reg[1] ; ; 4:1 ; 11 bits ; 22 LEs ; 0 LEs ; 22 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb|pwrite ; ; 64:1 ; 2 bits ; 84 LEs ; 10 LEs ; 74 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[6] ; ; 69:1 ; 10 bits ; 460 LEs ; 50 LEs ; 410 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[11] ; ; 69:1 ; 2 bits ; 92 LEs ; 14 LEs ; 78 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[2] ; ; 69:1 ; 2 bits ; 92 LEs ; 18 LEs ; 74 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|apb_prdata[7] ; ; 69:1 ; 2 bits ; 92 LEs ; 18 LEs ; 74 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[3] ; ; 74:1 ; 2 bits ; 98 LEs ; 24 LEs ; 74 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[0] ; ; 74:1 ; 2 bits ; 98 LEs ; 24 LEs ; 74 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[1] ; ; 74:1 ; 4 bits ; 196 LEs ; 44 LEs ; 152 LEs ; Yes ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs|apb_prdata[4] ; ; 3:1 ; 2 bits ; 4 LEs ; 2 LEs ; 2 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs|ShiftLeft0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|Selector1 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|Selector1 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|Selector1 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|Selector0 ; ; 8:1 ; 2 bits ; 10 LEs ; 4 LEs ; 6 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|Selector0 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|Selector3 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|Selector0 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|Selector3 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|Selector3 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|Selector3 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|Selector4 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|Selector3 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|Selector0 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|Selector4 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|Selector4 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|Selector4 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|Selector2 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|Selector4 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|Selector0 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|Selector3 ; ; 10:1 ; 3 bits ; 18 LEs ; 9 LEs ; 9 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|Selector1 ; ; 10:1 ; 2 bits ; 12 LEs ; 4 LEs ; 8 LEs ; No ; |test_uart|multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|Selector3 ; +--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------------------------------------------------------------+ +---------------------------------------------------------------------+ ; Source assignments for Top-level Entity: |test_uart ; +------------------------------+-------+------+-----------------------+ ; Assignment ; Value ; From ; To ; +------------------------------+-------+------+-----------------------+ ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio3_io_in[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio3_io_in[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio4_io_in[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio4_io_in[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio5_io_in[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio5_io_in[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_in[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_in[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_in[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_in[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_in[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_in[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; PLL_ENABLE ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; PLL_ENABLE ; ; IGNORE_LCELL_BUFFERS ; off ; - ; PLL_LOCK ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; PLL_LOCK ; ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_resetn ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_resetn ; ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_stop ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_stop ; ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_clkSource[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_clkSource[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; sys_ctrl_clkSource[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; sys_ctrl_clkSource[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_data[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_data[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio1_io_out_en[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio1_io_out_en[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_data[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_data[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio2_io_out_en[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio2_io_out_en[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_data[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_data[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio6_io_out_en[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio6_io_out_en[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_out_data[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_out_data[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio7_io_out_en[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio7_io_out_en[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_data[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_data[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio8_io_out_en[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio8_io_out_en[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_data[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_data[0] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[7] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[7] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[6] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[6] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[5] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[5] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[4] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[4] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[3] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[3] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[2] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[2] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[1] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[1] ; ; IGNORE_LCELL_BUFFERS ; off ; - ; gpio9_io_out_en[0] ; ; REMOVE_REDUNDANT_LOGIC_CELLS ; off ; - ; gpio9_io_out_en[0] ; +------------------------------+-------+------+-----------------------+ +--------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: altpll:pll_inst ; +-------------------------------+-------------------+----------------+ ; Parameter Name ; Value ; Type ; +-------------------------------+-------------------+----------------+ ; OPERATION_MODE ; NORMAL ; Untyped ; ; PLL_TYPE ; AUTO ; Untyped ; ; LPM_HINT ; UNUSED ; Untyped ; ; QUALIFY_CONF_DONE ; OFF ; Untyped ; ; COMPENSATE_CLOCK ; CLK0 ; Untyped ; ; SCAN_CHAIN ; LONG ; Untyped ; ; PRIMARY_CLOCK ; INCLK0 ; Untyped ; ; INCLK0_INPUT_FREQUENCY ; 125000 ; Signed Integer ; ; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ; ; GATE_LOCK_SIGNAL ; NO ; Untyped ; ; GATE_LOCK_COUNTER ; 0 ; Untyped ; ; LOCK_HIGH ; 1 ; Untyped ; ; LOCK_LOW ; 1 ; Untyped ; ; VALID_LOCK_MULTIPLIER ; 1 ; Untyped ; ; INVALID_LOCK_MULTIPLIER ; 5 ; Untyped ; ; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ; ; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ; ; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ; ; SKIP_VCO ; OFF ; Untyped ; ; SWITCH_OVER_COUNTER ; 0 ; Untyped ; ; SWITCH_OVER_TYPE ; AUTO ; Untyped ; ; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ; ; BANDWIDTH ; 0 ; Untyped ; ; BANDWIDTH_TYPE ; AUTO ; Untyped ; ; SPREAD_FREQUENCY ; 0 ; Untyped ; ; DOWN_SPREAD ; 0 ; Untyped ; ; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ; ; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ; ; CLK9_MULTIPLY_BY ; 0 ; Untyped ; ; CLK8_MULTIPLY_BY ; 0 ; Untyped ; ; CLK7_MULTIPLY_BY ; 0 ; Untyped ; ; CLK6_MULTIPLY_BY ; 0 ; Untyped ; ; CLK5_MULTIPLY_BY ; 1 ; Untyped ; ; CLK4_MULTIPLY_BY ; 120 ; Signed Integer ; ; CLK3_MULTIPLY_BY ; 120 ; Signed Integer ; ; CLK2_MULTIPLY_BY ; 120 ; Signed Integer ; ; CLK1_MULTIPLY_BY ; 120 ; Signed Integer ; ; CLK0_MULTIPLY_BY ; 120 ; Signed Integer ; ; CLK9_DIVIDE_BY ; 0 ; Untyped ; ; CLK8_DIVIDE_BY ; 0 ; Untyped ; ; CLK7_DIVIDE_BY ; 0 ; Untyped ; ; CLK6_DIVIDE_BY ; 0 ; Untyped ; ; CLK5_DIVIDE_BY ; 1 ; Untyped ; ; CLK4_DIVIDE_BY ; 4 ; Signed Integer ; ; CLK3_DIVIDE_BY ; 8 ; Signed Integer ; ; CLK2_DIVIDE_BY ; 4 ; Signed Integer ; ; CLK1_DIVIDE_BY ; 4 ; Signed Integer ; ; CLK0_DIVIDE_BY ; 4 ; Signed Integer ; ; CLK9_PHASE_SHIFT ; 0 ; Untyped ; ; CLK8_PHASE_SHIFT ; 0 ; Untyped ; ; CLK7_PHASE_SHIFT ; 0 ; Untyped ; ; CLK6_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_PHASE_SHIFT ; 0 ; Untyped ; ; CLK4_PHASE_SHIFT ; 0 ; Untyped ; ; CLK3_PHASE_SHIFT ; 0 ; Untyped ; ; CLK2_PHASE_SHIFT ; 0 ; Untyped ; ; CLK1_PHASE_SHIFT ; 0 ; Untyped ; ; CLK0_PHASE_SHIFT ; 0 ; Untyped ; ; CLK5_TIME_DELAY ; 0 ; Untyped ; ; CLK4_TIME_DELAY ; 0 ; Untyped ; ; CLK3_TIME_DELAY ; 0 ; Untyped ; ; CLK2_TIME_DELAY ; 0 ; Untyped ; ; CLK1_TIME_DELAY ; 0 ; Untyped ; ; CLK0_TIME_DELAY ; 0 ; Untyped ; ; CLK9_DUTY_CYCLE ; 50 ; Untyped ; ; CLK8_DUTY_CYCLE ; 50 ; Untyped ; ; CLK7_DUTY_CYCLE ; 50 ; Untyped ; ; CLK6_DUTY_CYCLE ; 50 ; Untyped ; ; CLK5_DUTY_CYCLE ; 50 ; Untyped ; ; CLK4_DUTY_CYCLE ; 50 ; Untyped ; ; CLK3_DUTY_CYCLE ; 50 ; Untyped ; ; CLK2_DUTY_CYCLE ; 50 ; Untyped ; ; CLK1_DUTY_CYCLE ; 50 ; Untyped ; ; CLK0_DUTY_CYCLE ; 50 ; Untyped ; ; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ; ; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ; ; LOCK_WINDOW_UI ; 0.05 ; Untyped ; ; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ; ; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ; ; DPA_MULTIPLY_BY ; 0 ; Untyped ; ; DPA_DIVIDE_BY ; 1 ; Untyped ; ; DPA_DIVIDER ; 0 ; Untyped ; ; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ; ; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ; ; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ; ; EXTCLK3_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK2_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK1_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK0_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ; ; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ; ; VCO_MULTIPLY_BY ; 0 ; Untyped ; ; VCO_DIVIDE_BY ; 0 ; Untyped ; ; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ; ; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ; ; VCO_MIN ; 0 ; Untyped ; ; VCO_MAX ; 0 ; Untyped ; ; VCO_CENTER ; 0 ; Untyped ; ; PFD_MIN ; 0 ; Untyped ; ; PFD_MAX ; 0 ; Untyped ; ; M_INITIAL ; 0 ; Untyped ; ; M ; 0 ; Untyped ; ; N ; 1 ; Untyped ; ; M2 ; 1 ; Untyped ; ; N2 ; 1 ; Untyped ; ; SS ; 1 ; Untyped ; ; C0_HIGH ; 0 ; Untyped ; ; C1_HIGH ; 0 ; Untyped ; ; C2_HIGH ; 0 ; Untyped ; ; C3_HIGH ; 0 ; Untyped ; ; C4_HIGH ; 0 ; Untyped ; ; C5_HIGH ; 0 ; Untyped ; ; C6_HIGH ; 0 ; Untyped ; ; C7_HIGH ; 0 ; Untyped ; ; C8_HIGH ; 0 ; Untyped ; ; C9_HIGH ; 0 ; Untyped ; ; C0_LOW ; 0 ; Untyped ; ; C1_LOW ; 0 ; Untyped ; ; C2_LOW ; 0 ; Untyped ; ; C3_LOW ; 0 ; Untyped ; ; C4_LOW ; 0 ; Untyped ; ; C5_LOW ; 0 ; Untyped ; ; C6_LOW ; 0 ; Untyped ; ; C7_LOW ; 0 ; Untyped ; ; C8_LOW ; 0 ; Untyped ; ; C9_LOW ; 0 ; Untyped ; ; C0_INITIAL ; 0 ; Untyped ; ; C1_INITIAL ; 0 ; Untyped ; ; C2_INITIAL ; 0 ; Untyped ; ; C3_INITIAL ; 0 ; Untyped ; ; C4_INITIAL ; 0 ; Untyped ; ; C5_INITIAL ; 0 ; Untyped ; ; C6_INITIAL ; 0 ; Untyped ; ; C7_INITIAL ; 0 ; Untyped ; ; C8_INITIAL ; 0 ; Untyped ; ; C9_INITIAL ; 0 ; Untyped ; ; C0_MODE ; BYPASS ; Untyped ; ; C1_MODE ; BYPASS ; Untyped ; ; C2_MODE ; BYPASS ; Untyped ; ; C3_MODE ; BYPASS ; Untyped ; ; C4_MODE ; BYPASS ; Untyped ; ; C5_MODE ; BYPASS ; Untyped ; ; C6_MODE ; BYPASS ; Untyped ; ; C7_MODE ; BYPASS ; Untyped ; ; C8_MODE ; BYPASS ; Untyped ; ; C9_MODE ; BYPASS ; Untyped ; ; C0_PH ; 0 ; Untyped ; ; C1_PH ; 0 ; Untyped ; ; C2_PH ; 0 ; Untyped ; ; C3_PH ; 0 ; Untyped ; ; C4_PH ; 0 ; Untyped ; ; C5_PH ; 0 ; Untyped ; ; C6_PH ; 0 ; Untyped ; ; C7_PH ; 0 ; Untyped ; ; C8_PH ; 0 ; Untyped ; ; C9_PH ; 0 ; Untyped ; ; L0_HIGH ; 1 ; Untyped ; ; L1_HIGH ; 1 ; Untyped ; ; G0_HIGH ; 1 ; Untyped ; ; G1_HIGH ; 1 ; Untyped ; ; G2_HIGH ; 1 ; Untyped ; ; G3_HIGH ; 1 ; Untyped ; ; E0_HIGH ; 1 ; Untyped ; ; E1_HIGH ; 1 ; Untyped ; ; E2_HIGH ; 1 ; Untyped ; ; E3_HIGH ; 1 ; Untyped ; ; L0_LOW ; 1 ; Untyped ; ; L1_LOW ; 1 ; Untyped ; ; G0_LOW ; 1 ; Untyped ; ; G1_LOW ; 1 ; Untyped ; ; G2_LOW ; 1 ; Untyped ; ; G3_LOW ; 1 ; Untyped ; ; E0_LOW ; 1 ; Untyped ; ; E1_LOW ; 1 ; Untyped ; ; E2_LOW ; 1 ; Untyped ; ; E3_LOW ; 1 ; Untyped ; ; L0_INITIAL ; 1 ; Untyped ; ; L1_INITIAL ; 1 ; Untyped ; ; G0_INITIAL ; 1 ; Untyped ; ; G1_INITIAL ; 1 ; Untyped ; ; G2_INITIAL ; 1 ; Untyped ; ; G3_INITIAL ; 1 ; Untyped ; ; E0_INITIAL ; 1 ; Untyped ; ; E1_INITIAL ; 1 ; Untyped ; ; E2_INITIAL ; 1 ; Untyped ; ; E3_INITIAL ; 1 ; Untyped ; ; L0_MODE ; BYPASS ; Untyped ; ; L1_MODE ; BYPASS ; Untyped ; ; G0_MODE ; BYPASS ; Untyped ; ; G1_MODE ; BYPASS ; Untyped ; ; G2_MODE ; BYPASS ; Untyped ; ; G3_MODE ; BYPASS ; Untyped ; ; E0_MODE ; BYPASS ; Untyped ; ; E1_MODE ; BYPASS ; Untyped ; ; E2_MODE ; BYPASS ; Untyped ; ; E3_MODE ; BYPASS ; Untyped ; ; L0_PH ; 0 ; Untyped ; ; L1_PH ; 0 ; Untyped ; ; G0_PH ; 0 ; Untyped ; ; G1_PH ; 0 ; Untyped ; ; G2_PH ; 0 ; Untyped ; ; G3_PH ; 0 ; Untyped ; ; E0_PH ; 0 ; Untyped ; ; E1_PH ; 0 ; Untyped ; ; E2_PH ; 0 ; Untyped ; ; E3_PH ; 0 ; Untyped ; ; M_PH ; 0 ; Untyped ; ; C1_USE_CASC_IN ; OFF ; Untyped ; ; C2_USE_CASC_IN ; OFF ; Untyped ; ; C3_USE_CASC_IN ; OFF ; Untyped ; ; C4_USE_CASC_IN ; OFF ; Untyped ; ; C5_USE_CASC_IN ; OFF ; Untyped ; ; C6_USE_CASC_IN ; OFF ; Untyped ; ; C7_USE_CASC_IN ; OFF ; Untyped ; ; C8_USE_CASC_IN ; OFF ; Untyped ; ; C9_USE_CASC_IN ; OFF ; Untyped ; ; CLK0_COUNTER ; G0 ; Untyped ; ; CLK1_COUNTER ; G0 ; Untyped ; ; CLK2_COUNTER ; G0 ; Untyped ; ; CLK3_COUNTER ; G0 ; Untyped ; ; CLK4_COUNTER ; G0 ; Untyped ; ; CLK5_COUNTER ; G0 ; Untyped ; ; CLK6_COUNTER ; E0 ; Untyped ; ; CLK7_COUNTER ; E1 ; Untyped ; ; CLK8_COUNTER ; E2 ; Untyped ; ; CLK9_COUNTER ; E3 ; Untyped ; ; L0_TIME_DELAY ; 0 ; Untyped ; ; L1_TIME_DELAY ; 0 ; Untyped ; ; G0_TIME_DELAY ; 0 ; Untyped ; ; G1_TIME_DELAY ; 0 ; Untyped ; ; G2_TIME_DELAY ; 0 ; Untyped ; ; G3_TIME_DELAY ; 0 ; Untyped ; ; E0_TIME_DELAY ; 0 ; Untyped ; ; E1_TIME_DELAY ; 0 ; Untyped ; ; E2_TIME_DELAY ; 0 ; Untyped ; ; E3_TIME_DELAY ; 0 ; Untyped ; ; M_TIME_DELAY ; 0 ; Untyped ; ; N_TIME_DELAY ; 0 ; Untyped ; ; EXTCLK3_COUNTER ; E3 ; Untyped ; ; EXTCLK2_COUNTER ; E2 ; Untyped ; ; EXTCLK1_COUNTER ; E1 ; Untyped ; ; EXTCLK0_COUNTER ; E0 ; Untyped ; ; ENABLE0_COUNTER ; L0 ; Untyped ; ; ENABLE1_COUNTER ; L0 ; Untyped ; ; CHARGE_PUMP_CURRENT ; 2 ; Untyped ; ; LOOP_FILTER_R ; 1.000000 ; Untyped ; ; LOOP_FILTER_C ; 5 ; Untyped ; ; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_R_BITS ; 9999 ; Untyped ; ; LOOP_FILTER_C_BITS ; 9999 ; Untyped ; ; VCO_POST_SCALE ; 0 ; Untyped ; ; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ; ; INTENDED_DEVICE_FAMILY ; Cyclone IV E ; Untyped ; ; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK0 ; PORT_USED ; Untyped ; ; PORT_CLK1 ; PORT_UNUSED ; Untyped ; ; PORT_CLK2 ; PORT_UNUSED ; Untyped ; ; PORT_CLK3 ; PORT_USED ; Untyped ; ; PORT_CLK4 ; PORT_UNUSED ; Untyped ; ; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLK6 ; PORT_UNUSED ; Untyped ; ; PORT_CLK7 ; PORT_UNUSED ; Untyped ; ; PORT_CLK8 ; PORT_UNUSED ; Untyped ; ; PORT_CLK9 ; PORT_UNUSED ; Untyped ; ; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_INCLK0 ; PORT_USED ; Untyped ; ; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ARESET ; PORT_USED ; Untyped ; ; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ; ; PORT_LOCKED ; PORT_USED ; Untyped ; ; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ; ; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ; ; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ; ; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ; ; M_TEST_SOURCE ; 5 ; Untyped ; ; C0_TEST_SOURCE ; 5 ; Untyped ; ; C1_TEST_SOURCE ; 5 ; Untyped ; ; C2_TEST_SOURCE ; 5 ; Untyped ; ; C3_TEST_SOURCE ; 5 ; Untyped ; ; C4_TEST_SOURCE ; 5 ; Untyped ; ; C5_TEST_SOURCE ; 5 ; Untyped ; ; C6_TEST_SOURCE ; 5 ; Untyped ; ; C7_TEST_SOURCE ; 5 ; Untyped ; ; C8_TEST_SOURCE ; 5 ; Untyped ; ; C9_TEST_SOURCE ; 5 ; Untyped ; ; CBXI_PARAMETER ; altpll_9g32 ; Untyped ; ; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ; ; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ; ; WIDTH_CLOCK ; 5 ; Signed Integer ; ; WIDTH_PHASECOUNTERSELECT ; 3 ; Signed Integer ; ; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ; ; DEVICE_FAMILY ; Cyclone IV E ; Untyped ; ; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ; ; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ; ; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ; ; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ; ; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ; ; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ; +-------------------------------+-------------------+----------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +----------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: alta_gclksw:gclksw_inst ; +----------------+-------+---------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+---------------------------------------------+ ; coord_x ; 0 ; Signed Integer ; ; coord_y ; 0 ; Signed Integer ; ; coord_z ; 0 ; Signed Integer ; ; ENA_REG_MODE ; 0 ; Unsigned Binary ; +----------------+-------+---------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst ; +----------------+-------+----------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------+ ; UART_GROUP ; 2 ; Signed Integer ; ; UART_COUNT ; 6 ; Signed Integer ; ; UART_TOTAL ; 12 ; Signed Integer ; +----------------+-------+----------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb ; +----------------+-------+----------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------+ ; ADDR_BITS ; 13 ; Signed Integer ; ; DATA_BITS ; 32 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|apb_mux:u_apb_mux ; +----------------+-------+----------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+----------------------------------------------------------------+ ; APB_CNT ; 2 ; Signed Integer ; ; ADDR_BITS ; 12 ; Signed Integer ; ; DATA_BITS ; 32 ; Signed Integer ; +----------------+-------+----------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0] ; +----------------+-------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------+ ; CNT ; 6 ; Signed Integer ; ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs ; +----------------+-------+------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------------------+ ; CNT ; 6 ; Signed Integer ; ; DATA_WIDTH ; 8 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +--------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1] ; +----------------+-------+-------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-------------------------------------------------------------------+ ; CNT ; 6 ; Signed Integer ; ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_regs:u_regs ; +----------------+-------+------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------------------------------------------------------+ ; CNT ; 6 ; Signed Integer ; ; DATA_WIDTH ; 8 ; Signed Integer ; +----------------+-------+------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[0]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[1]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[2]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[3]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[4]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_tx:u_tx[5]|sync_fifo:tx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[0]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[1]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[2]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[3]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[4]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5] ; +----------------+-------+-----------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------+ ; DATA_WIDTH ; 8 ; Signed Integer ; ; FIFO_DEPTH ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +------------------------------------------------------------------------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: multi_uart_ip:macro_inst|multi_uart:u_uart[1]|uart_rx:u_rx[5]|sync_fifo:rx_fifo ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ ; WIDTH ; 8 ; Signed Integer ; ; DEPTH ; 1 ; Signed Integer ; ; SHOWAEAD ; 1 ; Signed Integer ; +----------------+-------+-----------------------------------------------------------------------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +---------------------------------------------------------------------------------------------------------------------------------------------------+ ; Partition Dependent Files ; +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+ ; File ; Location ; Library ; Checksum ; +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+ ; libraries/megafunctions/aglobal130.inc ; Quartus II Install ; work ; 6fc5170a475a9c6f00c3fd7627b30d31 ; ; libraries/megafunctions/altpll.tdf ; Quartus II Install ; work ; 2fbd40fef3231c521503c3b7162ebe3e ; ; libraries/megafunctions/cycloneii_pll.inc ; Quartus II Install ; work ; c2ee779f089b03bc181df753ea85b3ef ; ; libraries/megafunctions/stratix_pll.inc ; Quartus II Install ; work ; a9a94c5b0e18105f7ae8c218a67ec9f7 ; ; libraries/megafunctions/stratixii_pll.inc ; Quartus II Install ; work ; 6797ab505ed700f1a221e4a213e106a6 ; ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work ; 08f2cc6cdebd91dbc2e05d999cace46c ; ; ahb2apb.v ; Project Directory ; work ; c0ffc445ab6981ccc770b94b804da175 ; ; apb_mux.v ; Project Directory ; work ; 116a3aadafa91dc333e285e787adcfbd ; ; db/altpll_9g32.tdf ; Project Directory ; work ; 6571784d6e255593b8053aed7770dc66 ; ; multi_uart_ip.v ; Project Directory ; work ; f903c122b611903a57ce62ebf868c67c ; ; multi_uart_ip/baud_gen.v ; Project Directory ; work ; 9cc17364fcb27f4ebdc9b9f7e74df21b ; ; multi_uart_ip/multi_uart.v ; Project Directory ; work ; 0e8563a5553efcaa477674a21da00cb7 ; ; multi_uart_ip/sync_fifo.v ; Project Directory ; work ; 2c5edbc41601ae09647b7a780aa8bdf1 ; ; multi_uart_ip/uart_regs.v ; Project Directory ; work ; d2486baae9a756bd165a62753eff3d6a ; ; multi_uart_ip/uart_rx.v ; Project Directory ; work ; a94e4e50768cb2f98b014a60af8722f4 ; ; multi_uart_ip/uart_tx.v ; Project Directory ; work ; 26da0d543584fcfa1fbc29e7c62d286c ; ; test_uart.v ; Project Directory ; work ; 6e45d9343f699dc713c0cc45ba601a9c ; +---------------------------------------------------------------------------------+--------------------+---------+----------------------------------+ +-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Partition "rv32" Resource Utilization by Entity ; +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ; +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ ; |test_uart ; 1 (0) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart ; work ; ; |alta_rv32:rv32| ; 1 (1) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |test_uart|alta_rv32:rv32 ; work ; +----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------------+--------------+ Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy. +-------------------------------------------------------------+ ; Parameter Settings for User Entity Instance: alta_rv32:rv32 ; +----------------+-------+------------------------------------+ ; Parameter Name ; Value ; Type ; +----------------+-------+------------------------------------+ ; coord_x ; 0 ; Signed Integer ; ; coord_y ; 0 ; Signed Integer ; ; coord_z ; 0 ; Signed Integer ; +----------------+-------+------------------------------------+ Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off". +-----------------------------------------------------------------------------------------------------------------------------------------+ ; Partition Dependent Files ; +---------------------------------------------------------------------------------+----------+---------+----------------------------------+ ; File ; Location ; Library ; Checksum ; +---------------------------------------------------------------------------------+----------+---------+----------------------------------+ ; C:/Users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v ; Absolute ; work ; 08f2cc6cdebd91dbc2e05d999cace46c ; +---------------------------------------------------------------------------------+----------+---------+----------------------------------+ +--------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "alta_rv32:rv32" ; +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+ ; ext_resetn ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ; ; test_mode ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ; ; usb0_xcvr_clk ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ; ; usb0_id ; Partition Input ; Warning ; Stuck at VCC. Constants will not propagate across partition boundaries ; ; sys_ctrl_hseEnable ; Partition Output ; Info ; Explicitly unconnected ; ; sys_ctrl_hseBypass ; Partition Output ; Info ; Explicitly unconnected ; ; sys_ctrl_sleep ; Partition Output ; Info ; Explicitly unconnected ; ; sys_ctrl_standby ; Partition Output ; Info ; Explicitly unconnected ; ; dmactive ; Partition Output ; Info ; Explicitly unconnected ; ; swj_JTAGNSW ; Partition Output ; Info ; Explicitly unconnected ; ; swj_JTAGSTATE ; Partition Output ; Info ; Explicitly unconnected ; ; swj_JTAGIR ; Partition Output ; Info ; Explicitly unconnected ; ; ext_int ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ; ; gpio0_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ; ; gpio0_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio0_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio1_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ; ; gpio2_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ; ; gpio3_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio3_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio4_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio4_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio5_io_out_data ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio5_io_out_en ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_data[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_data[5] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_data[3] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_data[1] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_en[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_en[5] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_en[3] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio6_io_out_en[1] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio7_io_out_data[5..0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio7_io_out_data[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio7_io_out_en[5..0] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio7_io_out_en[7] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio8_io_in ; Partition Input ; Warning ; Stuck at GND. Constants will not propagate across partition boundaries ; ; gpio8_io_out_data[5] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; ; gpio8_io_out_en[5] ; Partition Output ; Warning ; Connected to dangling logic. Logic connected to a dangling partition output or bidir will not be optimized away. ; +-------------------------+------------------+----------+------------------------------------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[1]" ; +------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------+--------+----------+-------------------------------------------------------------------------------------+ ; tx_dma_clr ; Input ; Info ; Stuck at GND ; ; tx_dma_req ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; rx_dma_clr ; Input ; Info ; Stuck at GND ; ; rx_dma_req ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------------+--------+----------+-------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "multi_uart_ip:macro_inst|multi_uart:u_uart[0]" ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ ; tx_dma_clr[5..2] ; Input ; Info ; Stuck at GND ; ; tx_dma_req[5..2] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; rx_dma_clr[5..2] ; Input ; Info ; Stuck at GND ; ; rx_dma_req[5..2] ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +------------------+--------+----------+-------------------------------------------------------------------------------------+ +------------------------------------------------------------------------+ ; Port Connectivity Checks: "multi_uart_ip:macro_inst|apb_mux:u_apb_mux" ; +-----------------+-------+----------+-----------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+-------+----------+-----------------------------------+ ; apb_out_pslverr ; Input ; Info ; Stuck at GND ; +-----------------+-------+----------+-----------------------------------+ +---------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb" ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ ; ahb_hmastlock ; Input ; Info ; Stuck at GND ; ; ahb_hsel ; Input ; Info ; Stuck at VCC ; ; ahb_hprot[1..0] ; Input ; Info ; Stuck at VCC ; ; ahb_hprot[3..2] ; Input ; Info ; Stuck at GND ; ; apb_pstrb ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; ; apb_pprot ; Output ; Info ; Connected to dangling logic. Logic that only feeds a dangling port will be removed. ; +-----------------+--------+----------+-------------------------------------------------------------------------------------+ +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Port Connectivity Checks: "multi_uart_ip:macro_inst" ; +---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ ; Port ; Type ; Severity ; Details ; +---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ ; ext_int_in ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; rxd_14_ip_in ; Output ; Warning ; Declared by entity but not connected by instance. Logic that only feeds a dangling port will be removed. ; ; txd_14_ip_out_data ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; txd_14_ip_out_en ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; txen_14_ip_out_data ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; ; txen_14_ip_out_en ; Input ; Warning ; Declared by entity but not connected by instance. If a default value exists, it will be used. Otherwise, the port will be connected to GND. ; +---------------------+--------+----------+----------------------------------------------------------------------------------------------------------------------------------------------+ +-----------------------------------------------------+ ; Port Connectivity Checks: "alta_gclksw:gclksw_inst" ; +--------+-------+----------+-------------------------+ ; Port ; Type ; Severity ; Details ; +--------+-------+----------+-------------------------+ ; ena ; Input ; Info ; Stuck at VCC ; ; clkin3 ; Input ; Info ; Explicitly unconnected ; +--------+-------+----------+-------------------------+ +-------------------------------+ ; Elapsed Time Per Partition ; +----------------+--------------+ ; Partition Name ; Elapsed Time ; +----------------+--------------+ ; Top ; 00:00:07 ; ; rv32 ; 00:00:07 ; +----------------+--------------+ +-------------------------------+ ; Analysis & Synthesis Messages ; +-------------------------------+ Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version Info: Processing started: Tue Jul 15 16:26:04 2025 Info: Command: quartus_map --read_settings_files=on --write_settings_files=off test_uart -c test_uart Info (11104): Parallel Compilation has detected 8 hyper-threaded processors. However, the extra hyper-threaded processors will not be used by default. Parallel Compilation will use 4 of the 4 physical processors detected instead. Info (12021): Found 1 design units, including 1 entities, in source file test_uart.v Info (12023): Found entity 1: test_uart Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip.v Info (12023): Found entity 1: multi_uart_ip Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/baud_gen.v Info (12023): Found entity 1: baud_gen Warning (10275): Verilog HDL Module Instantiation warning at multi_uart.v(90): ignored dangling comma in List of Port Connections Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/multi_uart.v Info (12023): Found entity 1: multi_uart Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/sync_fifo.v Info (12023): Found entity 1: sync_fifo Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/uart_regs.v Info (12023): Found entity 1: uart_regs Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/uart_rx.v Info (12023): Found entity 1: uart_rx Info (12021): Found 1 design units, including 1 entities, in source file multi_uart_ip/uart_tx.v Info (12023): Found entity 1: uart_tx Info (12021): Found 57 design units, including 57 entities, in source file c:/users/zzz17/.platformio/packages/tool-agrv_logic/etc/arch/rodinia/alta_sim.v Info (12023): Found entity 1: alta_slice Info (12023): Found entity 2: alta_clkenctrl_rst Info (12023): Found entity 3: alta_clkenctrl Info (12023): Found entity 4: alta_asyncctrl Info (12023): Found entity 5: alta_syncctrl Info (12023): Found entity 6: alta_io_gclk Info (12023): Found entity 7: alta_gclksel Info (12023): Found entity 8: alta_gclkgen Info (12023): Found entity 9: alta_gclkgen0 Info (12023): Found entity 10: alta_gclkgen2 Info (12023): Found entity 11: alta_io Info (12023): Found entity 12: alta_rio Info (12023): Found entity 13: alta_srff Info (12023): Found entity 14: alta_dff Info (12023): Found entity 15: alta_ufm_gddd Info (12023): Found entity 16: alta_dff_stall Info (12023): Found entity 17: alta_srlat Info (12023): Found entity 18: alta_dio Info (12023): Found entity 19: alta_indel Info (12023): Found entity 20: alta_dpclkdel Info (12023): Found entity 21: alta_ufms Info (12023): Found entity 22: alta_ufms_sim Info (12023): Found entity 23: alta_pll Info (12023): Found entity 24: alta_pllx Info (12023): Found entity 25: pll_clk_trim Info (12023): Found entity 26: alta_pllv Info (12023): Found entity 27: alta_pllve Info (12023): Found entity 28: alta_sram Info (12023): Found entity 29: alta_dpram16x4 Info (12023): Found entity 30: alta_spram16x4 Info (12023): Found entity 31: alta_wram Info (12023): Found entity 32: alta_bram_pulse_generator Info (12023): Found entity 33: alta_bram Info (12023): Found entity 34: alta_boot Info (12023): Found entity 35: alta_osc Info (12023): Found entity 36: alta_ufml Info (12023): Found entity 37: alta_jtag Info (12023): Found entity 38: alta_mult Info (12023): Found entity 39: alta_dff_en Info (12023): Found entity 40: alta_multm_add Info (12023): Found entity 41: alta_multm Info (12023): Found entity 42: alta_i2c Info (12023): Found entity 43: alta_spi Info (12023): Found entity 44: alta_irda Info (12023): Found entity 45: alta_bram9k Info (12023): Found entity 46: alta_mcu Info (12023): Found entity 47: alta_mcu_m3 Info (12023): Found entity 48: alta_remote Info (12023): Found entity 49: alta_saradc Info (12023): Found entity 50: alta_gclksw Info (12023): Found entity 51: alta_rv32 Info (12023): Found entity 52: alta_mipi_clk Info (12023): Found entity 53: alta_adc Info (12023): Found entity 54: alta_dac Info (12023): Found entity 55: alta_cmp Info (12023): Found entity 56: alta_ram4k Info (12023): Found entity 57: alta_ram9k Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(143): created implicit net for "PIN_32_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(146): created implicit net for "PIN_33_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(154): created implicit net for "PIN_35_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(162): created implicit net for "PIN_38_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(180): created implicit net for "PIN_48_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(201): created implicit net for "PIN_66_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(259): created implicit net for "PIN_95_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(267): created implicit net for "PIN_97_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(270): created implicit net for "PIN_98_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(276): created implicit net for "PIN_HSE_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(279): created implicit net for "PIN_HSI_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(282): created implicit net for "PIN_OSC_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(405): created implicit net for "usb0_xcvr_clk" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(424): created implicit net for "bus_clk" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(437): created implicit net for "sys_clk" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__5__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__4__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__3__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__2__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__1__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(492): created implicit net for "gpio_int_g0_in__0__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__5__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__4__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__3__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__2__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__1__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(493): created implicit net for "gpio_int_g1_in__0__" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(494): created implicit net for "rxd_12_ip_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(495): created implicit net for "rxd_13_ip_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(496): created implicit net for "rxd_15_ip_in" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(497): created implicit net for "txd_12_ip_out_data" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(498): created implicit net for "txd_12_ip_out_en" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(499): created implicit net for "txd_13_ip_out_data" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(500): created implicit net for "txd_13_ip_out_en" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(501): created implicit net for "txd_15_ip_out_data" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(502): created implicit net for "txd_15_ip_out_en" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(503): created implicit net for "txen_12_ip_out_data" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(504): created implicit net for "txen_12_ip_out_en" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(505): created implicit net for "txen_13_ip_out_data" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(506): created implicit net for "txen_13_ip_out_en" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(507): created implicit net for "txen_15_ip_out_data" Warning (10236): Verilog HDL Implicit Net warning at test_uart.v(508): created implicit net for "txen_15_ip_out_en" Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(51): created implicit net for "baud16" Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(83): created implicit net for "lcr_sps" Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(84): created implicit net for "lcr_stp2" Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(85): created implicit net for "lcr_eps" Warning (10236): Verilog HDL Implicit Net warning at multi_uart.v(86): created implicit net for "lcr_pen" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(180): created implicit net for "ena_reg" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(204): created implicit net for "ena_int" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(205): created implicit net for "ena_reg" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(476): created implicit net for "outreg_h" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(477): created implicit net for "outreg_l" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(485): created implicit net for "oe_reg_h" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(486): created implicit net for "oe_reg_l" Warning (10236): Verilog HDL Implicit Net warning at alta_sim.v(2758): created implicit net for "dffOut" Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(105): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(106): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(126): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(127): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(128): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(38): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(39): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(40): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(41): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(42): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(43): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(44): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(45): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(46): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(47): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_regs.v(49): Parameter Declaration in module "uart_regs" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(21): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(22): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(23): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(24): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_tx.v(25): Parameter Declaration in module "uart_tx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at sync_fifo.v(12): Parameter Declaration in module "sync_fifo" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at sync_fifo.v(13): Parameter Declaration in module "sync_fifo" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at sync_fifo.v(18): Parameter Declaration in module "sync_fifo" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(24): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(25): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(26): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(27): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(28): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(30): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at uart_rx.v(31): Parameter Declaration in module "uart_rx" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(228): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(229): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at multi_uart_ip.v(230): Parameter Declaration in module "multi_uart_ip" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Warning (10222): Verilog HDL Parameter Declaration warning at alta_sim.v(2428): Parameter Declaration in module "alta_bram_pulse_generator" behaves as a Local Parameter Declaration because the module has a Module Parameter Port List Info (12127): Elaborating entity "test_uart" for the top level hierarchy Warning (10036): Verilog HDL or VHDL warning at test_uart.v(282): object "PIN_OSC_in" assigned a value but never read Info (12128): Elaborating entity "altpll" for hierarchy "altpll:pll_inst" Info (12130): Elaborated megafunction instantiation "altpll:pll_inst" Info (12133): Instantiated megafunction "altpll:pll_inst" with the following parameter: Info (12134): Parameter "bandwidth_type" = "AUTO" Info (12134): Parameter "clk0_divide_by" = "4" Info (12134): Parameter "clk0_multiply_by" = "120" Info (12134): Parameter "clk0_phase_shift" = "0" Info (12134): Parameter "clk1_divide_by" = "4" Info (12134): Parameter "clk1_multiply_by" = "120" Info (12134): Parameter "clk1_phase_shift" = "0" Info (12134): Parameter "clk2_divide_by" = "4" Info (12134): Parameter "clk2_multiply_by" = "120" Info (12134): Parameter "clk2_phase_shift" = "0" Info (12134): Parameter "clk3_divide_by" = "8" Info (12134): Parameter "clk3_multiply_by" = "120" Info (12134): Parameter "clk3_phase_shift" = "0" Info (12134): Parameter "clk4_divide_by" = "4" Info (12134): Parameter "clk4_multiply_by" = "120" Info (12134): Parameter "clk4_phase_shift" = "0" Info (12134): Parameter "compensate_clock" = "CLK0" Info (12134): Parameter "inclk0_input_frequency" = "125000" Info (12134): Parameter "lpm_type" = "altpll" Info (12134): Parameter "operation_mode" = "NORMAL" Info (12134): Parameter "pll_type" = "AUTO" Info (12134): Parameter "intended_device_family" = "Cyclone IV E" Info (12134): Parameter "port_areset" = "PORT_USED" Info (12134): Parameter "port_inclk0" = "PORT_USED" Info (12134): Parameter "port_locked" = "PORT_USED" Info (12134): Parameter "port_clk0" = "PORT_USED" Info (12134): Parameter "port_clk1" = "PORT_UNUSED" Info (12134): Parameter "port_clk2" = "PORT_UNUSED" Info (12134): Parameter "port_clk3" = "PORT_USED" Info (12134): Parameter "port_clk4" = "PORT_UNUSED" Info (12134): Parameter "width_clock" = "5" Info (12134): Parameter "width_phasecounterselect" = "3" Info (12021): Found 1 design units, including 1 entities, in source file db/altpll_9g32.tdf Info (12023): Found entity 1: altpll_9g32 Info (12128): Elaborating entity "altpll_9g32" for hierarchy "altpll:pll_inst|altpll_9g32:auto_generated" Info (12128): Elaborating entity "alta_gclksw" for hierarchy "alta_gclksw:gclksw_inst" Info (12128): Elaborating entity "multi_uart_ip" for hierarchy "multi_uart_ip:macro_inst" Warning (10230): Verilog HDL assignment warning at multi_uart_ip.v(238): truncated value with size 8 to match size of target (1) Warning (10030): Net "tx_dma_clr[11..2]" at multi_uart_ip.v(108) has no driver or initial value, using a default initial value '0' Warning (10030): Net "rx_dma_clr[11..2]" at multi_uart_ip.v(110) has no driver or initial value, using a default initial value '0' Warning (12125): Using design file ahb2apb.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info (12023): Found entity 1: ahb2apb Info (12128): Elaborating entity "ahb2apb" for hierarchy "multi_uart_ip:macro_inst|ahb2apb:u_ahb2apb" Warning (10764): Verilog HDL warning at ahb2apb.v(52): converting signed shift amount to unsigned Warning (10230): Verilog HDL assignment warning at ahb2apb.v(52): truncated value with size 32 to match size of target (4) Warning (12125): Using design file apb_mux.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project Info (12023): Found entity 1: apb_mux Info (12128): Elaborating entity "apb_mux" for hierarchy "multi_uart_ip:macro_inst|apb_mux:u_apb_mux" Info (12128): Elaborating entity "multi_uart" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]" Info (12128): Elaborating entity "baud_gen" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|baud_gen:u_baud" Warning (10230): Verilog HDL assignment warning at baud_gen.v(21): truncated value with size 32 to match size of target (16) Warning (10230): Verilog HDL assignment warning at baud_gen.v(31): truncated value with size 32 to match size of target (6) Info (12128): Elaborating entity "uart_regs" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_regs:u_regs" Warning (10230): Verilog HDL assignment warning at uart_regs.v(87): truncated value with size 16 to match size of target (6) Warning (10230): Verilog HDL assignment warning at uart_regs.v(208): truncated value with size 32 to match size of target (6) Info (12128): Elaborating entity "uart_tx" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]" Warning (10230): Verilog HDL assignment warning at uart_tx.v(90): truncated value with size 32 to match size of target (3) Warning (10230): Verilog HDL assignment warning at uart_tx.v(92): truncated value with size 32 to match size of target (3) Warning (10230): Verilog HDL assignment warning at uart_tx.v(100): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at uart_tx.v(110): truncated value with size 32 to match size of target (4) Info (12128): Elaborating entity "sync_fifo" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_tx:u_tx[0]|sync_fifo:tx_fifo" Warning (10230): Verilog HDL assignment warning at sync_fifo.v(36): truncated value with size 32 to match size of target (1) Warning (10230): Verilog HDL assignment warning at sync_fifo.v(38): truncated value with size 32 to match size of target (1) Info (12128): Elaborating entity "uart_rx" for hierarchy "multi_uart_ip:macro_inst|multi_uart:u_uart[0]|uart_rx:u_rx[0]" Warning (10230): Verilog HDL assignment warning at uart_rx.v(88): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at uart_rx.v(91): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at uart_rx.v(93): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at uart_rx.v(118): truncated value with size 32 to match size of target (4) Warning (10230): Verilog HDL assignment warning at uart_rx.v(120): truncated value with size 32 to match size of target (4) Info (12128): Elaborating entity "alta_rv32" for hierarchy "alta_rv32:rv32" Warning (10034): Output port "gpio0_io_out_data" at alta_sim.v(3739) has no driver Warning (10034): Output port "gpio0_io_out_en" at alta_sim.v(3740) has no driver Warning (10034): Output port "gpio1_io_out_data" at alta_sim.v(3742) has no driver Warning (10034): Output port "gpio1_io_out_en" at alta_sim.v(3743) has no driver Warning (10034): Output port "gpio2_io_out_data" at alta_sim.v(3753) has no driver Warning (10034): Output port "gpio2_io_out_en" at alta_sim.v(3754) has no driver Warning (10034): Output port "gpio3_io_out_data" at alta_sim.v(3756) has no driver Warning (10034): Output port "gpio3_io_out_en" at alta_sim.v(3757) has no driver Warning (10034): Output port "gpio4_io_out_data" at alta_sim.v(3759) has no driver Warning (10034): Output port "gpio4_io_out_en" at alta_sim.v(3760) has no driver Warning (10034): Output port "gpio5_io_out_data" at alta_sim.v(3762) has no driver Warning (10034): Output port "gpio5_io_out_en" at alta_sim.v(3763) has no driver Warning (10034): Output port "gpio6_io_out_data" at alta_sim.v(3765) has no driver Warning (10034): Output port "gpio6_io_out_en" at alta_sim.v(3766) has no driver Warning (10034): Output port "gpio7_io_out_data" at alta_sim.v(3768) has no driver Warning (10034): Output port "gpio7_io_out_en" at alta_sim.v(3769) has no driver Warning (10034): Output port "gpio8_io_out_data" at alta_sim.v(3771) has no driver Warning (10034): Output port "gpio8_io_out_en" at alta_sim.v(3772) has no driver Warning (10034): Output port "gpio9_io_out_data" at alta_sim.v(3774) has no driver Warning (10034): Output port "gpio9_io_out_en" at alta_sim.v(3775) has no driver Warning (10034): Output port "swj_JTAGSTATE" at alta_sim.v(3780) has no driver Warning (10034): Output port "swj_JTAGIR" at alta_sim.v(3781) has no driver Warning (10034): Output port "dmactive" at alta_sim.v(3778) has no driver Warning (10034): Output port "swj_JTAGNSW" at alta_sim.v(3779) has no driver Info (12206): 2 design partitions require synthesis Info (12210): Partition "rv32" requires synthesis because its netlist type is Source File Info (12210): Partition "Top" requires synthesis because its netlist type is Source File Info (12209): No design partitions will skip synthesis in the current incremental compilation Warning (12241): 2 hierarchies have connectivity warnings - see the Connectivity Checks report folder Info (281037): Using 4 processors to synthesize 2 partitions in parallel Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version Info: Processing started: Tue Jul 15 16:26:06 2025 Info: Command: quartus_map --parallel=1 --helper=0 --partition=Top test_uart -c test_uart Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13049): Converted tri-state buffer "multi_uart_ip:macro_inst|rxd_15_ip_in" feeding internal logic into a wire Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition Top Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the Top Info (281020): Starting Logic Optimization and Technology Mapping for Top Partition Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13046): Tri-state node(s) do not directly drive top-level pin(s) Warning (13047): Converted the fan-out from the tri-state buffer "multi_uart_ip:macro_inst|rxd_12_ip_in" to the node "gpio6_io_in[3]" into an OR gate Warning (13047): Converted the fan-out from the tri-state buffer "multi_uart_ip:macro_inst|rxd_13_ip_in" to the node "gpio6_io_in[5]" into an OR gate Info (13000): Registers with preset signals will power-up high Info (13003): DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back Info (286031): Timing-Driven Synthesis is running on partition "Top" Info (17049): 48 registers lost all their fanouts during netlist optimizations. Info (17016): Found the following redundant logic cells in design Info (17048): Logic cell "gpio3_io_in[0]" Info (17048): Logic cell "gpio3_io_in[1]" Info (17048): Logic cell "gpio3_io_in[2]" Info (17048): Logic cell "gpio3_io_in[3]" Info (17048): Logic cell "gpio3_io_in[4]" Info (17048): Logic cell "gpio4_io_in[0]" Info (17048): Logic cell "gpio4_io_in[1]" Info (17048): Logic cell "gpio4_io_in[2]" Info (17048): Logic cell "gpio4_io_in[3]" Info (17048): Logic cell "gpio4_io_in[4]" Info (17048): Logic cell "gpio4_io_in[5]" Info (17048): Logic cell "gpio5_io_in[0]" Info (17048): Logic cell "gpio5_io_in[1]" Info (17048): Logic cell "gpio5_io_in[2]" Info (17048): Logic cell "gpio5_io_in[3]" Info (17048): Logic cell "gpio5_io_in[4]" Info (17048): Logic cell "gpio5_io_in[5]" Info (17048): Logic cell "gpio6_io_in[6]" Info (17048): Logic cell "gpio6_io_in[7]" Info (17048): Logic cell "gpio7_io_in[1]" Info (17048): Logic cell "gpio9_io_in[1]" Info (17048): Logic cell "gpio1_io_out_data[0]" Info (17048): Logic cell "gpio1_io_out_en[0]" Info (17048): Logic cell "gpio1_io_out_data[1]" Info (17048): Logic cell "gpio1_io_out_en[1]" Info (17048): Logic cell "gpio1_io_out_data[2]" Info (17048): Logic cell "gpio1_io_out_en[2]" Info (17048): Logic cell "gpio1_io_out_data[3]" Info (17048): Logic cell "gpio1_io_out_en[3]" Info (17048): Logic cell "gpio1_io_out_data[4]" Info (17048): Logic cell "gpio1_io_out_en[4]" Info (17048): Logic cell "gpio1_io_out_data[5]" Info (17048): Logic cell "gpio1_io_out_en[5]" Info (17048): Logic cell "gpio1_io_out_data[6]" Info (17048): Logic cell "gpio1_io_out_en[6]" Info (17048): Logic cell "gpio1_io_out_data[7]" Info (17048): Logic cell "gpio1_io_out_en[7]" Info (17048): Logic cell "gpio2_io_out_data[0]" Info (17048): Logic cell "gpio2_io_out_en[0]" Info (17048): Logic cell "gpio2_io_out_data[1]" Info (17048): Logic cell "gpio2_io_out_en[1]" Info (17048): Logic cell "gpio2_io_out_data[2]" Info (17048): Logic cell "gpio2_io_out_en[2]" Info (17048): Logic cell "gpio2_io_out_data[3]" Info (17048): Logic cell "gpio2_io_out_en[3]" Info (17048): Logic cell "gpio2_io_out_data[4]" Info (17048): Logic cell "gpio2_io_out_en[4]" Info (17048): Logic cell "gpio2_io_out_data[5]" Info (17048): Logic cell "gpio2_io_out_en[5]" Info (17048): Logic cell "gpio2_io_out_data[6]" Info (17048): Logic cell "gpio2_io_out_en[6]" Info (17048): Logic cell "gpio2_io_out_data[7]" Info (17048): Logic cell "gpio2_io_out_en[7]" Info (17048): Logic cell "gpio6_io_out_data[0]" Info (17048): Logic cell "gpio6_io_out_en[0]" Info (17048): Logic cell "gpio6_io_out_data[2]" Info (17048): Logic cell "gpio6_io_out_en[2]" Info (17048): Logic cell "gpio6_io_out_data[4]" Info (17048): Logic cell "gpio6_io_out_en[4]" Info (17048): Logic cell "gpio9_io_out_data[0]" Info (17048): Logic cell "gpio9_io_out_en[0]" Info (17048): Logic cell "gpio9_io_out_data[2]" Info (17048): Logic cell "gpio9_io_out_en[2]" Info (17048): Logic cell "gpio9_io_out_data[3]" Info (17048): Logic cell "gpio9_io_out_en[3]" Info (17048): Logic cell "gpio9_io_out_data[4]" Info (17048): Logic cell "gpio9_io_out_en[4]" Info (17048): Logic cell "gpio9_io_out_data[5]" Info (17048): Logic cell "gpio9_io_out_en[5]" Info (17048): Logic cell "gpio9_io_out_data[6]" Info (17048): Logic cell "gpio9_io_out_en[6]" Info (17048): Logic cell "gpio9_io_out_data[7]" Info (17048): Logic cell "gpio9_io_out_en[7]" Info (17048): Logic cell "sys_resetn" Info (17048): Logic cell "gpio8_io_out_data[4]" Info (17048): Logic cell "gpio8_io_out_en[4]" Info (17048): Logic cell "gpio8_io_out_data[6]" Info (17048): Logic cell "gpio8_io_out_en[6]" Info (17048): Logic cell "gpio7_io_out_data[6]" Info (17048): Logic cell "gpio8_io_out_en[7]" Info (17048): Logic cell "gpio8_io_out_data[1]" Info (17048): Logic cell "gpio8_io_out_en[1]" Info (17048): Logic cell "gpio8_io_out_data[3]" Info (17048): Logic cell "gpio8_io_out_en[3]" Info (17048): Logic cell "sys_ctrl_clkSource[0]" Info (17048): Logic cell "sys_ctrl_clkSource[1]" Info (17048): Logic cell "gpio6_io_out_data[6]" Info (17048): Logic cell "gpio6_io_out_en[6]" Info (17048): Logic cell "gpio9_io_out_data[1]" Info (17048): Logic cell "gpio9_io_out_en[1]" Info (17048): Logic cell "gpio8_io_out_data[0]" Info (17048): Logic cell "gpio8_io_out_en[0]" Info (17048): Logic cell "gpio8_io_out_data[2]" Info (17048): Logic cell "gpio8_io_out_en[2]" Info (17048): Logic cell "gpio7_io_out_en[6]" Info (17048): Logic cell "gpio8_io_out_data[7]" Info (17048): Logic cell "PLL_ENABLE" Warning (15899): PLL "altpll:pll_inst|altpll_9g32:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected Info (128000): Starting physical synthesis optimizations for speed Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 4 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 125.000 PIN_HSE Info (332111): 100.000 PIN_HSI Info (332111): 4.166 pll_inst|auto_generated|pll1|clk[0] Info (332111): 8.333 pll_inst|auto_generated|pll1|clk[3] Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 Info (21057): Implemented 2476 device resources after synthesis - the final resource count might be different Info (21058): Implemented 11 input pins Info (21059): Implemented 30 output pins Info (21060): Implemented 17 bidirectional pins Info (21061): Implemented 2414 logic cells Info (21065): Implemented 1 PLLs Info (21071): Implemented 1 partitions Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 6 warnings Info: Peak virtual memory: 4692 megabytes Info: Processing ended: Tue Jul 15 16:26:13 2025 Info: Elapsed time: 00:00:07 Info: Total CPU time (on all processors): 00:00:09 Info: ******************************************************************* Info: Running Quartus II 64-Bit Analysis & Synthesis Info: Version 13.0.0 Build 156 04/24/2013 SJ Full Version Info: Processing started: Tue Jul 15 16:26:06 2025 Info: Command: quartus_map --parallel=1 --helper=1 --partition=rv32 test_uart -c test_uart Info (270000): Limiting DSP block usage to 0 DSP block(s) for the partition alta_rv32:rv32 Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32 Info (270017): Limiting M4K/M9K RAM block usage to 4 M4K/M9K RAM block(s) for the alta_rv32:rv32 Info (281019): Starting Logic Optimization and Technology Mapping for Partition rv32 Info (17026): Resynthesizing 0 WYSIWYG logic cells and I/Os using "balanced" technology mapper which leaves 0 WYSIWYG logic cells and I/Os untouched Warning (13024): Output pins are stuck at VCC or GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio0_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio1_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio2_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio3_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio4_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio5_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio6_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio7_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio8_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_data[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[4]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[5]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[6]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|gpio9_io_out_en[7]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|dmactive" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGNSW" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGSTATE[3]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[0]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[1]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[2]" is stuck at GND Warning (13410): Pin "alta_rv32:rv32|swj_JTAGIR[3]" is stuck at GND Info (128000): Starting physical synthesis optimizations for speed Info (332129): Detected timing requirements -- optimizing circuit to achieve only the specified requirements Info (332111): Found 4 clocks Info (332111): Period Clock Name Info (332111): ======== ============ Info (332111): 125.000 PIN_HSE Info (332111): 100.000 PIN_HSI Info (332111): 4.166 pll_inst|auto_generated|pll1|clk[0] Info (332111): 8.333 pll_inst|auto_generated|pll1|clk[3] Info (128002): Starting physical synthesis algorithm combinational resynthesis using boolean division Info (128003): Physical synthesis algorithm combinational resynthesis using boolean division complete: estimated slack improvement of 0 ps Info (128001): Physical synthesis optimizations for speed complete: elapsed time is 00:00:01 Info (21057): Implemented 520 device resources after synthesis - the final resource count might be different Info (21058): Implemented 224 input pins Info (21059): Implemented 295 output pins Info (21061): Implemented 1 logic cells Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 171 warnings Info: Peak virtual memory: 4676 megabytes Info: Processing ended: Tue Jul 15 16:26:08 2025 Info: Elapsed time: 00:00:02 Info: Total CPU time (on all processors): 00:00:03 Info (281038): Finished parallel synthesis of all partitions Info (144001): Generated suppressed messages file D:/LYW/NEW_DECODE/2006_APP_s2/logic/quartus_logs/test_uart.map.smsg Info: Quartus II 64-Bit Analysis & Synthesis was successful. 0 errors, 316 warnings Info: Peak virtual memory: 4628 megabytes Info: Processing ended: Tue Jul 15 16:26:14 2025 Info: Elapsed time: 00:00:10 Info: Total CPU time (on all processors): 00:00:11 +------------------------------------------+ ; Analysis & Synthesis Suppressed Messages ; +------------------------------------------+ The suppressed messages can be found in D:/LYW/NEW_DECODE/2006_APP_s2/logic/quartus_logs/test_uart.map.smsg.