> alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n"
Cmd : C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/bin/af.exe 2025.06.b0(3f05be1c)
> alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n"
Args : -X "set QUARTUS_SDC true" -X "set FITTING Auto" -X "set FITTER full" -X "set EFFORT high" -X "set HOLDX default" -X "set SKEW   basic" -X "set MODE QUARTUS" -X "set FLOW ALL" -F ./af_run.tcl
> 
> set_seed_rand $SEED
> set ar_timing_derate ${TIMING_DERATE}
> 
> date_time
Tue Jul 15 16:27:27 2025
> if { [file exists [file join . ${DESIGN}.pre.asf]] } {
  alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n"
  source [file join . ${DESIGN}.pre.asf]
}
Using pre-ASF file test_uart.pre.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> set BOARD_PLL_CLKIN PIN_HSE
> set db_io_name_priority False
> set ip_pll_vco_lowpower true
> set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION "OFF"
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
> 
> set LOAD_DB    false
> set LOAD_PLACE false
> set LOAD_ROUTE false
> set LOAD_PACK false
> if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } {
  set LOAD_DB    true
  set LOAD_PLACE true
  set LOAD_ROUTE true
} elseif { $FLOW == "R" || $FLOW == "ROUTE" } {
  set LOAD_DB    true
  set LOAD_PLACE true
} elseif { $FLOW == "PR" || $FLOW == "PLACE_AND_ROUTE" } {
  set LOAD_DB    false
  set LOAD_PACK  true
}
> 
> set ORIGINAL_QSF "./test_uart.qsf"
> set ORIGINAL_PIN ""
> 
> #################################################################################
> 
> # The default SDC file is ${DESIGN}.sdc 
> set sdc_file $SDC_FILE
> if { $sdc_file == "" } {
  set sdc_file [file join . ${DESIGN}.adc]
  if { ! [file exists $sdc_file] } { set sdc_file [file join . ${DESIGN}.sdc]; }
}
> # No default VE file is not specified
> set ve_file $VEX_FILE
> 
> while (1) {

if { $FLOW == "SKIP" } { break }

if { [info exists CORNER] } { set_mode -corner $CORNER; }

eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
foreach ip_file $IP_FILES { read_ip $ip_file; }


if { $FLOW == "GEN" } {
  if { ! [info exists CONFIG_BITS] } {
    set CONFIG_BITS [file join ${RESULT_DIR} ${DESIGN}.bin]
  }
  if { [llength $CONFIG_BITS] > 1 } {
    if { ! [info exists BOOT_BINARY] } {
      set BOOT_BINARY [file join ${RESULT_DIR} ${DESIGN}_boot.bin]
    }
    if { ! [info exists CONFIG_ADDRESSES] } {
      set CONFIG_ADDRESSES ""
    }
    generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES
  } else {
    set CONFIG_ROOT   [file rootname [lindex $CONFIG_BITS 0]]
    set SLAVE_RBF     "${CONFIG_ROOT}_slave.rbf"
    set MASTER_BINARY "${CONFIG_ROOT}_master.bin"
    if { [file exists [lindex $CONFIG_BITS 0]] } {
      generate_binary -slave  $SLAVE_RBF     -inputs [lindex $CONFIG_BITS 0] -reverse
      generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0]
    }
    if { ! [info exists BOOT_BINARY] } {
      set BOOT_BINARY $MASTER_BINARY
    }
  }
  set PRG_FILE [file rootname $BOOT_BINARY].prg
  set AS_FILE  [file rootname $BOOT_BINARY]_as.prg
  generate_programming_file $BOOT_BINARY -erase $ERASE \
                            -program $PROGRAM -verify $VERIFY -offset $OFFSET \
                            -prg $PRG_FILE -as $AS_FILE
  break
}

if { $LOAD_DB } {
  load_db -top ${TOP_MODULE}
  if { [file exists $sdc_file] } { read_sdc $sdc_file; }

} elseif { $MODE == "QUARTUS" } {
  set verilog ${DESIGN}.vo
  set is_migrated false
  if { ! [file exists $verilog] } {
    set verilog [file join . simulation modelsim ${DESIGN}.vo]
    set is_migrated true
  }
  if { ! [file exists $verilog] } {
    error "Can not find design verilog file $verilog"
  }
  alta::tcl_highlight "Using design verilog file $verilog.\n"
  if { $ve_file != "" && ! [file exists $ve_file] } {
    alta::tcl_warn "Can not find design VE file $ve_file"
    set ve_file ""
  } else {
    alta::tcl_highlight "Using design VE file $ve_file.\n"
  }
  set ret [read_design -top ${TOP_MODULE} -ve $ve_file -qsf $ORIGINAL_QSF $verilog -hierachy 1]
  if { !$ret } { exit -1; }

  if { $sdc_file != "" && ! [file exists $sdc_file] } {
    alta::tcl_warn "Can not find design SDC file $sdc_file"
    set sdc_file ""
  } else {
    alta::tcl_highlight "Using design SDC file $sdc_file.\n"
    read_sdc $sdc_file
  }

} elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } {
  set_hierarchy_separator .
  set db_gclk_assignment_level 2
  set verilog ${DESIGN}.vqm
  set is_migrated false
  if { ! [file exists $verilog] } {
    error "Can not find design verilog file $verilog"
  }

  if { $VEX_FILE != "" } {
    if { $VEX_FILE == "-" } {
      set VEX_FILE ""
    } elseif { ! [file exists $VEX_FILE] } {
      error "Can not find design VE file $VEX_FILE"
    }
  }
  if { $AGF_FILE != "" } {
    if { $AGF_FILE == "-" } {
      set AGF_FILE ""
    } elseif { ! [file exists $AGF_FILE] } {
      error "Can not find design AGF file $AGF_FILE"
    }
  }

  set alta0_asf [file join $::alta_work alta0.asf]
  set alta0_apf [file join $::alta_work alta0.apf]
  file delete -force $alta0_asf
  file delete -force $alta0_apf
  if { $AGF_FILE != "" || $VEX_FILE != "" } {
    alta::convert_pio_settings_cmd $VEX_FILE $AGF_FILE $alta0_asf $alta0_apf
  }

  alta::tcl_highlight "Using design verilog file $verilog.\n"
  if { $sdc_file != "" && ! [file exists $sdc_file] } {
    alta::tcl_warn "Can not find design SDC file $sdc_file"
    set sdc_file ""
  } else {
    alta::tcl_highlight "Using design SDC file $sdc_file.\n"
  }
  set load_pack ""
  if { $LOAD_PACK  } { set load_pack  "-load_pack"; }
  set ret [eval "read_design_and_pack $load_pack -sdc {$sdc_file} -top ${TOP_MODULE} -type vqm -gclk_level 2 $verilog"]

  set FITTER "full"
  if { !$ret } { exit -1; }

} else {
  error "Unsupported mode $MODE"
}

if { $FLOW == "PACK" } { break }

if { [info exists FITTING] } {
  if { $FITTING == "Auto" } { set FITTING auto; }
  set_mode -fitting $FITTING
}
if { [info exists FITTER] } {
  if { $FITTER == "Auto" } {
    if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; }
  }
  if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; }
  set_mode -fitter $FITTER
}
if { [info exists EFFORT] } { set_mode -effort $EFFORT; }
if { [info exists SKEW  ] } { set_mode -skew   $SKEW  ; }
if { [info exists SKOPE ] } { set_mode -skope  $SKOPE ; }
if { [info exists HOLDX ] } { set_mode -holdx  $HOLDX; }
if { [info exists TUNING] } { set_mode -tuning $TUNING; }
if { [info exists TARGET] } { set_mode -target $TARGET; }
if { [info exists PRESET] } { set_mode -preset $PRESET; }
if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; }

set alta_aqf [file join $::alta_work alta.aqf]
if { $LOAD_DB } {
  # Empty
} else {
  file delete -force $alta_aqf
  if { true } {
    if { $ORIGINAL_PIN != "" } {
      if { [file exists $VE_FILE] } {
        set ORIGINAL_PIN ""
      } elseif { $ORIGINAL_PIN == "-" } {
        set ORIGINAL_PIN ""
      } elseif { ! [file exists $ORIGINAL_PIN] } {
        if { $is_migrated } {
          error "Can not find design PIN file $ORIGINAL_PIN, please compile design first"
        }
        set ORIGINAL_PIN ""
      }
    }
    if { $ORIGINAL_QSF != "" } {
      if { $ORIGINAL_QSF == "-" } {
        set ORIGINAL_QSF ""
      } elseif { ! [file exists $ORIGINAL_QSF] } {
        if { $is_migrated } {
          error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first"
        }
      }
    }
    if { $ORIGINAL_QSF != "" || $ORIGINAL_PIN != "" } {
      alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf
    }
  }
}
if { [file exists "$alta_aqf"] } {
  alta::tcl_highlight "Using AQF file $alta_aqf.\n"
  source "$alta_aqf"
}
if { [file exists [file join . ${DESIGN}.asf]] } {
  alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n"
  source [file join . ${DESIGN}.asf]
}

if { $FLOW == "PROBE" } {
  set ret [eval "place_pseudo ${user_io} -place_io -place_pll -place_gclk"]
  if { !$ret } { exit -1 }

  set force ""
  if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" }
  eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}"

} elseif { $FLOW == "CHECK" } {
  set ret [eval "place_pseudo ${user_io} -place_io -place_pll -place_gclk"]
  if { !$ret } { exit -1 }

  if { [file exists [file join . ${DESIGN}.chk]] } {
    alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n"
    source [file join . ${DESIGN}.chk]
    place_design -dry
    check_design -rule led_guide
  } else {
    error "Can not find design CHECK file ${DESIGN}.chk"
  }

} else {
  set ret [eval "place_pseudo ${user_io} -place_io -place_pll -place_gclk -warn_io"]
  if { !$ret } { exit -1 }

  set org_place ""
  set load_place ""
  set load_route ""
  set quiet ""
  if {  $ORG_PLACE } { set  org_place "-org_place" ; }
  if { $LOAD_PLACE } { set load_place "-load_place"; }
  if { $LOAD_ROUTE } { set load_route "-load_route"; }
  eval "place_and_route_design $org_place $load_place $load_route \
                               -retry $RETRY $seed_rand $quiet"
}

date_time
if { $FLOW != "CHECK" } {
if { $FLOW != "PROBE" } {
report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
report_timing -verbose 1 -setup -file $::alta_work/setup_summary.rpt
report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
report_timing -verbose 1 -hold -file $::alta_work/hold_summary.rpt

set ta_report_auto_constraints 0
report_timing -fmax -file $::alta_work/fmax.rpt
report_timing -xfer -file $::alta_work/xfer.rpt
set ta_report_auto_constraints $ta_report_auto

set ta_dump_uncovered 1
report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
set ta_dump_uncovered -1


if { ! [info exists rt_report_timing_fast] } {
  set rt_report_timing_fast false
}
if { $rt_report_timing_fast } {
  set_timing_corner fast
  route_delay -quiet
  report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz
  report_timing -verbose 1 -setup -file $::alta_work/setup_fast_summary.rpt
  report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz
  report_timing -verbose 1 -hold -file $::alta_work/hold_fast_summary.rpt
  set ta_report_auto_constraints 0
  report_timing -fmax -file $::alta_work/fmax_fast.rpt
  report_timing -xfer -file $::alta_work/xfer_fast.rpt
  set ta_report_auto_constraints $ta_report_auto
}

write_routed_design "${RESULT_DIR}/${RESULT}_routed.v"
}

bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin"
if { true } {
alta::bin_to_asc "${RESULT_DIR}/${RESULT}.bin" "${RESULT_DIR}/${RESULT}.inc"
set python_exe [expr {$tcl_platform(platform) eq "unix" ? "python3" : "python.exe"}]
if { ! [ info exist BATCH_ARG ] } {
  set BATCH_ARG ""
}
set LOGIC_COMPRESS [alta::get_global_assignment_cmd ON_CHIP_BITSTREAM_DECOMPRESSION false]
if { [string toupper $LOGIC_COMPRESS] != "OFF" } {
  set BATCH_ARG "$BATCH_ARG --logic-compress"
}
set BATCH_MCU 0xbff5105000730062aa234371030002b7
if { [info exists BATCH_HSE] } {
  set BATCH_MCU 0xbff5105000730062a62343110062aa234371030002b7
}
set GEN_BATCH "{[alta::prog_home]/python_dist/$python_exe} {[alta::prog_home]/pio/gen_batch}\
  -d [[alta::get_device_info_cmd $DEVICE] device_id]\
  -i $BATCH_MCU\
  -o ${RESULT_DIR}/${RESULT}_batch.bin\
  --logic-config ${RESULT_DIR}/${RESULT}.bin\
  --logic-address 0x80007000\
  $BATCH_ARG"
alta::tcl_highlight "Generating batch file: $GEN_BATCH\n"
eval "exec $GEN_BATCH"
} else {
bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg"
bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf"
generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \
                -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse
generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \
                -inputs "${RESULT_DIR}/${RESULT}.bin"
generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \
  -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg"
}
}
break
}
Total IO  : 150
Total Pin : 128/17
Top array is built.
Loading architect libraries...

## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 52MB (52MB)
Loading route table...

## CPU time: 0:0:2, REAL time: 0:0:2
## Memory Usage: 317MB (317MB)
Using design verilog file ./simulation/modelsim/test_uart.vo.
Using design VE file test_uart.vex.
Preparing design...

Info: Rename duplicated module cell alta_rv32 to alta_rv32_duplicated at ./alta_db/flatten.vx:1.
Info: Removing bbox feeder slice gpio1_io_out_data[0] driven by BBOX rv32|gpio1_io_out_data[0].
Info: Removing bbox feeder slice gpio1_io_out_data[1] driven by BBOX rv32|gpio1_io_out_data[1].
Info: Removing bbox feeder slice gpio1_io_out_data[2] driven by BBOX rv32|gpio1_io_out_data[2].
Info: Removing bbox feeder slice gpio1_io_out_data[3] driven by BBOX rv32|gpio1_io_out_data[3].
Info: Removing bbox feeder slice gpio1_io_out_data[4] driven by BBOX rv32|gpio1_io_out_data[4].
Info: Removing bbox feeder slice gpio1_io_out_data[5] driven by BBOX rv32|gpio1_io_out_data[5].
Info: Removing bbox feeder slice gpio1_io_out_data[6] driven by BBOX rv32|gpio1_io_out_data[6].
Info: Removing bbox feeder slice gpio1_io_out_data[7] driven by BBOX rv32|gpio1_io_out_data[7].
Info: Removing bbox feeder slice gpio1_io_out_en[0] driven by BBOX rv32|gpio1_io_out_en[0].
Info: Removing bbox feeder slice gpio1_io_out_en[1] driven by BBOX rv32|gpio1_io_out_en[1].
Info: Removing bbox feeder slice gpio1_io_out_en[2] driven by BBOX rv32|gpio1_io_out_en[2].
Info: Removing bbox feeder slice gpio1_io_out_en[3] driven by BBOX rv32|gpio1_io_out_en[3].
Info: Removing bbox feeder slice gpio1_io_out_en[4] driven by BBOX rv32|gpio1_io_out_en[4].
Info: Removing bbox feeder slice gpio1_io_out_en[5] driven by BBOX rv32|gpio1_io_out_en[5].
Info: Removing bbox feeder slice gpio1_io_out_en[6] driven by BBOX rv32|gpio1_io_out_en[6].
Info: Removing bbox feeder slice gpio1_io_out_en[7] driven by BBOX rv32|gpio1_io_out_en[7].
Info: Removing bbox feeder slice gpio2_io_out_data[0] driven by BBOX rv32|gpio2_io_out_data[0].
Info: Removing bbox feeder slice gpio2_io_out_data[1] driven by BBOX rv32|gpio2_io_out_data[1].
Info: Removing bbox feeder slice gpio2_io_out_data[2] driven by BBOX rv32|gpio2_io_out_data[2].
Info: Removing bbox feeder slice gpio2_io_out_data[3] driven by BBOX rv32|gpio2_io_out_data[3].
Info: Removing bbox feeder slice gpio2_io_out_data[4] driven by BBOX rv32|gpio2_io_out_data[4].
Info: Removing bbox feeder slice gpio2_io_out_data[5] driven by BBOX rv32|gpio2_io_out_data[5].
Info: Removing bbox feeder slice gpio2_io_out_data[6] driven by BBOX rv32|gpio2_io_out_data[6].
Info: Removing bbox feeder slice gpio2_io_out_data[7] driven by BBOX rv32|gpio2_io_out_data[7].
Info: Removing bbox feeder slice gpio2_io_out_en[0] driven by BBOX rv32|gpio2_io_out_en[0].
Info: Removing bbox feeder slice gpio2_io_out_en[1] driven by BBOX rv32|gpio2_io_out_en[1].
Info: Removing bbox feeder slice gpio2_io_out_en[2] driven by BBOX rv32|gpio2_io_out_en[2].
Info: Removing bbox feeder slice gpio2_io_out_en[3] driven by BBOX rv32|gpio2_io_out_en[3].
Info: Removing bbox feeder slice gpio2_io_out_en[4] driven by BBOX rv32|gpio2_io_out_en[4].
Info: Removing bbox feeder slice gpio2_io_out_en[5] driven by BBOX rv32|gpio2_io_out_en[5].
Info: Removing bbox feeder slice gpio2_io_out_en[6] driven by BBOX rv32|gpio2_io_out_en[6].
Info: Removing bbox feeder slice gpio2_io_out_en[7] driven by BBOX rv32|gpio2_io_out_en[7].
Info: Removing bbox feeder slice gpio3_io_in[0] driving BBOX rv32|gpio3_io_in[0].
Info: Removing bbox feeder slice gpio3_io_in[1] driving BBOX rv32|gpio3_io_in[1].
Info: Removing bbox feeder slice gpio3_io_in[2] driving BBOX rv32|gpio3_io_in[2].
Info: Removing bbox feeder slice gpio3_io_in[3] driving BBOX rv32|gpio3_io_in[3].
Info: Removing bbox feeder slice gpio3_io_in[4] driving BBOX rv32|gpio3_io_in[4].
Info: Removing bbox feeder slice gpio4_io_in[0] driving BBOX rv32|gpio4_io_in[0].
Info: Removing bbox feeder slice gpio4_io_in[1] driving BBOX rv32|gpio4_io_in[1].
Info: Removing bbox feeder slice gpio4_io_in[2] driving BBOX rv32|gpio4_io_in[2].
Info: Removing bbox feeder slice gpio4_io_in[3] driving BBOX rv32|gpio4_io_in[3].
Info: Removing bbox feeder slice gpio4_io_in[4] driving BBOX rv32|gpio4_io_in[4].
Info: Removing bbox feeder slice gpio4_io_in[5] driving BBOX rv32|gpio4_io_in[5].
Info: Removing bbox feeder slice gpio5_io_in[0] driving BBOX rv32|gpio5_io_in[0].
Info: Removing bbox feeder slice gpio5_io_in[1] driving BBOX rv32|gpio5_io_in[1].
Info: Removing bbox feeder slice gpio5_io_in[2] driving BBOX rv32|gpio5_io_in[2].
Info: Removing bbox feeder slice gpio5_io_in[3] driving BBOX rv32|gpio5_io_in[3].
Info: Removing bbox feeder slice gpio5_io_in[4] driving BBOX rv32|gpio5_io_in[4].
Info: Removing bbox feeder slice gpio5_io_in[5] driving BBOX rv32|gpio5_io_in[5].
Info: Removing bbox feeder slice gpio6_io_in[6] driving BBOX rv32|gpio6_io_in[6].
Info: Removing bbox feeder slice gpio6_io_in[7] driving BBOX rv32|gpio6_io_in[7].
Info: Removing bbox feeder slice gpio6_io_out_data[0] driven by BBOX rv32|gpio6_io_out_data[0].
Info: Removing bbox feeder slice gpio6_io_out_data[2] driven by BBOX rv32|gpio6_io_out_data[2].
Info: Removing bbox feeder slice gpio6_io_out_data[4] driven by BBOX rv32|gpio6_io_out_data[4].
Info: Removing bbox feeder slice gpio6_io_out_data[6] driven by BBOX rv32|gpio6_io_out_data[6].
Info: Removing bbox feeder slice gpio6_io_out_en[0] driven by BBOX rv32|gpio6_io_out_en[0].
Info: Removing bbox feeder slice gpio6_io_out_en[2] driven by BBOX rv32|gpio6_io_out_en[2].
Info: Removing bbox feeder slice gpio6_io_out_en[4] driven by BBOX rv32|gpio6_io_out_en[4].
Info: Removing bbox feeder slice gpio6_io_out_en[6] driven by BBOX rv32|gpio6_io_out_en[6].
Info: Removing bbox feeder slice gpio7_io_in[1] driving BBOX rv32|gpio7_io_in[1].
Info: Removing bbox feeder slice gpio7_io_out_data[6] driven by BBOX rv32|gpio7_io_out_data[6].
Info: Removing bbox feeder slice gpio7_io_out_en[6] driven by BBOX rv32|gpio7_io_out_en[6].
Info: Removing bbox feeder slice gpio8_io_out_data[0] driven by BBOX rv32|gpio8_io_out_data[0].
Info: Removing bbox feeder slice gpio8_io_out_data[1] driven by BBOX rv32|gpio8_io_out_data[1].
Info: Removing bbox feeder slice gpio8_io_out_data[2] driven by BBOX rv32|gpio8_io_out_data[2].
Info: Removing bbox feeder slice gpio8_io_out_data[3] driven by BBOX rv32|gpio8_io_out_data[3].
Info: Removing bbox feeder slice gpio8_io_out_data[4] driven by BBOX rv32|gpio8_io_out_data[4].
Info: Removing bbox feeder slice gpio8_io_out_data[6] driven by BBOX rv32|gpio8_io_out_data[6].
Info: Removing bbox feeder slice gpio8_io_out_data[7] driven by BBOX rv32|gpio8_io_out_data[7].
Info: Removing bbox feeder slice gpio8_io_out_en[0] driven by BBOX rv32|gpio8_io_out_en[0].
Info: Removing bbox feeder slice gpio8_io_out_en[1] driven by BBOX rv32|gpio8_io_out_en[1].
Info: Removing bbox feeder slice gpio8_io_out_en[2] driven by BBOX rv32|gpio8_io_out_en[2].
Info: Removing bbox feeder slice gpio8_io_out_en[3] driven by BBOX rv32|gpio8_io_out_en[3].
Info: Removing bbox feeder slice gpio8_io_out_en[4] driven by BBOX rv32|gpio8_io_out_en[4].
Info: Removing bbox feeder slice gpio8_io_out_en[6] driven by BBOX rv32|gpio8_io_out_en[6].
Info: Removing bbox feeder slice gpio9_io_in[1] driving BBOX rv32|gpio9_io_in[1].
Info: Removing bbox feeder slice gpio9_io_out_data[0] driven by BBOX rv32|gpio9_io_out_data[0].
Info: Removing bbox feeder slice gpio9_io_out_data[1] driven by BBOX rv32|gpio9_io_out_data[1].
Info: Removing bbox feeder slice gpio9_io_out_data[2] driven by BBOX rv32|gpio9_io_out_data[2].
Info: Removing bbox feeder slice gpio9_io_out_data[3] driven by BBOX rv32|gpio9_io_out_data[3].
Info: Removing bbox feeder slice gpio9_io_out_data[4] driven by BBOX rv32|gpio9_io_out_data[4].
Info: Removing bbox feeder slice gpio9_io_out_data[5] driven by BBOX rv32|gpio9_io_out_data[5].
Info: Removing bbox feeder slice gpio9_io_out_data[6] driven by BBOX rv32|gpio9_io_out_data[6].
Info: Removing bbox feeder slice gpio9_io_out_data[7] driven by BBOX rv32|gpio9_io_out_data[7].
Info: Removing bbox feeder slice gpio9_io_out_en[0] driven by BBOX rv32|gpio9_io_out_en[0].
Info: Removing bbox feeder slice gpio9_io_out_en[1] driven by BBOX rv32|gpio9_io_out_en[1].
Info: Removing bbox feeder slice gpio9_io_out_en[2] driven by BBOX rv32|gpio9_io_out_en[2].
Info: Removing bbox feeder slice gpio9_io_out_en[3] driven by BBOX rv32|gpio9_io_out_en[3].
Info: Removing bbox feeder slice gpio9_io_out_en[4] driven by BBOX rv32|gpio9_io_out_en[4].
Info: Removing bbox feeder slice gpio9_io_out_en[5] driven by BBOX rv32|gpio9_io_out_en[5].
Info: Removing bbox feeder slice gpio9_io_out_en[6] driven by BBOX rv32|gpio9_io_out_en[6].
Info: Removing bbox feeder slice gpio9_io_out_en[7] driven by BBOX rv32|gpio9_io_out_en[7].
Info: Removing bbox feeder slice macro_inst|u_ahb2apb|hreadyout~_wirecell driving BBOX rv32|mem_ahb_hreadyout inverted.
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|break_error_ie[1]~feeder driven by BBOX rv32|mem_ahb_hwdata[9].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|break_error_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[9].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|fbrd[1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|fbrd[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|framing_error_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|ibrd[12]~feeder driven by BBOX rv32|mem_ahb_hwdata[12].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|ibrd[5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|ibrd[7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|ibrd[9]~feeder driven by BBOX rv32|mem_ahb_hwdata[9].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|overrun_error_ie[1]~feeder driven by BBOX rv32|mem_ahb_hwdata[10].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|parity_error_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[8].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|rx_idle_ie[1]~feeder driven by BBOX rv32|mem_ahb_hwdata[11].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|rx_idle_ie[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[11].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|tx_dma_en[0]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|break_error_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[9].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|break_error_ie[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[9].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|fbrd[5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|framing_error_ie[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|ibrd[10]~feeder driven by BBOX rv32|mem_ahb_hwdata[10].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|ibrd[1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|ibrd[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|ibrd[5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|ibrd[6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|lcr_sps~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|rx_idle_ie[1]~feeder driven by BBOX rv32|mem_ahb_hwdata[11].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|rx_idle_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[11].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_regs|tx_dma_en[4]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2]~feeder driven by BBOX rv32|mem_ahb_hwdata[2].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4]~feeder driven by BBOX rv32|mem_ahb_hwdata[4].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0]~feeder driven by BBOX rv32|mem_ahb_hwdata[0].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1]~feeder driven by BBOX rv32|mem_ahb_hwdata[1].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3]~feeder driven by BBOX rv32|mem_ahb_hwdata[3].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5]~feeder driven by BBOX rv32|mem_ahb_hwdata[5].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6]~feeder driven by BBOX rv32|mem_ahb_hwdata[6].
Info: Removing bbox feeder slice macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7]~feeder driven by BBOX rv32|mem_ahb_hwdata[7].
Info: Removing bbox feeder slice sys_ctrl_clkSource[0] driven by BBOX rv32|sys_ctrl_clkSource[0].
Info: Removing bbox feeder slice sys_ctrl_clkSource[1] driven by BBOX rv32|sys_ctrl_clkSource[1].
## CPU time: 0:0:1, REAL time: 0:0:1
## Memory Usage: 337MB (337MB)
Pseudo pack design...

Using location file test_uart.vex
VCO frequency: 480.000 Mhz
  clkout0: Enabled , 240.000 Mhz
  clkout1: Disabled, 0.938 Mhz
  clkout2: Disabled, 0.938 Mhz
  clkout3: Enabled , 120.000 Mhz
  clkout4: Disabled, 0.938 Mhz
Info: Instance gclksw_inst|gclk_switch is identified as a clock switch.
Packing Statistics
 Total      Logics : 1988/2112 ( 94%)
 Total        LUTs : 1866/2112 ( 88%)
 Total   Registers : 1303/2112 ( 61%)
 Total  Block Rams :    0/   4 (  0%)
 Total        PLLs :    1/   1 (100%)
 Total        Pins :   58/ 128 ( 45%)
 Global    Signals :    4/   5 ( 80%)
                           PLL_ENABLE~clkctrl_outclk (from:                               PLL_ENABLE~combout)
      auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp (from:   auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp)
      auto_generated_inst.hbo_22_717df45ba12dbb20_bp (from:          pll_inst|auto_generated|pll1_CLK_bus[3])
                           sys_resetn~clkctrl_outclk (from:                               sys_resetn~combout)
 Total Lonely   Datain   : 177
 Total Lonely   Register : 17
 Total LUT-FF   Pairs    : 777
 Total Register Packings : 332
 Registers with synchronous    reset : 0
 Registers with asynchronous   reset : 897
 Registers with sync and async reset : 70
## CPU time: 0:0:0, REAL time: 0:0:1
## Memory Usage: 335MB (337MB)
Filter verilog...

## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 335MB (337MB)
Reading DB design...

## CPU time: 0:0:0, REAL time: 0:0:1
## Memory Usage: 337MB (337MB)
Processing design...

> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_CLK~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_5~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_6~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_4~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO6_0~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO6_4~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_3~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO6_2~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to uart15_tx~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_7~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[1]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to UART4_UARTTXD~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO_15~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO_12~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO6_6~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO_13~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_1~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_5~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to UART3_UARTTXD~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_0~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[0]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_2~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_7~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_6~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[11]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[5]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[7]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[6]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[8]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_1~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_2~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_0~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[3]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[2]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[9]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_1~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_2~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[4]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to SIM_IO[10]~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_5~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_7~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_6~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_4~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO2_0~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO1_3~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_4~output false
> set_instance_assignment -name ENABLE_OPEN_DRAIN -to GPIO9_3~output false
> set_instance_assignment -extension -name CLKIN_FREQ -to pll_inst|auto_generated|pll1 8
> set_instance_assignment -extension -name FIXED_COORD -to gclksw_inst|gclk_switch__alta_gclksw {22 4 0}
> set_instance_assignment -extension -name FIXED_COORD -to gclksw_inst|gclk_switch {22 4 5}
> set_location_assignment -to GPIO1_0 PIN_78
> set_location_assignment -to GPIO1_1 PIN_82
> set_location_assignment -to GPIO1_2 PIN_87
> set_location_assignment -to GPIO1_3 PIN_91
> set_location_assignment -to GPIO1_4 PIN_80
> set_location_assignment -to GPIO1_5 PIN_84
> set_location_assignment -to GPIO1_6 PIN_89
> set_location_assignment -to GPIO1_7 PIN_93
> set_location_assignment -to GPIO2_0 PIN_29
> set_location_assignment -to GPIO2_1 PIN_23
> set_location_assignment -to GPIO2_2 PIN_15
> set_location_assignment -to GPIO2_3 PIN_3
> set_location_assignment -to GPIO2_4 PIN_31
> set_location_assignment -to GPIO2_5 PIN_25
> set_location_assignment -to GPIO2_6 PIN_17
> set_location_assignment -to GPIO2_7 PIN_5
> set_location_assignment -to GPIO3_0 PIN_95
> set_location_assignment -to GPIO3_1 PIN_97
> set_location_assignment -to GPIO3_2 PIN_35
> set_location_assignment -to GPIO3_3 PIN_33
> set_location_assignment -to GPIO3_4 PIN_32
> set_location_assignment -to GPIO6_0 PIN_51
> set_location_assignment -to GPIO6_2 PIN_52
> set_location_assignment -to GPIO6_4 PIN_1
> set_location_assignment -to GPIO6_6 PIN_98
> set_location_assignment -to GPIO9_0 PIN_47
> set_location_assignment -to GPIO9_1 PIN_48
> set_location_assignment -to GPIO9_2 PIN_46
> set_location_assignment -to GPIO9_3 PIN_96
> set_location_assignment -to GPIO9_4 PIN_39
> set_location_assignment -to GPIO9_5 PIN_34
> set_location_assignment -to GPIO9_6 PIN_71
> set_location_assignment -to GPIO9_7 PIN_70
> set_location_assignment -to PIN_HSE PIN_HSE
> set_location_assignment -to PIN_HSI PIN_HSI
> set_location_assignment -to PIN_OSC PIN_OSC
> set_location_assignment -to SIM_CLK PIN_85
> set_location_assignment -to SIM_IO[0] PIN_77
> set_location_assignment -to SIM_IO[10] PIN_7
> set_location_assignment -to SIM_IO[11] PIN_2
> set_location_assignment -to SIM_IO[1] PIN_81
> set_location_assignment -to SIM_IO[2] PIN_86
> set_location_assignment -to SIM_IO[3] PIN_90
> set_location_assignment -to SIM_IO[4] PIN_79
> set_location_assignment -to SIM_IO[5] PIN_83
> set_location_assignment -to SIM_IO[6] PIN_88
> set_location_assignment -to SIM_IO[7] PIN_92
> set_location_assignment -to SIM_IO[8] PIN_26
> set_location_assignment -to SIM_IO[9] PIN_18
> set_location_assignment -to SIM_IO_12 PIN_30
> set_location_assignment -to SIM_IO_13 PIN_24
> set_location_assignment -to SIM_IO_15 PIN_4
> set_location_assignment -to UART3_UARTRXD PIN_66
> set_location_assignment -to UART3_UARTTXD PIN_67
> set_location_assignment -to UART4_UARTRXD PIN_38
> set_location_assignment -to UART4_UARTTXD PIN_36
> set_location_assignment -to uart15_rx PIN_69
> set_location_assignment -to uart15_tx PIN_68
Info: Found GCLK net PLL_ENABLE~clkctrl_outclk (1).
Info: Found GCLK net sys_resetn~clkctrl_outclk (124).
Info: Found GCLK net auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp (5).
Info: Found GCLK net auto_generated_inst.hbo_22_717df45ba12dbb20_bp (242).
Info: Fixing net rv32.resetn_out, from rv32|resetn_out to gclksw_inst|gclk_switch__alta_gclksw|resetn.
Info: Fixing net PIN_HSE~input_o, from PIN_HSE~input|combout to gclksw_inst|gclk_switch__alta_gclksw|clkin1.
Info: Fixing net gclksw_inst|gclk_switch__alta_gclksw__clkout, from gclksw_inst|gclk_switch__alta_gclksw|clkout to rv32|sys_clk.
Info: Fixing net auto_generated_inst.hbo_13_1797ab7b230f061a_bp, from pll_inst|auto_generated|pll1|lock to rv32|sys_ctrl_pllReady.
Info: Slice gpio3_io_in[5] is removed.
Info: Slice gpio3_io_in[6] is removed.
Info: Slice gpio3_io_in[7] is removed.
Info: Slice gpio4_io_in[6] is removed.
Info: Slice gpio4_io_in[7] is removed.
Info: Slice gpio5_io_in[6] is removed.
Info: Slice gpio5_io_in[7] is removed.
Info: Slice gpio6_io_in[0] is removed.
Info: Slice gpio6_io_in[2] is removed.
Info: Slice gpio6_io_in[4] is removed.
Info: Slice gpio7_io_in[0] is removed.
Info: Slice gpio7_io_in[5] is removed.
Info: Slice gpio7_io_in[6] is removed.
Info: Slice gpio7_io_in[7] is removed.
Info: Slice gpio7_io_in[2] is removed.
Info: Slice gpio7_io_in[3] is removed.
Info: Slice gpio7_io_in[4] is removed.
Info: Slice gpio9_io_in[0] is removed.
Info: Slice gpio9_io_in[5] is removed.
Info: Slice gpio9_io_in[6] is removed.
Info: Slice gpio9_io_in[7] is removed.
Info: Slice gpio9_io_in[2] is removed.
Info: Slice gpio9_io_in[3] is removed.
Info: Slice gpio9_io_in[4] is removed.
## CPU time: 0:0:0, REAL time: 0:0:0
## Memory Usage: 338MB (338MB)
Using design SDC file ./test_uart.sdc.
# pio_begin
if { ! [info exists ::HSI_PERIOD] } {
  set ::HSI_PERIOD 100.0
}
create_clock -name PIN_HSI -period $::HSI_PERIOD [get_ports PIN_HSI]
set_clock_groups -asynchronous -group PIN_HSI
if { ! [info exists ::HSE_PERIOD] } {
  set ::HSE_PERIOD 125.0
}
create_clock -name PIN_HSE -period $::HSE_PERIOD [get_ports PIN_HSE]
set_clock_groups -asynchronous -group PIN_HSE
derive_pll_clocks -create_base_clocks
Info: Auto constraint PLL: create_generated_clock -name pll_inst|auto_generated|pll1|clk[0] -multiply_by 30 -add -source PIN_HSE -master_clock PIN_HSE pll_inst|auto_generated|pll1|clkout0.
Info: Auto constraint PLL: create_generated_clock -name pll_inst|auto_generated|pll1|clk[3] -multiply_by 15 -add -source PIN_HSE -master_clock PIN_HSE pll_inst|auto_generated|pll1|clkout3.
set_false_path -from rv32|resetn_out
# pio_end
##

set SYS_CLK [get_clocks pll_inst|*clk*0*]
if { [get_clocks -nowarn pll_inst|*clk*3*] != {} } {
  set BUS_CLK [get_clocks pll_inst|*clk*3*]

  # Always make sure there is an extra cycle of margin for inter domain transfers between SYS_CLK
  # and BUS_CLK. The extra cycle is always in terms of the to (latching) clock.
  set_multicycle_path -from $SYS_CLK -to $BUS_CLK -setup 2
  set_multicycle_path -from $SYS_CLK -to $BUS_CLK -hold  1
  set_multicycle_path -from $BUS_CLK -to $SYS_CLK -setup 2
  set_multicycle_path -from $BUS_CLK -to $SYS_CLK -hold  1

  # These are for mem_ahb_hreadyout going into rv32, since it's ok for rv32 to receive
  # mem_ahb_hreadyout 1 cycle late. They theoretically should help useful skew.
  set_multicycle_path -from $SYS_CLK -to rv32 -setup 2
  set_multicycle_path -from $SYS_CLK -to rv32 -hold  1
}
> #set pl_criticality_wratio  "1.00 1.00 1.00 1.00"
> #set pl_max_iter_eco        "10 20 300 40 3  100 100 1"
> #set pl_eco_slack_crit      "99999. 1.00  0.10 5 0.03 20 0.01 100"
> 
> #set pl_priority_compare  "2 2 2 3"
> #set pl_priority_result   "2 1 1 0"
> #set pl_priority_pass     "2 1 1 0"
> #set pl_swap_cost_margin       "200.0  0.0  200.0  0.0  200.0  0.0   0.00  0.0"
> #set pl_swap_wirelength_margin "200.0  0.0  200.0  0.0  200.0  0.0   020.0 -0.3  2000. 1.30"
> #set pl_swap_congestion_margin "100.0  0.0  100.0  0.0  100.0  0.0   010.0 -0.3  1000. 1.15"
> #set pl_criticality_beta "1.0 3.0 1.0  1.0 3.0 1.0  1.0 3.0 1.0  99999 3.0 3.0"
> #set pl_oci_iter "1 1 100 1"
> 
>  set rt_retiming_idx         5
> #set rt_converge_accelerator "2 2 0 3"
> #set rt_pres_cost_ratio      "1.00 1.50  2.00 2.50"
> #set rt_dly_ratio            "0.50 0.30 0.30  0.50 0.50 0.30"
> #set rt_reroute_max_iter     "6  6 6  7 9  12"
> #set rt_reroute_start_iter   "0  2 2  2 4  0 "
> #set rt_quick_converge_ratio 0.50
>  set pl_reuse_existing_placement false
>  set pl_fix_bram_cells 0
>  set pl_fix_mult_cells 0
>  set pl_neighbor_swap_range "3  6  6  3 "
>  set pl_pass_result "1 1 1 1"
>  set pl_max_pass    "1 1 1 1 1"
>  set pl_max_iter       10
>  set pl_max_iter_part  20
>  set pl_max_iter_final 20
>  set pl_max_iter_legal 10
>  set pl_max_iter_touch 00
> #set pl_neighbor_swap_range "2  6  6  3 "
> #set pl_spread_swap_max_iter "3 5  5 4"
> #set pl_use_initial_place_once 0
>  set rt_min_converge "5"
>  set rt_optimize_max "3"
>  set pl_useful_skew_level -1
>  set rt_useful_skew_level 0
>  set rt_useful_skew_bram         true
>  set rt_useful_skew_io           false
>  set rt_useful_skew_io_ireg      false
>  set rt_useful_skew_io_oreg      false
>  set rt_useful_skew_output_io    false
>  set rt_useful_skew_input_io     false
>  set rt_useful_skew_unconstraint "false false"
>  set rt_useful_skew_max                "0 100"
>  set rt_skew_crit_minmax               "0.00 1.00"
> #set rt_useful_skew_setup_slac_margin  "1.00 1.00  1.00 1.00  1.00 0.10 0.50 0.10 0.70 0.10  1.00"
> #set rt_useful_skew_hold_slack_margin  "0.10 0.10  0.30 0.30  0.30 0.30"
> #set rt_useful_skew_hold_slack_ratio   "0.05 0.05  0.10 0.10  0.10 0.10"
> # Minimal logical slice hold fix, only by routing to bram/mult, no IO delay
> 
>  set ta_cross_clock_slack "2 0"
> 
> #set pl_max_iter_hold_fix "30 1 3"
> #set pl_hold_slack_margin  0.2
> #set pl_setup_slack_margin "0.5 -1000."
> #set pl_net_hold_fix_target "alta_bram alta_bram9k alta_mult"
> 
>  set rt_hold_slack_margin  "0.2 0.2    0.2 0.2    0.2 0.7   -1000. 0.0"
>  set rt_setup_slack_margin "0.5 -1000. 0.5 -1000. 0.0 -1000."
> #set rt_net_hold_crit_minmax "0.5 0.5"
>  set rt_net_hold_budget_method 0
>  set rt_net_hold_fix_target "alta_bram alta_bram9k alta_mult"
> 
> #set pl_net_hold_fix_clock false
> #set pl_net_hold_fix_auto  false
> #set pl_net_hold_fix_io    false
> #set rt_net_hold_fix_start false
> #set rt_net_hold_fix_clock false
> #set rt_net_hold_fix_auto  false
> #set rt_net_hold_fix_io    false
Using AQF file ./alta_db/alta.aqf.
> set_global_assignment -name DEVICE_IO_STANDARD "3.3-V LVTTL"
Using ASF file test_uart.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> if { [info exists BOARD_PLL_CLKIN] } {
  if { $BOARD_PLL_CLKIN == "PIN_OSC" } {
    set_config -loc 18 0 0 CFG_RCOSC_EN 1'b1
  }
}
> if { [info exists USB0_MODE] } {
  alta::tcl_info "USB0_MODE = $USB0_MODE"
  set_config -loc 0 1 3 CFG_PULLUP_ENB 1'b0
  set_config -loc 0 1 3 CFG_PULLDN_ENB 1'b0
}
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
> # set_instance_assignment -name WEAK_PULLUP -to uart_rxd* true
> 
> set_instance_assignment -name WEAK_PULLUP -to SIM_IO* true
> set_instance_assignment -name WEAK_PULLUP -to SIM_RST* true
Warn: [set_instance_assignment] Empty -to specified, objects SIM_RST* are not recognized.
> 
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_77
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_81
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_86
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_90
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_79
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_83
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_88
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_92
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_26
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_18
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_7
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_2
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_30
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_24
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_16
Warn: [set_instance_assignment] Empty -to specified, objects PIN_16 are not recognized.
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_4
> 
> 
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_48
> set_instance_assignment -name AUTO_OPEN_DRAIN_PINS ON -to PIN_98
Placement Statistics
 Total  Logic    Counts  : 1964/2112 (93.0%)
 Total  Logic    Tiles   : 132/132 (100.0%)
 Total  Valid    Nets    : 3051 (1520+1531)
 Total  Valid    Fanouts : 13298 (6988+6310)
 Total  Tile     Fanouts : 3461
 Tile   Zip      Fanins  : 19 (1:36)
 Tile   Zip      Fanouts : 27 (1:481)
 Total  Ignored  Nets    : 1330
 Total  Valid    Blocks  : 155 (132/21)
 Total  Ignored  Blocks  : 0
 Total  Zip Complexities : 1122/4003 1.74/1950.47
 Avg    Zip   Bottleneck : 7.30 82.54
 Avg    Net   Bottleneck : 18.97 523.94
Iter #1/1 ...
Pass 1 #1/1 ...
Partitioning...
 step = 0, partition : 20,12

 step = 1, partition : 10,7
....................
 step = 2, partition : 5,3
....................
 step = 3, partition : 2,2
....................
 step = 4, partition : 2,2
....................

## CPU time: 0:0:7, REAL time: 0:0:8
Pass 2 #1/1 ...
Legalization and Swapping...
..........

## CPU time: 0:0:4, REAL time: 0:0:5
Pass 3 #1/1 ...
Touchup...


## CPU time: 0:0:0, REAL time: 0:0:0
Pass 4 #1/1 ...
Optimization...
............................................................
Finishing...

## CPU time: 0:0:10, REAL time: 0:0:10
Total wire cost after placement: -0.953333:-0.2288:0.644(-0.953333:-0.2288) 6529.16(1358.04)+18985(0)+8935.54 8574.23(4637.34)+4740.75


*** Post Placement Timing Report ***

=== User constraints ===
Fmax report
  User constraint:   8.000MHz, Fmax: 140.588MHz, Clock: PIN_HSE
  User constraint:  10.000MHz, Fmax: 140.588MHz, Clock: PIN_HSI
  User constraint: 240.000MHz, Fmax: 195.313MHz, Clock: pll_inst|auto_generated|pll1|clk[0]
  User constraint: 120.000MHz, Fmax: 114.077MHz, Clock: pll_inst|auto_generated|pll1|clk[3]

Clock transfer report:
  Worst setup: 117.887, with clock PIN_HSE
  Worst setup:  92.887, with clock PIN_HSI
  Worst setup:  -0.953, with clock pll_inst|auto_generated|pll1|clk[0]
  Worst setup:  -0.433, with clock pll_inst|auto_generated|pll1|clk[3]
  Worst setup:   6.183, from clock pll_inst|auto_generated|pll1|clk[0] to pll_inst|auto_generated|pll1|clk[3]
  Worst setup:   3.158, from clock pll_inst|auto_generated|pll1|clk[3] to pll_inst|auto_generated|pll1|clk[0]

  Worst  hold:   0.615, with clock PIN_HSE
  Worst  hold:   0.615, with clock PIN_HSI
  Worst  hold:   0.615, with clock pll_inst|auto_generated|pll1|clk[0]
  Worst  hold:   0.603, with clock pll_inst|auto_generated|pll1|clk[3]
  Worst  hold:   0.750, from clock pll_inst|auto_generated|pll1|clk[0] to pll_inst|auto_generated|pll1|clk[3]
  Worst  hold:   1.079, from clock pll_inst|auto_generated|pll1|clk[3] to pll_inst|auto_generated|pll1|clk[0]

=== Auto constraints ===


Coverage report
  User constraints covered 9470 connections out of 9603 total, coverage: 98.6%
  Auto constraints covered 9470 connections out of 9603 total, coverage: 98.6%


Setup from rv32 to clken_ctrl_X59_Y2_N1, clock pll_inst|auto_generated|pll1|clk[0], constraint 4.167, skew 1.613, data 6.600
  Slack:  -0.953
    Arrival Time:    5.645
    Required Time:   4.692

*** End Timing Report ***



route_design -dump ./alta_db/route.tx -replace ./alta_db/replace.tx 

Route Design Statistics
 Total Routing Nets : 3051
 Fanout     Average : 3.36 (1..242)
 Max   Fanout  Net  : auto_generated_inst.hbo_22_717df45ba12dbb20_bp
 Logic       Slices : 1964/2112 (93.0%)

Routing...
 Budget Useful Skew...
## CPU time: 0:0:0, REAL time: 0:0:1
 iter = 1/1, route#: 3051, violation# : 1835, overflow# : 1727, conflict# : 1488, node#: 18654
## CPU time: 0:0:1, REAL time: 0:0:2
 iter = 2/2, route#: 3051, violation# : 1344, overflow# : 1308, conflict# : 1156, node#: 19699
## CPU time: 0:0:2, REAL time: 0:0:2
 iter = 3/3, route#: 3051, violation# : 602, overflow# : 588, conflict# : 597, node#: 20863
## CPU time: 0:0:2, REAL time: 0:0:3
 iter = 4/4, route#: 3051, violation# : 304, overflow# : 300, conflict# : 317, node#: 21518
## CPU time: 0:0:3, REAL time: 0:0:3
 iter = 5/5, route#: 3051, violation# : 207, overflow# : 204, conflict# : 242, node#: 21793
## CPU time: 0:0:3, REAL time: 0:0:4
 iter = 6/6, route#: 3051, violation# : 134, overflow# : 134, conflict# : 198, node#: 21938
## CPU time: 0:0:4, REAL time: 0:0:4
 iter = 7/7, route#: 3051, violation# : 128, overflow# : 128, conflict# : 182, node#: 22073
## CPU time: 0:0:4, REAL time: 0:0:5
 iter = 8/3, route#: 336, violation# : 312, overflow# : 312, conflict# : 301, node#: 21420
## CPU time: 0:0:5, REAL time: 0:0:5
 iter = 9/4, route#: 267, violation# : 162, overflow# : 161, conflict# : 199, node#: 21745
## CPU time: 0:0:5, REAL time: 0:0:6
 iter = 10/5, route#: 280, violation# : 112, overflow# : 112, conflict# : 172, node#: 21886
## CPU time: 0:0:5, REAL time: 0:0:6
 iter = 11/6, route#: 115, violation# : 51, overflow# : 51, conflict# : 82, node#: 22159
## CPU time: 0:0:6, REAL time: 0:0:6
 iter = 12/7, route#: 181, violation# : 47, overflow# : 47, conflict# : 82, node#: 22232
## CPU time: 0:0:6, REAL time: 0:0:7
 iter = 13/8, route#: 88, violation# : 36, overflow# : 36, conflict# : 64, node#: 22373
## CPU time: 0:0:6, REAL time: 0:0:7
 iter = 14/5, route#: 83, violation# : 55, overflow# : 55, conflict# : 82, node#: 22264
## CPU time: 0:0:6, REAL time: 0:0:7
 iter = 15/6, route#: 62, violation# : 25, overflow# : 25, conflict# : 44, node#: 22350
## CPU time: 0:0:6, REAL time: 0:0:7
 iter = 16/7, route#: 49, violation# : 20, overflow# : 20, conflict# : 38, node#: 22427
## CPU time: 0:0:7, REAL time: 0:0:7
 iter = 17/8, route#: 30, violation# : 16, overflow# : 16, conflict# : 27, node#: 22465
## CPU time: 0:0:7, REAL time: 0:0:7
 iter = 18/9, route#: 47, violation# : 18, overflow# : 18, conflict# : 31, node#: 22506
## CPU time: 0:0:7, REAL time: 0:0:7
 iter = 19/10, route#: 22, violation# : 14, overflow# : 14, conflict# : 26, node#: 22537
## CPU time: 0:0:7, REAL time: 0:0:8
 iter = 20/5, route#: 50, violation# : 38, overflow# : 38, conflict# : 58, node#: 22483
## CPU time: 0:0:7, REAL time: 0:0:8
 iter = 21/6, route#: 78, violation# : 39, overflow# : 39, conflict# : 53, node#: 22455
## CPU time: 0:0:7, REAL time: 0:0:8
 iter = 22/7, route#: 55, violation# : 22, overflow# : 22, conflict# : 37, node#: 22548
## CPU time: 0:0:7, REAL time: 0:0:8
 iter = 23/8, route#: 39, violation# : 22, overflow# : 22, conflict# : 36, node#: 22644
## CPU time: 0:0:7, REAL time: 0:0:8
 iter = 24/9, route#: 47, violation# : 15, overflow# : 15, conflict# : 26, node#: 22609
## CPU time: 0:0:7, REAL time: 0:0:8
 iter = 25/10, route#: 34, violation# : 16, overflow# : 16, conflict# : 27, node#: 22661
## CPU time: 0:0:8, REAL time: 0:0:8
 iter = 26/5, route#: 117, violation# : 68, overflow# : 68, conflict# : 95, node#: 22451
## CPU time: 0:0:8, REAL time: 0:0:8
 iter = 27/6, route#: 71, violation# : 40, overflow# : 40, conflict# : 63, node#: 22601
## CPU time: 0:0:8, REAL time: 0:0:9
 iter = 28/7, route#: 67, violation# : 27, overflow# : 27, conflict# : 42, node#: 22679
## CPU time: 0:0:8, REAL time: 0:0:9
 iter = 29/8, route#: 70, violation# : 17, overflow# : 17, conflict# : 30, node#: 22711
## CPU time: 0:0:8, REAL time: 0:0:9
 iter = 30/9, route#: 35, violation# : 14, overflow# : 14, conflict# : 25, node#: 22762
## CPU time: 0:0:8, REAL time: 0:0:9
 iter = 31/10, route#: 18, violation# : 16, overflow# : 16, conflict# : 24, node#: 22783
## CPU time: 0:0:8, REAL time: 0:0:9
 iter = 32/5, route#: 101, violation# : 56, overflow# : 56, conflict# : 77, node#: 22577
## CPU time: 0:0:8, REAL time: 0:0:9
 iter = 33/6, route#: 78, violation# : 33, overflow# : 33, conflict# : 54, node#: 22615
## CPU time: 0:0:9, REAL time: 0:0:9
 iter = 34/7, route#: 32, violation# : 17, overflow# : 17, conflict# : 30, node#: 22704
## CPU time: 0:0:9, REAL time: 0:0:9
 iter = 35/8, route#: 40, violation# : 11, overflow# : 11, conflict# : 21, node#: 22741
## CPU time: 0:0:9, REAL time: 0:0:9
 iter = 36/9, route#: 19, violation# : 11, overflow# : 11, conflict# : 20, node#: 22763
## CPU time: 0:0:9, REAL time: 0:0:9
 iter = 37/10, route#: 23, violation# : 12, overflow# : 12, conflict# : 19, node#: 22779
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 38/5, route#: 90, violation# : 56, overflow# : 56, conflict# : 84, node#: 22572
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 39/6, route#: 81, violation# : 31, overflow# : 31, conflict# : 55, node#: 22649
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 40/7, route#: 36, violation# : 23, overflow# : 23, conflict# : 35, node#: 22724
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 41/8, route#: 28, violation# : 10, overflow# : 10, conflict# : 18, node#: 22735
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 42/9, route#: 27, violation# : 10, overflow# : 10, conflict# : 19, node#: 22768
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 43/10, route#: 26, violation# : 8, overflow# : 8, conflict# : 16, node#: 22753
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 44/5, route#: 19, violation# : 11, overflow# : 11, conflict# : 16, node#: 22726
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 45/6, route#: 9, violation# : 8, overflow# : 8, conflict# : 13, node#: 22742
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 46/7, route#: 23, violation# : 6, overflow# : 6, conflict# : 11, node#: 22767
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 47/8, route#: 9, violation# : 5, overflow# : 5, conflict# : 7, node#: 22804
## CPU time: 0:0:9, REAL time: 0:0:10
 iter = 48/9, route#: 10, violation# : 3, overflow# : 3, conflict# : 5, node#: 22814
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 49/10, route#: 4, violation# : 2, overflow# : 2, conflict# : 4, node#: 22814
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 50/5, route#: 22, violation# : 15, overflow# : 15, conflict# : 22, node#: 22746
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 51/6, route#: 18, violation# : 8, overflow# : 8, conflict# : 12, node#: 22772
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 52/7, route#: 9, violation# : 6, overflow# : 6, conflict# : 10, node#: 22784
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 53/8, route#: 15, violation# : 5, overflow# : 5, conflict# : 9, node#: 22786
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 54/9, route#: 8, violation# : 3, overflow# : 3, conflict# : 6, node#: 22794
## CPU time: 0:0:10, REAL time: 0:0:10
 iter = 55/10, route#: 22, violation# : 10, overflow# : 10, conflict# : 13, node#: 22820
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 56/5, route#: 10, violation# : 11, overflow# : 11, conflict# : 16, node#: 22784
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 57/6, route#: 19, violation# : 9, overflow# : 9, conflict# : 16, node#: 22771
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 58/7, route#: 34, violation# : 10, overflow# : 10, conflict# : 17, node#: 22785
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 59/8, route#: 12, violation# : 8, overflow# : 8, conflict# : 13, node#: 22824
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 60/9, route#: 24, violation# : 8, overflow# : 8, conflict# : 14, node#: 22853
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 61/10, route#: 19, violation# : 4, overflow# : 4, conflict# : 7, node#: 22892
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 62/5, route#: 6, violation# : 4, overflow# : 4, conflict# : 7, node#: 22865
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 63/6, route#: 8, violation# : 4, overflow# : 4, conflict# : 6, node#: 22847
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 64/7, route#: 13, violation# : 8, overflow# : 8, conflict# : 13, node#: 22850
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 65/8, route#: 13, violation# : 3, overflow# : 3, conflict# : 6, node#: 22863
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 66/9, route#: 5, violation# : 3, overflow# : 3, conflict# : 6, node#: 22872
## CPU time: 0:0:10, REAL time: 0:0:11
 iter = 67/10, route#: 8, violation# : 0, overflow# : 0, conflict# : 0, node#: 22880
## CPU time: 0:0:11, REAL time: 0:0:12
 iter = 68/3, route#: 375, violation# : 216, overflow# : 216, conflict# : 261, node#: 21908
## CPU time: 0:0:11, REAL time: 0:0:12
 iter = 69/4, route#: 193, violation# : 44, overflow# : 44, conflict# : 78, node#: 22194
## CPU time: 0:0:11, REAL time: 0:0:12
 iter = 70/5, route#: 93, violation# : 15, overflow# : 15, conflict# : 28, node#: 22268
## CPU time: 0:0:11, REAL time: 0:0:12
 iter = 71/6, route#: 20, violation# : 6, overflow# : 6, conflict# : 12, node#: 22305
## CPU time: 0:0:12, REAL time: 0:0:12
 iter = 72/7, route#: 51, violation# : 4, overflow# : 4, conflict# : 8, node#: 22294
## CPU time: 0:0:12, REAL time: 0:0:12
 iter = 73/3, route#: 68, violation# : 35, overflow# : 35, conflict# : 53, node#: 22212
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 74/4, route#: 84, violation# : 33, overflow# : 33, conflict# : 47, node#: 22164
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 75/5, route#: 46, violation# : 4, overflow# : 4, conflict# : 8, node#: 22278
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 76/6, route#: 7, violation# : 1, overflow# : 1, conflict# : 2, node#: 22298
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 77/7, route#: 45, violation# : 2, overflow# : 2, conflict# : 4, node#: 22265
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 78/8, route#: 3, violation# : 1, overflow# : 1, conflict# : 2, node#: 22269
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 79/5, route#: 2, violation# : 1, overflow# : 1, conflict# : 2, node#: 22265
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 80/6, route#: 2, violation# : 1, overflow# : 1, conflict# : 2, node#: 22265
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 81/7, route#: 3, violation# : 1, overflow# : 1, conflict# : 2, node#: 22265
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 82/8, route#: 3, violation# : 2, overflow# : 2, conflict# : 3, node#: 22275
## CPU time: 0:0:12, REAL time: 0:0:13
 iter = 83/9, route#: 3, violation# : 0, overflow# : 0, conflict# : 0, node#: 22273
## CPU time: 0:0:13, REAL time: 0:0:13
 iter = 84/3, route#: 207, violation# : 94, overflow# : 94, conflict# : 131, node#: 21963
## CPU time: 0:0:13, REAL time: 0:0:14
 iter = 85/4, route#: 105, violation# : 30, overflow# : 30, conflict# : 55, node#: 22095
## CPU time: 0:0:13, REAL time: 0:0:14
 iter = 86/5, route#: 65, violation# : 7, overflow# : 7, conflict# : 13, node#: 22169
## CPU time: 0:0:13, REAL time: 0:0:14
 iter = 87/6, route#: 18, violation# : 3, overflow# : 3, conflict# : 5, node#: 22195
## CPU time: 0:0:13, REAL time: 0:0:14
 iter = 88/7, route#: 42, violation# : 0, overflow# : 0, conflict# : 0, node#: 22202
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 89/3, route#: 182, violation# : 110, overflow# : 110, conflict# : 131, node#: 21976
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 90/4, route#: 114, violation# : 34, overflow# : 34, conflict# : 56, node#: 22139
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 91/5, route#: 56, violation# : 6, overflow# : 6, conflict# : 12, node#: 22217
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 92/6, route#: 10, violation# : 3, overflow# : 3, conflict# : 6, node#: 22223
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 93/7, route#: 34, violation# : 1, overflow# : 1, conflict# : 2, node#: 22240
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 94/5, route#: 40, violation# : 3, overflow# : 3, conflict# : 6, node#: 22210
## CPU time: 0:0:14, REAL time: 0:0:15
 iter = 95/6, route#: 4, violation# : 1, overflow# : 1, conflict# : 2, node#: 22222
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 96/7, route#: 25, violation# : 1, overflow# : 1, conflict# : 2, node#: 22215
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 97/8, route#: 2, violation# : 2, overflow# : 2, conflict# : 3, node#: 22222
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 98/9, route#: 24, violation# : 2, overflow# : 2, conflict# : 4, node#: 22234
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 99/10, route#: 3, violation# : 2, overflow# : 2, conflict# : 3, node#: 22233
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 100/5, route#: 3, violation# : 2, overflow# : 2, conflict# : 3, node#: 22233
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 101/6, route#: 4, violation# : 2, overflow# : 2, conflict# : 4, node#: 22233
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 102/7, route#: 3, violation# : 2, overflow# : 2, conflict# : 4, node#: 22230
## CPU time: 0:0:15, REAL time: 0:0:15
 iter = 103/8, route#: 6, violation# : 1, overflow# : 1, conflict# : 2, node#: 22250
## CPU time: 0:0:15, REAL time: 0:0:16
 iter = 104/9, route#: 3, violation# : 0, overflow# : 0, conflict# : 0, node#: 22242
## CPU time: 0:0:15, REAL time: 0:0:16
 iter = 105/3, route#: 152, violation# : 80, overflow# : 80, conflict# : 110, node#: 22014
## CPU time: 0:0:15, REAL time: 0:0:16
 iter = 106/4, route#: 63, violation# : 17, overflow# : 17, conflict# : 29, node#: 22157
## CPU time: 0:0:15, REAL time: 0:0:16
 iter = 107/5, route#: 53, violation# : 5, overflow# : 5, conflict# : 10, node#: 22181
## CPU time: 0:0:16, REAL time: 0:0:16
 iter = 108/6, route#: 8, violation# : 2, overflow# : 2, conflict# : 4, node#: 22203
## CPU time: 0:0:16, REAL time: 0:0:16
 iter = 109/7, route#: 37, violation# : 4, overflow# : 4, conflict# : 7, node#: 22220
## CPU time: 0:0:16, REAL time: 0:0:16
 iter = 110/3, route#: 55, violation# : 26, overflow# : 26, conflict# : 38, node#: 22111
## CPU time: 0:0:16, REAL time: 0:0:17
 iter = 111/4, route#: 52, violation# : 16, overflow# : 16, conflict# : 23, node#: 22136
## CPU time: 0:0:16, REAL time: 0:0:17
 iter = 112/5, route#: 31, violation# : 3, overflow# : 3, conflict# : 6, node#: 22176
## CPU time: 0:0:16, REAL time: 0:0:17
 iter = 113/6, route#: 4, violation# : 1, overflow# : 1, conflict# : 2, node#: 22188
## CPU time: 0:0:16, REAL time: 0:0:17
 iter = 114/7, route#: 31, violation# : 1, overflow# : 1, conflict# : 2, node#: 22211
## CPU time: 0:0:16, REAL time: 0:0:17
 iter = 115/8, route#: 2, violation# : 0, overflow# : 0, conflict# : 0, node#: 22209
Optimizing...
...

Done


*** Post Routing Timing Report ***

=== User constraints ===
Fmax report
  User constraint:   8.000MHz, Fmax: 145.033MHz, Clock: PIN_HSE
  User constraint:  10.000MHz, Fmax: 145.033MHz, Clock: PIN_HSI
  User constraint: 240.000MHz, Fmax: 249.314MHz, Clock: pll_inst|auto_generated|pll1|clk[0]
  User constraint: 120.000MHz, Fmax: 106.270MHz, Clock: pll_inst|auto_generated|pll1|clk[3]

Clock transfer report:
  Worst setup: 118.105, with clock PIN_HSE
  Worst setup:  93.105, with clock PIN_HSI
  Worst setup:   0.156, with clock pll_inst|auto_generated|pll1|clk[0]
  Worst setup:  -1.077, with clock pll_inst|auto_generated|pll1|clk[3]
  Worst setup:   3.132, from clock pll_inst|auto_generated|pll1|clk[0] to pll_inst|auto_generated|pll1|clk[3]
  Worst setup:   3.396, from clock pll_inst|auto_generated|pll1|clk[3] to pll_inst|auto_generated|pll1|clk[0]

  Worst  hold:   0.615, with clock PIN_HSE
  Worst  hold:   0.615, with clock PIN_HSI
  Worst  hold:   0.615, with clock pll_inst|auto_generated|pll1|clk[0]
  Worst  hold:   0.606, with clock pll_inst|auto_generated|pll1|clk[3]
  Worst  hold:   1.740, from clock pll_inst|auto_generated|pll1|clk[0] to pll_inst|auto_generated|pll1|clk[3]
  Worst  hold:   0.818, from clock pll_inst|auto_generated|pll1|clk[3] to pll_inst|auto_generated|pll1|clk[0]

=== Auto constraints ===


Coverage report
  User constraints covered 9470 connections out of 9603 total, coverage: 98.6%
  Auto constraints covered 9470 connections out of 9603 total, coverage: 98.6%


Setup from macro_inst|u_uart[0]|u_rx[0]|parity_error to macro_inst|u_uart[0]|u_regs|apb_prdata[1], clock pll_inst|auto_generated|pll1|clk[3], constraint 8.333, skew -0.066, data 9.015
  Slack:  -1.077
    Arrival Time:    9.805
    Required Time:   8.728

*** End Timing Report ***



Tue Jul 15 16:28:19 2025
Generating batch file: {C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/python_dist/python.exe} {C:/Users/zzz17/AgRV_pio/packages/tool-agrv_logic/pio/gen_batch} -d 1075838977 -i 0xbff5105000730062aa234371030002b7 -o ./test_uart_batch.bin --logic-config ./test_uart.bin --logic-address 0x80007000 
> 
> if { [file exists "./${DESIGN}.post.asf"] } {
  alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n"
  source "./${DESIGN}.post.asf"
}
Using post-ASF file test_uart.post.asf.
> # pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
> # pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<
> ##
> 
> date_time
Tue Jul 15 16:28:20 2025
> exit

Total 0 fatals, 0 errors, 2 warnings, 236 infos.