| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| rv32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[5]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[5] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[4]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[4] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[3]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[3] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[2]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[2] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[1]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[1] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[0]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_rx[0] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[5]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[5] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[4]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[4] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[3]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[3] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[2]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[2] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[1]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[1] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[0]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_tx[0] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_regs |
163 |
0 |
19 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1]|u_baud |
25 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[1] |
67 |
24 |
0 |
24 |
63 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[5]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[5] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[4]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[4] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[3]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[3] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[2]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[2] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[1]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[1] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[0]|rx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_rx[0] |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[5]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[5] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[4]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[4] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[3]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[3] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[2]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[2] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[1]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[1] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[0]|tx_fifo |
12 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_tx[0] |
19 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_regs |
163 |
0 |
19 |
0 |
96 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0]|u_baud |
25 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_uart[0] |
67 |
16 |
0 |
16 |
63 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_apb_mux |
119 |
2 |
0 |
2 |
128 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| macro_inst|u_ahb2apb |
98 |
9 |
4 |
9 |
89 |
9 |
9 |
9 |
0 |
0 |
0 |
0 |
0 |
| macro_inst |
133 |
91 |
58 |
91 |
146 |
91 |
91 |
91 |
15 |
0 |
0 |
0 |
0 |
| gclksw_inst |
7 |
1 |
2 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| pll_inst|auto_generated |
3 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |