`timescale 1 ps/ 1 ps

module test_uart(
	GPIO1_0,
	GPIO1_1,
	GPIO1_2,
	GPIO1_3,
	GPIO1_4,
	GPIO1_5,
	GPIO1_6,
	GPIO1_7,
	GPIO2_0,
	GPIO2_1,
	GPIO2_2,
	GPIO2_3,
	GPIO2_4,
	GPIO2_5,
	GPIO2_6,
	GPIO2_7,
	GPIO3_0,
	GPIO3_1,
	GPIO3_2,
	GPIO3_3,
	GPIO3_4,
	GPIO6_0,
	GPIO6_2,
	GPIO6_4,
	GPIO6_6,
	GPIO9_0,
	GPIO9_1,
	GPIO9_2,
	GPIO9_3,
	GPIO9_4,
	GPIO9_5,
	GPIO9_6,
	GPIO9_7,
	PIN_HSE,
	PIN_HSI,
	PIN_OSC,
	SIM_CLK,
	SIM_IO,
	SIM_IO_12,
	SIM_IO_13,
	SIM_IO_15,
	UART3_UARTRXD,
	UART3_UARTTXD,
	UART4_UARTRXD,
	UART4_UARTTXD,
	uart15_rx,
	uart15_tx);
output	GPIO1_0;
output	GPIO1_1;
output	GPIO1_2;
output	GPIO1_3;
output	GPIO1_4;
output	GPIO1_5;
output	GPIO1_6;
output	GPIO1_7;
output	GPIO2_0;
output	GPIO2_1;
output	GPIO2_2;
output	GPIO2_3;
output	GPIO2_4;
output	GPIO2_5;
output	GPIO2_6;
output	GPIO2_7;
input	GPIO3_0;
input	GPIO3_1;
input	GPIO3_2;
input	GPIO3_3;
input	GPIO3_4;
output	GPIO6_0;
output	GPIO6_2;
output	GPIO6_4;
inout	GPIO6_6;
output	GPIO9_0;
inout	GPIO9_1;
output	GPIO9_2;
output	GPIO9_3;
output	GPIO9_4;
output	GPIO9_5;
output	GPIO9_6;
output	GPIO9_7;
input	PIN_HSE;
input	PIN_HSI;
input	PIN_OSC;
output	SIM_CLK;
inout	[11:0] SIM_IO;
inout	SIM_IO_12;
inout	SIM_IO_13;
inout	SIM_IO_15;
input	UART3_UARTRXD;
output	UART3_UARTTXD;
input	UART4_UARTRXD;
output	UART4_UARTTXD;
input	uart15_rx;
output	uart15_tx;

// module alta_rv32
// Design Ports Information

// module hard_block
// Design Ports Information
// ~ALTERA_ASDO_DATA1~	=>  Location: PIN_F4,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_FLASH_nCE_nCSO~	=>  Location: PIN_E2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_DCLK~	=>  Location: PIN_P3,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_DATA0~	=>  Location: PIN_N7,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// ~ALTERA_nCEO~	=>  Location: PIN_P28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA

// module test_uart
// Design Ports Information
// GPIO1_0	=>  Location: PIN_AD17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_1	=>  Location: PIN_AF17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_2	=>  Location: PIN_AE17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_3	=>  Location: PIN_AE19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_4	=>  Location: PIN_AG22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_5	=>  Location: PIN_AH23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_6	=>  Location: PIN_AH22,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO1_7	=>  Location: PIN_AG23,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_0	=>  Location: PIN_AF19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_1	=>  Location: PIN_AF18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_2	=>  Location: PIN_AE18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_3	=>  Location: PIN_AD11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_4	=>  Location: PIN_AE11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_5	=>  Location: PIN_AE12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_6	=>  Location: PIN_AF11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO2_7	=>  Location: PIN_AE13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO6_0	=>  Location: PIN_AH11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO6_2	=>  Location: PIN_AC11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO6_4	=>  Location: PIN_AG11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_0	=>  Location: PIN_AC15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_2	=>  Location: PIN_AF16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_3	=>  Location: PIN_AF24,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_4	=>  Location: PIN_AF20,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_5	=>  Location: PIN_AE15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_6	=>  Location: PIN_AG17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_7	=>  Location: PIN_AH17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// PIN_OSC	=>  Location: PIN_J28,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// SIM_CLK	=>  Location: PIN_AE8,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART3_UARTTXD	=>  Location: PIN_AD15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// UART4_UARTTXD	=>  Location: PIN_AD12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// uart15_tx	=>  Location: PIN_AF13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO6_6	=>  Location: PIN_AG12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO9_1	=>  Location: PIN_AF15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[0]	=>  Location: PIN_AA16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[1]	=>  Location: PIN_AE14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[2]	=>  Location: PIN_AH19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[3]	=>  Location: PIN_AC17,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[4]	=>  Location: PIN_AH21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[5]	=>  Location: PIN_AA15,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[6]	=>  Location: PIN_AH18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[7]	=>  Location: PIN_AB16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[8]	=>  Location: PIN_AG18,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[9]	=>  Location: PIN_AG19,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[10]	=>  Location: PIN_AG21,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO[11]	=>  Location: PIN_AE16,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO_12	=>  Location: PIN_AH12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO_13	=>  Location: PIN_AF14,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// SIM_IO_15	=>  Location: PIN_AB13,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: 8mA
// GPIO3_0	=>  Location: PIN_J27,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO3_1	=>  Location: PIN_AH10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO3_2	=>  Location: PIN_AE10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO3_3	=>  Location: PIN_AG10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// GPIO3_4	=>  Location: PIN_AF12,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// uart15_rx	=>  Location: PIN_AE9,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// UART3_UARTRXD	=>  Location: PIN_AF10,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// UART4_UARTRXD	=>  Location: PIN_AB11,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// PIN_HSI	=>  Location: PIN_Y2,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default
// PIN_HSE	=>  Location: PIN_J1,	 I/O Standard: 3.3-V LVTTL,	 Current Strength: Default

//wire	gnd;
//wire	gnd;
//wire	vcc;
//wire	vcc;
//wire	unknown;
//wire	unknown;
//wire	\GPIO1_0~output_o ;
//wire	\GPIO1_1~output_o ;
//wire	\GPIO1_2~output_o ;
//wire	\GPIO1_3~output_o ;
//wire	\GPIO1_4~output_o ;
//wire	\GPIO1_5~output_o ;
//wire	\GPIO1_6~output_o ;
//wire	\GPIO1_7~output_o ;
//wire	\GPIO2_0~output_o ;
//wire	\GPIO2_1~output_o ;
//wire	\GPIO2_2~output_o ;
//wire	\GPIO2_3~output_o ;
//wire	\GPIO2_4~output_o ;
//wire	\GPIO2_5~output_o ;
//wire	\GPIO2_6~output_o ;
//wire	\GPIO2_7~output_o ;
wire	\GPIO3_0~input_o ;
wire	\GPIO3_1~input_o ;
wire	\GPIO3_2~input_o ;
wire	\GPIO3_3~input_o ;
wire	\GPIO3_4~input_o ;
//wire	\GPIO6_0~output_o ;
//wire	\GPIO6_2~output_o ;
//wire	\GPIO6_4~output_o ;
//wire	\GPIO6_6~output_o ;
wire	\GPIO6_6~input_o ;
//wire	\GPIO9_0~output_o ;
//wire	\GPIO9_1~output_o ;
wire	\GPIO9_1~input_o ;
//wire	\GPIO9_2~output_o ;
//wire	\GPIO9_3~output_o ;
//wire	\GPIO9_4~output_o ;
//wire	\GPIO9_5~output_o ;
//wire	\GPIO9_6~output_o ;
//wire	\GPIO9_7~output_o ;
//wire	hbi_7_0_4730eacd893fc1ea_bp;
wire	\PIN_HSE~input_o ;
//wire	hbi_69_0_9cb2c0024f9919c5_bp;
wire	\PIN_HSI~input_o ;
wire	\PIN_OSC~input_o ;
wire	\PLL_ENABLE~clkctrl_outclk ;
//wire	hbi_71_0_4730eacd893fc1ea_bp;
wire	\PLL_ENABLE~combout ;
wire	\PLL_LOCK~combout ;
//wire	\SIM_CLK~output_o ;
//wire	\SIM_IO[0]~output_o ;
wire	\SIM_IO[0]~input_o ;
//wire	\SIM_IO[10]~output_o ;
wire	\SIM_IO[10]~input_o ;
//wire	\SIM_IO[11]~output_o ;
wire	\SIM_IO[11]~input_o ;
//wire	\SIM_IO[1]~output_o ;
wire	\SIM_IO[1]~input_o ;
//wire	\SIM_IO[2]~output_o ;
wire	\SIM_IO[2]~input_o ;
//wire	\SIM_IO[3]~output_o ;
wire	\SIM_IO[3]~input_o ;
//wire	\SIM_IO[4]~output_o ;
wire	\SIM_IO[4]~input_o ;
//wire	\SIM_IO[5]~output_o ;
wire	\SIM_IO[5]~input_o ;
//wire	\SIM_IO[6]~output_o ;
wire	\SIM_IO[6]~input_o ;
//wire	\SIM_IO[7]~output_o ;
wire	\SIM_IO[7]~input_o ;
//wire	\SIM_IO[8]~output_o ;
wire	\SIM_IO[8]~input_o ;
//wire	\SIM_IO[9]~output_o ;
wire	\SIM_IO[9]~input_o ;
//wire	\SIM_IO_12~output_o ;
wire	\SIM_IO_12~input_o ;
//wire	\SIM_IO_13~output_o ;
wire	\SIM_IO_13~input_o ;
//wire	\SIM_IO_15~output_o ;
wire	\SIM_IO_15~input_o ;
wire	\UART3_UARTRXD~input_o ;
//wire	\UART3_UARTTXD~output_o ;
wire	\UART4_UARTRXD~input_o ;
//wire	\UART4_UARTTXD~output_o ;
//wire	hbo_13_1797ab7b230f061a_bp;
//wire	\pll_inst|auto_generated|pll1~LOCKED ;
wire	\auto_generated_inst.hbo_13_1797ab7b230f061a_bp ;
//wire	hbo_22_717df45ba12dbb20_bp;
//wire	bus_clk;
wire	\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ;
//wire	hbo_22_f9ff3d300b43c0f2_bp;
//wire	\gclksw_inst|clkout ;
wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ;
//wire	devclrn;
tri1	devclrn;
//wire	devoe;
tri1	devoe;
//wire	devpor;
tri1	devpor;
wire	[7:0] gpio3_io_in;
//wire	gpio3_io_in[5];
//wire	gpio3_io_in[6];
//wire	gpio3_io_in[7];
wire	[7:0] gpio4_io_in;
//wire	gpio4_io_in[6];
//wire	gpio4_io_in[7];
wire	[7:0] gpio5_io_in;
//wire	gpio5_io_in[6];
//wire	gpio5_io_in[7];
wire	[7:0] gpio6_io_in;
//wire	gpio6_io_in[0];
//wire	gpio6_io_in[1];
//wire	gpio6_io_in[2];
//wire	gpio6_io_in[3];
//wire	gpio6_io_in[4];
//wire	gpio6_io_in[5];
wire	[7:0] gpio6_io_out_data;
//wire	gpio6_io_out_data[1];
//wire	gpio6_io_out_data[3];
//wire	gpio6_io_out_data[5];
//wire	gpio6_io_out_data[7];
wire	[7:0] gpio6_io_out_en;
//wire	gpio6_io_out_en[1];
//wire	gpio6_io_out_en[3];
//wire	gpio6_io_out_en[5];
//wire	gpio6_io_out_en[7];
wire	[7:0] gpio7_io_in;
//wire	gpio7_io_in[0];
//wire	gpio7_io_in[2];
//wire	gpio7_io_in[3];
//wire	gpio7_io_in[4];
//wire	gpio7_io_in[5];
//wire	gpio7_io_in[6];
//wire	gpio7_io_in[7];
wire	[7:0] gpio7_io_out_data;
//wire	gpio7_io_out_data[0];
//wire	gpio7_io_out_data[1];
//wire	gpio7_io_out_data[2];
//wire	gpio7_io_out_data[3];
//wire	gpio7_io_out_data[4];
//wire	gpio7_io_out_data[5];
//wire	gpio7_io_out_data[7];
wire	[7:0] gpio7_io_out_en;
//wire	gpio7_io_out_en[0];
//wire	gpio7_io_out_en[1];
//wire	gpio7_io_out_en[2];
//wire	gpio7_io_out_en[3];
//wire	gpio7_io_out_en[4];
//wire	gpio7_io_out_en[5];
//wire	gpio7_io_out_en[7];
wire	[7:0] gpio8_io_out_data;
//wire	gpio8_io_out_data[5];
wire	[7:0] gpio8_io_out_en;
//wire	gpio8_io_out_en[5];
//wire	gpio8_io_out_en[7];
wire	[7:0] gpio9_io_in;
//wire	gpio9_io_in[0];
//wire	gpio9_io_in[2];
//wire	gpio9_io_in[3];
//wire	gpio9_io_in[4];
//wire	gpio9_io_in[5];
//wire	gpio9_io_in[6];
//wire	gpio9_io_in[7];
wire	\macro_inst|LessThan0~0_combout ;
wire	\macro_inst|LessThan0~1_combout ;
wire	\macro_inst|LessThan0~2_combout ;
wire	\macro_inst|SIM_IO_12~1_combout ;
wire	\macro_inst|SIM_IO_13~1_combout ;
wire	\macro_inst|SIM_IO_15~1_combout ;
wire	[7:0] \macro_inst|sim_clk_cnt ;
//wire	\macro_inst|sim_clk_cnt [0];
wire	\macro_inst|sim_clk_cnt[0]~8_combout ;
wire	\macro_inst|sim_clk_cnt[0]~9 ;
//wire	\macro_inst|sim_clk_cnt [1];
wire	\macro_inst|sim_clk_cnt[1]~10_combout ;
wire	\macro_inst|sim_clk_cnt[1]~11 ;
//wire	\macro_inst|sim_clk_cnt [2];
wire	\macro_inst|sim_clk_cnt[2]~12_combout ;
wire	\macro_inst|sim_clk_cnt[2]~13 ;
//wire	\macro_inst|sim_clk_cnt [3];
wire	\macro_inst|sim_clk_cnt[3]~14_combout ;
wire	\macro_inst|sim_clk_cnt[3]~15 ;
//wire	\macro_inst|sim_clk_cnt [4];
wire	\macro_inst|sim_clk_cnt[4]~16_combout ;
wire	\macro_inst|sim_clk_cnt[4]~17 ;
//wire	\macro_inst|sim_clk_cnt [5];
wire	\macro_inst|sim_clk_cnt[5]~18_combout ;
wire	\macro_inst|sim_clk_cnt[5]~19 ;
//wire	\macro_inst|sim_clk_cnt [6];
wire	\macro_inst|sim_clk_cnt[6]~20_combout ;
wire	\macro_inst|sim_clk_cnt[6]~21 ;
//wire	\macro_inst|sim_clk_cnt [7];
wire	\macro_inst|sim_clk_cnt[7]~22_combout ;
wire	\macro_inst|sim_clk_reg~0_combout ;
wire	\macro_inst|sim_clk_reg~q ;
wire	\macro_inst|u_ahb2apb|Selector0~0_combout ;
wire	\macro_inst|u_ahb2apb|Selector22~0_combout ;
wire	\macro_inst|u_ahb2apb|Selector2~0_combout ;
wire	\macro_inst|u_ahb2apb|always0~0_combout ;
wire	\macro_inst|u_ahb2apb|always2~0_combout ;
wire	\macro_inst|u_ahb2apb|apbState.apbAccess~q ;
wire	\macro_inst|u_ahb2apb|apbState.apbIdle~q ;
wire	\macro_inst|u_ahb2apb|apbState.apbSetup~q ;
wire	\macro_inst|u_ahb2apb|apb_pdone~combout ;
wire	[12:0] \macro_inst|u_ahb2apb|haddr ;
//wire	\macro_inst|u_ahb2apb|haddr [0];
//wire	\macro_inst|u_ahb2apb|haddr [10];
//wire	\macro_inst|u_ahb2apb|haddr [11];
//wire	\macro_inst|u_ahb2apb|haddr [12];
//wire	\macro_inst|u_ahb2apb|haddr [1];
//wire	\macro_inst|u_ahb2apb|haddr [2];
//wire	\macro_inst|u_ahb2apb|haddr [3];
//wire	\macro_inst|u_ahb2apb|haddr [4];
//wire	\macro_inst|u_ahb2apb|haddr [5];
//wire	\macro_inst|u_ahb2apb|haddr [6];
//wire	\macro_inst|u_ahb2apb|haddr [7];
//wire	\macro_inst|u_ahb2apb|haddr [8];
//wire	\macro_inst|u_ahb2apb|haddr [9];
wire	\macro_inst|u_ahb2apb|hdone~0_combout ;
wire	\macro_inst|u_ahb2apb|hdone~q ;
wire	\macro_inst|u_ahb2apb|hreadyout~0_combout ;
wire	\macro_inst|u_ahb2apb|hreadyout~q ;
wire	\macro_inst|u_ahb2apb|hwrite~q ;
wire	[12:0] \macro_inst|u_ahb2apb|paddr ;
//wire	\macro_inst|u_ahb2apb|paddr [0];
//wire	\macro_inst|u_ahb2apb|paddr [10];
//wire	\macro_inst|u_ahb2apb|paddr [11];
//wire	\macro_inst|u_ahb2apb|paddr [12];
//wire	\macro_inst|u_ahb2apb|paddr [1];
//wire	\macro_inst|u_ahb2apb|paddr [2];
//wire	\macro_inst|u_ahb2apb|paddr [3];
//wire	\macro_inst|u_ahb2apb|paddr [4];
//wire	\macro_inst|u_ahb2apb|paddr [5];
//wire	\macro_inst|u_ahb2apb|paddr [6];
//wire	\macro_inst|u_ahb2apb|paddr [7];
//wire	\macro_inst|u_ahb2apb|paddr [8];
//wire	\macro_inst|u_ahb2apb|paddr [9];
wire	\macro_inst|u_ahb2apb|pdone~0_combout ;
wire	\macro_inst|u_ahb2apb|pdone~q ;
wire	\macro_inst|u_ahb2apb|penable~q ;
wire	[31:0] \macro_inst|u_ahb2apb|prdata ;
//wire	\macro_inst|u_ahb2apb|prdata [0];
//wire	\macro_inst|u_ahb2apb|prdata [10];
//wire	\macro_inst|u_ahb2apb|prdata [11];
//wire	\macro_inst|u_ahb2apb|prdata [12];
//wire	\macro_inst|u_ahb2apb|prdata [13];
//wire	\macro_inst|u_ahb2apb|prdata [14];
//wire	\macro_inst|u_ahb2apb|prdata [15];
//wire	\macro_inst|u_ahb2apb|prdata [16];
//wire	\macro_inst|u_ahb2apb|prdata [17];
//wire	\macro_inst|u_ahb2apb|prdata [18];
//wire	\macro_inst|u_ahb2apb|prdata [19];
//wire	\macro_inst|u_ahb2apb|prdata [1];
//wire	\macro_inst|u_ahb2apb|prdata [20];
//wire	\macro_inst|u_ahb2apb|prdata [21];
//wire	\macro_inst|u_ahb2apb|prdata [22];
//wire	\macro_inst|u_ahb2apb|prdata [23];
//wire	\macro_inst|u_ahb2apb|prdata [24];
//wire	\macro_inst|u_ahb2apb|prdata [25];
//wire	\macro_inst|u_ahb2apb|prdata [26];
//wire	\macro_inst|u_ahb2apb|prdata [27];
//wire	\macro_inst|u_ahb2apb|prdata [28];
//wire	\macro_inst|u_ahb2apb|prdata [29];
//wire	\macro_inst|u_ahb2apb|prdata [2];
//wire	\macro_inst|u_ahb2apb|prdata [30];
//wire	\macro_inst|u_ahb2apb|prdata [31];
//wire	\macro_inst|u_ahb2apb|prdata [3];
//wire	\macro_inst|u_ahb2apb|prdata [4];
//wire	\macro_inst|u_ahb2apb|prdata [5];
//wire	\macro_inst|u_ahb2apb|prdata [6];
//wire	\macro_inst|u_ahb2apb|prdata [7];
//wire	\macro_inst|u_ahb2apb|prdata [8];
//wire	\macro_inst|u_ahb2apb|prdata [9];
wire	\macro_inst|u_ahb2apb|psel~0_combout ;
wire	\macro_inst|u_ahb2apb|psel~1_combout ;
wire	\macro_inst|u_ahb2apb|psel~q ;
wire	\macro_inst|u_ahb2apb|pvalid~q ;
wire	\macro_inst|u_ahb2apb|pwrite~0_combout ;
wire	\macro_inst|u_ahb2apb|pwrite~q ;
wire	\macro_inst|u_apb_mux|always0~0_combout ;
wire	[31:0] \macro_inst|u_apb_mux|apb_in_prdata ;
//wire	\macro_inst|u_apb_mux|apb_in_prdata [0];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [10];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [11];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [12];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [13];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [14];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [15];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [16];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [17];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [18];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [19];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [1];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [20];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [21];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [22];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [23];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [24];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [25];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [26];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [27];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [28];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [29];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [2];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [30];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [31];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [3];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [4];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [5];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [6];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [7];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [8];
//wire	\macro_inst|u_apb_mux|apb_in_prdata [9];
wire	\macro_inst|u_apb_mux|apb_in_pready~0_combout ;
wire	[1:0] \macro_inst|u_apb_mux|pr_select ;
//wire	\macro_inst|u_apb_mux|pr_select [0];
wire	\macro_inst|u_apb_mux|pr_select[0]~0_combout ;
//wire	\macro_inst|u_apb_mux|pr_select [1];
wire	\macro_inst|u_apb_mux|pr_select[1]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_baud|Equal1~0_combout ;
wire	\macro_inst|u_uart[0]|u_baud|Equal1~1_combout ;
wire	\macro_inst|u_uart[0]|u_baud|Equal1~2_combout ;
wire	\macro_inst|u_uart[0]|u_baud|Equal1~3_combout ;
wire	\macro_inst|u_uart[0]|u_baud|Equal1~4_combout ;
wire	\macro_inst|u_uart[0]|u_baud|LessThan0~10_combout ;
wire	\macro_inst|u_uart[0]|u_baud|LessThan0~1_cout ;
wire	\macro_inst|u_uart[0]|u_baud|LessThan0~3_cout ;
wire	\macro_inst|u_uart[0]|u_baud|LessThan0~5_cout ;
wire	\macro_inst|u_uart[0]|u_baud|LessThan0~7_cout ;
wire	\macro_inst|u_uart[0]|u_baud|LessThan0~9_cout ;
wire	\macro_inst|u_uart[0]|u_baud|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_baud|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_baud|baud16~q ;
wire	[5:0] \macro_inst|u_uart[0]|u_baud|f_cnt ;
//wire	\macro_inst|u_uart[0]|u_baud|f_cnt [0];
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[0]~6_combout ;
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[0]~7 ;
//wire	\macro_inst|u_uart[0]|u_baud|f_cnt [1];
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[1]~8_combout ;
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[1]~9 ;
//wire	\macro_inst|u_uart[0]|u_baud|f_cnt [2];
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[2]~10_combout ;
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[2]~11 ;
//wire	\macro_inst|u_uart[0]|u_baud|f_cnt [3];
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[3]~12_combout ;
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[3]~13 ;
//wire	\macro_inst|u_uart[0]|u_baud|f_cnt [4];
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[4]~14_combout ;
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[4]~15 ;
//wire	\macro_inst|u_uart[0]|u_baud|f_cnt [5];
wire	\macro_inst|u_uart[0]|u_baud|f_cnt[5]~16_combout ;
wire	\macro_inst|u_uart[0]|u_baud|f_del~q ;
wire	[15:0] \macro_inst|u_uart[0]|u_baud|i_cnt ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [0];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[0]~16_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[0]~17 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [10];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[10]~36_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[10]~37 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [11];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[11]~38_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[11]~39 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [12];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[12]~40_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[12]~41 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [13];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[13]~42_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[13]~43 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [14];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[14]~44_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[14]~45 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [15];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[15]~46_combout ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [1];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[1]~18_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[1]~19 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [2];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[2]~20_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[2]~21 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [3];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[3]~22_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[3]~23 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [4];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[4]~24_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[4]~25 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [5];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[5]~26_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[5]~27 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [6];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[6]~28_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[6]~29 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [7];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[7]~30_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[7]~31 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [8];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[8]~32_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[8]~33 ;
//wire	\macro_inst|u_uart[0]|u_baud|i_cnt [9];
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[9]~34_combout ;
wire	\macro_inst|u_uart[0]|u_baud|i_cnt[9]~35 ;
wire	\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Decoder1~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux0~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux0~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux0~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux0~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux10~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux10~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux11~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux11~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux11~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux11~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux12~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux12~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux1~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux1~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux1~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux1~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux2~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux2~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux2~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux2~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux3~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux3~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux3~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux3~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux4~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux4~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux4~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux4~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux5~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux5~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux5~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux5~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux6~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux6~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux6~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux6~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux7~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux7~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux7~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux7~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Mux8~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector0~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector0~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector0~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector0~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector10~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~13_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector11~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector12~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector1~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector1~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector1~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector1~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector1~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector2~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector2~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector3~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector3~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector3~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector5~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector6~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector6~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector6~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector6~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~13_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~14_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~15_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~16_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~17_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~18_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector7~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector8~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|Selector9~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|always1~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|always5~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|always5~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|always7~0_combout ;
wire	[31:0] \macro_inst|u_uart[0]|u_regs|apb_prdata ;
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [0];
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [10];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [11];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [12];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [13];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [14];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [15];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [16];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [17];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [18];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [19];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [1];
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [20];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [21];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [22];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [23];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [24];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [25];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [26];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [27];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [28];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [29];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [2];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [30];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [31];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [3];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [4];
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [5];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [6];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [7];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [8];
//wire	\macro_inst|u_uart[0]|u_regs|apb_prdata [9];
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata~19_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata~20_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_prdata~21_combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_pready~q ;
wire	\macro_inst|u_uart[0]|u_regs|apb_read0~combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_read1~combout ;
wire	\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ;
wire	[5:0] \macro_inst|u_uart[0]|u_regs|break_error_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|break_error_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|break_error_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|break_error_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|break_error_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|break_error_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|break_error_ie [5];
wire	\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ;
wire	\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ;
wire	\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ;
wire	\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ;
wire	\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ;
wire	[5:0] \macro_inst|u_uart[0]|u_regs|fbrd ;
//wire	\macro_inst|u_uart[0]|u_regs|fbrd [0];
//wire	\macro_inst|u_uart[0]|u_regs|fbrd [1];
//wire	\macro_inst|u_uart[0]|u_regs|fbrd [2];
//wire	\macro_inst|u_uart[0]|u_regs|fbrd [3];
//wire	\macro_inst|u_uart[0]|u_regs|fbrd [4];
//wire	\macro_inst|u_uart[0]|u_regs|fbrd [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|framing_error_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|framing_error_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|framing_error_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|framing_error_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|framing_error_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|framing_error_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|framing_error_ie [5];
wire	[15:0] \macro_inst|u_uart[0]|u_regs|ibrd ;
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [0];
wire	\macro_inst|u_uart[0]|u_regs|ibrd[0]~_wirecell_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [10];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [11];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [12];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [13];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [14];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [15];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [1];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [2];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [3];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [4];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [5];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [6];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [7];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [8];
//wire	\macro_inst|u_uart[0]|u_regs|ibrd [9];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|interrupts ;
//wire	\macro_inst|u_uart[0]|u_regs|interrupts [0];
//wire	\macro_inst|u_uart[0]|u_regs|interrupts [1];
//wire	\macro_inst|u_uart[0]|u_regs|interrupts [2];
//wire	\macro_inst|u_uart[0]|u_regs|interrupts [3];
//wire	\macro_inst|u_uart[0]|u_regs|interrupts [4];
//wire	\macro_inst|u_uart[0]|u_regs|interrupts [5];
wire	\macro_inst|u_uart[0]|u_regs|interrupts~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~10_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~11_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~13_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~14_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~15_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~16_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~17_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~18_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~19_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~20_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~21_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~22_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~23_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~24_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~25_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~26_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~27_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~28_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~29_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~6_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~7_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~8_combout ;
wire	\macro_inst|u_uart[0]|u_regs|interrupts~9_combout ;
wire	\macro_inst|u_uart[0]|u_regs|lcr_eps~q ;
wire	\macro_inst|u_uart[0]|u_regs|lcr_pen~q ;
wire	\macro_inst|u_uart[0]|u_regs|lcr_sps~q ;
wire	\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ;
wire	[5:0] \macro_inst|u_uart[0]|u_regs|overrun_error_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|overrun_error_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|overrun_error_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|overrun_error_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|overrun_error_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|overrun_error_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|overrun_error_ie [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|parity_error_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|parity_error_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|parity_error_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|parity_error_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|parity_error_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|parity_error_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|parity_error_ie [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|rx_dma_en ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en [0];
wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en [1];
wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en [2];
wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en [3];
wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en [4];
wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en [5];
wire	\macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2_combout ;
wire	[5:0] \macro_inst|u_uart[0]|u_regs|rx_idle_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_idle_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|rx_idle_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|rx_idle_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|rx_idle_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|rx_idle_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|rx_idle_ie [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [0];
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [1];
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [2];
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [3];
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [4];
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [5];
wire	\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout ;
wire	[5:0] \macro_inst|u_uart[0]|u_regs|rx_read ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_read [0];
//wire	\macro_inst|u_uart[0]|u_regs|rx_read [1];
//wire	\macro_inst|u_uart[0]|u_regs|rx_read [2];
//wire	\macro_inst|u_uart[0]|u_regs|rx_read [3];
//wire	\macro_inst|u_uart[0]|u_regs|rx_read [4];
//wire	\macro_inst|u_uart[0]|u_regs|rx_read [5];
wire	\macro_inst|u_uart[0]|u_regs|rx_read~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_read~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_read~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_read~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_read~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|rx_read~5_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_regs|rx_reg ;
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [0];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [1];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [2];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [3];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [4];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [5];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [6];
//wire	\macro_inst|u_uart[0]|u_regs|rx_reg [7];
wire	[4:0] \macro_inst|u_uart[0]|u_regs|status_reg ;
//wire	\macro_inst|u_uart[0]|u_regs|status_reg [0];
wire	\macro_inst|u_uart[0]|u_regs|status_reg[0]~0_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|status_reg [1];
//wire	\macro_inst|u_uart[0]|u_regs|status_reg [2];
wire	\macro_inst|u_uart[0]|u_regs|status_reg[2]~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|status_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_regs|status_reg [3];
//wire	\macro_inst|u_uart[0]|u_regs|status_reg [4];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|tx_complete_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|tx_complete_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|tx_complete_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|tx_complete_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|tx_complete_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|tx_complete_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|tx_complete_ie [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|tx_dma_en ;
//wire	\macro_inst|u_uart[0]|u_regs|tx_dma_en [0];
//wire	\macro_inst|u_uart[0]|u_regs|tx_dma_en [1];
//wire	\macro_inst|u_uart[0]|u_regs|tx_dma_en [2];
//wire	\macro_inst|u_uart[0]|u_regs|tx_dma_en [3];
//wire	\macro_inst|u_uart[0]|u_regs|tx_dma_en [4];
//wire	\macro_inst|u_uart[0]|u_regs|tx_dma_en [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|tx_not_full_ie ;
//wire	\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [0];
//wire	\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [1];
//wire	\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [2];
//wire	\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [3];
//wire	\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [4];
//wire	\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [5];
wire	[5:0] \macro_inst|u_uart[0]|u_regs|tx_write ;
//wire	\macro_inst|u_uart[0]|u_regs|tx_write [0];
//wire	\macro_inst|u_uart[0]|u_regs|tx_write [1];
//wire	\macro_inst|u_uart[0]|u_regs|tx_write [2];
//wire	\macro_inst|u_uart[0]|u_regs|tx_write [3];
//wire	\macro_inst|u_uart[0]|u_regs|tx_write [4];
//wire	\macro_inst|u_uart[0]|u_regs|tx_write [5];
wire	\macro_inst|u_uart[0]|u_regs|tx_write~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|tx_write~1_combout ;
wire	\macro_inst|u_uart[0]|u_regs|tx_write~2_combout ;
wire	\macro_inst|u_uart[0]|u_regs|tx_write~3_combout ;
wire	\macro_inst|u_uart[0]|u_regs|tx_write~4_combout ;
wire	\macro_inst|u_uart[0]|u_regs|tx_write~5_combout ;
wire	\macro_inst|u_uart[0]|u_regs|uart_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_regs|uart_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Add4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Add4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Add4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector1~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector1~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector1~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always11~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always11~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always11~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always3~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|always8~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|break_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|break_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|framing_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|framing_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|overrun_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|parity_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|parity_error~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~q ;
wire	[0:0] \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[0]|u_rx[0]|rx_in ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_in [0];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_in [1];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_in [2];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_in [3];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_in [4];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_parity~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Add4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Add4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Add4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector0~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector0~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector0~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always11~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always11~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always11~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always3~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|always8~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|break_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|break_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|framing_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|framing_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|overrun_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|parity_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|parity_error~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~q ;
wire	[0:0] \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[0]|u_rx[1]|rx_in ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_in [0];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_in [1];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_in [2];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_in [3];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_in [4];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_parity~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [1];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [2];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [3];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [5];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [6];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Add4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Add4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Add4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector2~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector2~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector2~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector2~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|Selector4~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always11~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always11~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always11~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always3~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|always8~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|break_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|break_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|framing_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|framing_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|overrun_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|parity_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|parity_error~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[0]|u_rx[2]|rx_in ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_in [0];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_in [1];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_in [2];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_in [3];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_in [4];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_parity~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [2];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [3];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [4];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Add4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Add4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Add4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector2~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector2~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector2~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector2~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|Selector4~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always11~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always11~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always11~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always3~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|always8~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|break_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|break_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|framing_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|framing_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|overrun_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|parity_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|parity_error~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[0]|u_rx[3]|rx_in ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_in [0];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_in [1];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_in [2];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_in [3];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_in [4];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_parity~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Add4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Add4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Add4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector2~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector2~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector2~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector2~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|Selector4~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always11~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always11~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always11~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always3~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|always8~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|break_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|break_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|framing_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|framing_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|overrun_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|parity_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|parity_error~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[0]|u_rx[4]|rx_in ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in [0];
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in [1];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in[1]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in [2];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in[2]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in [3];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in[3]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in [4];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_parity~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [1];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [2];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [4];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [5];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [6];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6]~feeder_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Add4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Add4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Add4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector0~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector0~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector0~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector1~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector2~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~3_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~5_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|Selector4~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always11~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always11~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always11~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always2~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always3~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always4~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|always8~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|break_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|break_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|framing_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|framing_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|overrun_error~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|parity_error~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|parity_error~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [3];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~feeder_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[0]|u_rx[5]|rx_in ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_in [0];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_in [1];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_in [2];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_in [3];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_in [4];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_parity~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector5~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector5~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~q ;
wire	[0:0] \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [2];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout ;
wire	\macro_inst|u_uart[0]|u_tx[0]|uart_txd~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector5~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector5~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~q ;
wire	[0:0] \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout ;
wire	\macro_inst|u_uart[0]|u_tx[1]|uart_txd~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector5~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector5~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [5];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout ;
wire	\macro_inst|u_uart[0]|u_tx[2]|uart_txd~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector5~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector5~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [3];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout ;
wire	\macro_inst|u_uart[0]|u_tx[3]|uart_txd~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector5~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector5~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [3];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout ;
wire	\macro_inst|u_uart[0]|u_tx[4]|uart_txd~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector2~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector3~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector3~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector4~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector4~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector5~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector5~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|Selector5~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|always0~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|always6~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|always6~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [0];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [2];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [5];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout ;
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [7];
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout ;
wire	\macro_inst|u_uart[0]|u_tx[5]|uart_txd~q ;
wire	\macro_inst|u_uart[1]|u_baud|Equal1~0_combout ;
wire	\macro_inst|u_uart[1]|u_baud|Equal1~1_combout ;
wire	\macro_inst|u_uart[1]|u_baud|Equal1~2_combout ;
wire	\macro_inst|u_uart[1]|u_baud|Equal1~3_combout ;
wire	\macro_inst|u_uart[1]|u_baud|Equal1~4_combout ;
wire	\macro_inst|u_uart[1]|u_baud|LessThan0~10_combout ;
wire	\macro_inst|u_uart[1]|u_baud|LessThan0~1_cout ;
wire	\macro_inst|u_uart[1]|u_baud|LessThan0~3_cout ;
wire	\macro_inst|u_uart[1]|u_baud|LessThan0~5_cout ;
wire	\macro_inst|u_uart[1]|u_baud|LessThan0~7_cout ;
wire	\macro_inst|u_uart[1]|u_baud|LessThan0~9_cout ;
wire	\macro_inst|u_uart[1]|u_baud|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_baud|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_baud|baud16~q ;
wire	[5:0] \macro_inst|u_uart[1]|u_baud|f_cnt ;
//wire	\macro_inst|u_uart[1]|u_baud|f_cnt [0];
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[0]~6_combout ;
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[0]~7 ;
//wire	\macro_inst|u_uart[1]|u_baud|f_cnt [1];
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[1]~8_combout ;
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[1]~9 ;
//wire	\macro_inst|u_uart[1]|u_baud|f_cnt [2];
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[2]~10_combout ;
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[2]~11 ;
//wire	\macro_inst|u_uart[1]|u_baud|f_cnt [3];
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[3]~12_combout ;
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[3]~13 ;
//wire	\macro_inst|u_uart[1]|u_baud|f_cnt [4];
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[4]~14_combout ;
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[4]~15 ;
//wire	\macro_inst|u_uart[1]|u_baud|f_cnt [5];
wire	\macro_inst|u_uart[1]|u_baud|f_cnt[5]~16_combout ;
wire	\macro_inst|u_uart[1]|u_baud|f_del~q ;
wire	[15:0] \macro_inst|u_uart[1]|u_baud|i_cnt ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [0];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[0]~16_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[0]~17 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [10];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[10]~36_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[10]~37 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [11];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[11]~38_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[11]~39 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [12];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[12]~40_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[12]~41 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [13];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[13]~42_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[13]~43 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [14];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[14]~44_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[14]~45 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [15];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[15]~46_combout ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [1];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[1]~18_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[1]~19 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [2];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[2]~20_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[2]~21 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [3];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[3]~22_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[3]~23 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [4];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[4]~24_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[4]~25 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [5];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[5]~26_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[5]~27 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [6];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[6]~28_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[6]~29 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [7];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[7]~30_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[7]~31 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [8];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[8]~32_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[8]~33 ;
//wire	\macro_inst|u_uart[1]|u_baud|i_cnt [9];
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[9]~34_combout ;
wire	\macro_inst|u_uart[1]|u_baud|i_cnt[9]~35 ;
wire	\macro_inst|u_uart[1]|u_regs|Equal2~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux0~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux0~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux0~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux0~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux10~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux10~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux11~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux11~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux11~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux11~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux12~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux12~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux1~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux1~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux1~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux1~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux2~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux2~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux2~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux2~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux3~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux3~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux3~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux3~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux4~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux4~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux4~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux4~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux5~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux5~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux5~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux5~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux6~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux6~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux6~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux6~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux7~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux7~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux7~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux7~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Mux8~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector0~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector0~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector0~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector0~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector10~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~10_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~12_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~13_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~14_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~15_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector11~9_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~10_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector12~9_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector1~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector1~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector1~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector1~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector2~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector2~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector3~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector3~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector3~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~10_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector5~9_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector6~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector6~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~10_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~12_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~13_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~14_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~15_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector7~9_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~10_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~12_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~13_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~14_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~15_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector8~9_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|Selector9~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|always1~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|always5~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|always7~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|always8~1_combout ;
wire	[31:0] \macro_inst|u_uart[1]|u_regs|apb_prdata ;
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [0];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [10];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [11];
wire	\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [12];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [13];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [14];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [15];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [16];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [17];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [18];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [19];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [1];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [20];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [21];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [22];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [23];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [24];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [25];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [26];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [27];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [28];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [29];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [2];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [30];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [31];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [3];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [4];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [5];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [6];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [7];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [8];
//wire	\macro_inst|u_uart[1]|u_regs|apb_prdata [9];
wire	\macro_inst|u_uart[1]|u_regs|apb_prdata~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_prdata~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_prdata~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_pready~q ;
wire	\macro_inst|u_uart[1]|u_regs|apb_read0~combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_read1~combout ;
wire	\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ;
wire	[5:0] \macro_inst|u_uart[1]|u_regs|break_error_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|break_error_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|break_error_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|break_error_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|break_error_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|break_error_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|break_error_ie [5];
wire	\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ;
wire	\macro_inst|u_uart[1]|u_regs|clear_flags[1]~13_combout ;
wire	\macro_inst|u_uart[1]|u_regs|clear_flags[2]~14_combout ;
wire	\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ;
wire	\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ;
wire	\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ;
wire	[5:0] \macro_inst|u_uart[1]|u_regs|fbrd ;
//wire	\macro_inst|u_uart[1]|u_regs|fbrd [0];
//wire	\macro_inst|u_uart[1]|u_regs|fbrd [1];
//wire	\macro_inst|u_uart[1]|u_regs|fbrd [2];
//wire	\macro_inst|u_uart[1]|u_regs|fbrd [3];
//wire	\macro_inst|u_uart[1]|u_regs|fbrd [4];
//wire	\macro_inst|u_uart[1]|u_regs|fbrd [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|framing_error_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|framing_error_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|framing_error_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|framing_error_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|framing_error_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|framing_error_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|framing_error_ie [5];
wire	[15:0] \macro_inst|u_uart[1]|u_regs|ibrd ;
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [0];
wire	\macro_inst|u_uart[1]|u_regs|ibrd[0]~_wirecell_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [10];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [11];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [12];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [13];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [14];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [15];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [1];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [2];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [3];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [4];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [5];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [6];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [7];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [8];
//wire	\macro_inst|u_uart[1]|u_regs|ibrd [9];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|interrupts ;
//wire	\macro_inst|u_uart[1]|u_regs|interrupts [0];
//wire	\macro_inst|u_uart[1]|u_regs|interrupts [1];
//wire	\macro_inst|u_uart[1]|u_regs|interrupts [2];
//wire	\macro_inst|u_uart[1]|u_regs|interrupts [3];
//wire	\macro_inst|u_uart[1]|u_regs|interrupts [4];
//wire	\macro_inst|u_uart[1]|u_regs|interrupts [5];
wire	\macro_inst|u_uart[1]|u_regs|interrupts~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~10_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~12_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~13_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~14_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~15_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~16_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~17_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~18_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~19_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~20_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~21_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~22_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~23_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~24_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~25_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~26_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~27_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~28_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~29_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~6_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~7_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~8_combout ;
wire	\macro_inst|u_uart[1]|u_regs|interrupts~9_combout ;
wire	\macro_inst|u_uart[1]|u_regs|lcr_eps~q ;
wire	\macro_inst|u_uart[1]|u_regs|lcr_pen~q ;
wire	\macro_inst|u_uart[1]|u_regs|lcr_sps~q ;
wire	\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ;
wire	[5:0] \macro_inst|u_uart[1]|u_regs|overrun_error_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|overrun_error_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|overrun_error_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|overrun_error_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|overrun_error_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|overrun_error_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|overrun_error_ie [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|parity_error_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|parity_error_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|parity_error_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|parity_error_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|parity_error_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|parity_error_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|parity_error_ie [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|rx_dma_en ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en [0];
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en [1];
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en [2];
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en [3];
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en [4];
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en [5];
wire	\macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0_combout ;
wire	[5:0] \macro_inst|u_uart[1]|u_regs|rx_idle_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_idle_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|rx_idle_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|rx_idle_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|rx_idle_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|rx_idle_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|rx_idle_ie [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [0];
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [1];
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~16_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [2];
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [3];
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [4];
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~11_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [5];
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~13_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout ;
wire	[5:0] \macro_inst|u_uart[1]|u_regs|rx_read ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_read [0];
//wire	\macro_inst|u_uart[1]|u_regs|rx_read [1];
//wire	\macro_inst|u_uart[1]|u_regs|rx_read [2];
//wire	\macro_inst|u_uart[1]|u_regs|rx_read [3];
//wire	\macro_inst|u_uart[1]|u_regs|rx_read [4];
//wire	\macro_inst|u_uart[1]|u_regs|rx_read [5];
wire	\macro_inst|u_uart[1]|u_regs|rx_read~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_read~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_read~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_read~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_read~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|rx_read~5_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_regs|rx_reg ;
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [0];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [1];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [2];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [3];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [4];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [5];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [6];
//wire	\macro_inst|u_uart[1]|u_regs|rx_reg [7];
wire	[4:0] \macro_inst|u_uart[1]|u_regs|status_reg ;
//wire	\macro_inst|u_uart[1]|u_regs|status_reg [0];
wire	\macro_inst|u_uart[1]|u_regs|status_reg[0]~0_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|status_reg [1];
//wire	\macro_inst|u_uart[1]|u_regs|status_reg [2];
wire	\macro_inst|u_uart[1]|u_regs|status_reg[2]~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|status_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_regs|status_reg [3];
//wire	\macro_inst|u_uart[1]|u_regs|status_reg [4];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|tx_complete_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|tx_complete_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|tx_complete_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|tx_complete_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|tx_complete_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|tx_complete_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|tx_complete_ie [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|tx_dma_en ;
//wire	\macro_inst|u_uart[1]|u_regs|tx_dma_en [0];
//wire	\macro_inst|u_uart[1]|u_regs|tx_dma_en [1];
//wire	\macro_inst|u_uart[1]|u_regs|tx_dma_en [2];
//wire	\macro_inst|u_uart[1]|u_regs|tx_dma_en [3];
//wire	\macro_inst|u_uart[1]|u_regs|tx_dma_en [4];
//wire	\macro_inst|u_uart[1]|u_regs|tx_dma_en [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|tx_not_full_ie ;
//wire	\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [0];
//wire	\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [1];
//wire	\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [2];
//wire	\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [3];
//wire	\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [4];
//wire	\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [5];
wire	[5:0] \macro_inst|u_uart[1]|u_regs|tx_write ;
//wire	\macro_inst|u_uart[1]|u_regs|tx_write [0];
//wire	\macro_inst|u_uart[1]|u_regs|tx_write [1];
//wire	\macro_inst|u_uart[1]|u_regs|tx_write [2];
//wire	\macro_inst|u_uart[1]|u_regs|tx_write [3];
//wire	\macro_inst|u_uart[1]|u_regs|tx_write [4];
//wire	\macro_inst|u_uart[1]|u_regs|tx_write [5];
wire	\macro_inst|u_uart[1]|u_regs|tx_write~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|tx_write~1_combout ;
wire	\macro_inst|u_uart[1]|u_regs|tx_write~2_combout ;
wire	\macro_inst|u_uart[1]|u_regs|tx_write~3_combout ;
wire	\macro_inst|u_uart[1]|u_regs|tx_write~4_combout ;
wire	\macro_inst|u_uart[1]|u_regs|tx_write~5_combout ;
wire	\macro_inst|u_uart[1]|u_regs|uart_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_regs|uart_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Add4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Add4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Add4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector2~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector2~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector2~5_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector2~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always11~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always11~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always11~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always3~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|break_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|break_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|framing_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|framing_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|overrun_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|parity_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|parity_error~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[1]|u_rx[0]|rx_in ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in [0];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in [1];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in [2];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in[2]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in [3];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in [4];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_parity~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [0];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Add4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Add4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Add4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector2~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector2~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector2~5_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector2~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|Selector4~5_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always10~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always10~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always11~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always11~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always11~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always3~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|break_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|break_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|framing_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|framing_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|overrun_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|parity_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[1]|u_rx[1]|rx_in ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_in [0];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_in [1];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_in [2];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_in [3];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_in [4];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_parity~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Add4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Add4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Add4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector2~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector2~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector2~5_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector2~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always10~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always10~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always11~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always11~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always11~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always3~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|break_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|break_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|framing_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|framing_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|overrun_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|parity_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[1]|u_rx[2]|rx_in ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_in [0];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_in [1];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_in [2];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_in [3];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_in [4];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_parity~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [0];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [1];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [4];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Add4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Add4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Add4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector2~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector2~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector2~5_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector2~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always11~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always11~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always11~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always3~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|break_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|break_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|framing_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|framing_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|overrun_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|parity_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|parity_error~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[1]|u_rx[3]|rx_in ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in [0];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in [1];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in [2];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in[2]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in [3];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in [4];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_parity~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Add4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Add4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Add4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector0~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector0~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector0~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always11~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always11~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always11~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always3~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|break_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|break_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|framing_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|framing_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|overrun_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|parity_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|parity_error~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[1]|u_rx[4]|rx_in ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in [0];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in [1];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in [2];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in[2]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in [3];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in [4];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_parity~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [0];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [1];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [2];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [6];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Add4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Add4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Add4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector1~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector2~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector2~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector2~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector2~5_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector2~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector4~3_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|Selector4~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always11~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always11~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always11~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always2~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always3~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always4~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|always8~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|break_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|break_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|framing_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|framing_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|overrun_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|overrun_error~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|parity_error~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|parity_error~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|parity_error~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ;
wire	[3:0] \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [2];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [3];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~4_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~5_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~feeder_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_idle~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_idle~q ;
wire	[4:0] \macro_inst|u_uart[1]|u_rx[5]|rx_in ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_in [0];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_in [1];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_in [2];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_in [3];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_in [4];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_in[4]~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_parity~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_sample~0_combout ;
wire	[7:0] \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [1];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [2];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [3];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3]~feeder_combout ;
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~1_combout ;
wire	\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|always6~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [5];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout ;
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout ;
wire	\macro_inst|u_uart[1]|u_tx[0]|uart_txd~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|always6~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout ;
wire	\macro_inst|u_uart[1]|u_tx[1]|uart_txd~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|always6~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout ;
wire	\macro_inst|u_uart[1]|u_tx[2]|uart_txd~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|always6~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [2];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout ;
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout ;
wire	\macro_inst|u_uart[1]|u_tx[3]|uart_txd~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|always6~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|comb~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [3];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [4];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout ;
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout ;
wire	\macro_inst|u_uart[1]|u_tx[4]|uart_txd~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector2~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector3~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector3~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector4~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector4~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector5~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector5~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|Selector5~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|always0~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|always6~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|always6~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ;
wire	[3:0] \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [0];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0]~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0]~5 ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [1];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1]~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1]~7 ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2]~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2]~9 ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [3];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3]~10_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_complete~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_complete~q ;
wire	[2:0] \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [0];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [1];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [2];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~3_combout ;
wire	[0:0] \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter [0];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7]~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_parity~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_parity~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_parity~q ;
wire	[7:0] \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [0];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [1];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [2];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [3];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout ;
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [4];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [5];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [6];
//wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [7];
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~2_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~3_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~4_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~5_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~6_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~7_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~8_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~1_combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~q ;
wire	\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout ;
wire	\macro_inst|u_uart[1]|u_tx[5]|uart_txd~q ;
wire	[11:0] \macro_inst|uart_rxd ;
//wire	\macro_inst|uart_rxd [0];
//wire	\macro_inst|uart_rxd [10];
//wire	\macro_inst|uart_rxd [11];
//wire	\macro_inst|uart_rxd [1];
//wire	\macro_inst|uart_rxd [2];
//wire	\macro_inst|uart_rxd [3];
//wire	\macro_inst|uart_rxd [4];
//wire	\macro_inst|uart_rxd [5];
//wire	\macro_inst|uart_rxd [6];
//wire	\macro_inst|uart_rxd [7];
//wire	\macro_inst|uart_rxd [8];
//wire	\macro_inst|uart_rxd [9];
wire	\pll_inst|auto_generated|pll_lock_sync~feeder_combout ;
wire	\pll_inst|auto_generated|pll_lock_sync~q ;
wire	\rv32.dmactive ;
wire	\rv32.ext_dma_DMACCLR[0] ;
wire	\rv32.ext_dma_DMACCLR[1] ;
wire	\rv32.ext_dma_DMACCLR[2] ;
wire	\rv32.ext_dma_DMACCLR[3] ;
wire	\rv32.ext_dma_DMACTC[0] ;
wire	\rv32.ext_dma_DMACTC[1] ;
wire	\rv32.ext_dma_DMACTC[2] ;
wire	\rv32.ext_dma_DMACTC[3] ;
wire	\rv32.gpio0_io_out_data[0] ;
wire	\rv32.gpio0_io_out_data[1] ;
wire	\rv32.gpio0_io_out_data[2] ;
wire	\rv32.gpio0_io_out_data[3] ;
wire	\rv32.gpio0_io_out_data[4] ;
wire	\rv32.gpio0_io_out_data[5] ;
wire	\rv32.gpio0_io_out_data[6] ;
wire	\rv32.gpio0_io_out_data[7] ;
wire	\rv32.gpio0_io_out_en[0] ;
wire	\rv32.gpio0_io_out_en[1] ;
wire	\rv32.gpio0_io_out_en[2] ;
wire	\rv32.gpio0_io_out_en[3] ;
wire	\rv32.gpio0_io_out_en[4] ;
wire	\rv32.gpio0_io_out_en[5] ;
wire	\rv32.gpio0_io_out_en[6] ;
wire	\rv32.gpio0_io_out_en[7] ;
wire	\rv32.gpio1_io_out_data[0] ;
wire	\rv32.gpio1_io_out_data[1] ;
wire	\rv32.gpio1_io_out_data[2] ;
wire	\rv32.gpio1_io_out_data[3] ;
wire	\rv32.gpio1_io_out_data[4] ;
wire	\rv32.gpio1_io_out_data[5] ;
wire	\rv32.gpio1_io_out_data[6] ;
wire	\rv32.gpio1_io_out_data[7] ;
wire	\rv32.gpio1_io_out_en[0] ;
wire	\rv32.gpio1_io_out_en[1] ;
wire	\rv32.gpio1_io_out_en[2] ;
wire	\rv32.gpio1_io_out_en[3] ;
wire	\rv32.gpio1_io_out_en[4] ;
wire	\rv32.gpio1_io_out_en[5] ;
wire	\rv32.gpio1_io_out_en[6] ;
wire	\rv32.gpio1_io_out_en[7] ;
wire	\rv32.gpio2_io_out_data[0] ;
wire	\rv32.gpio2_io_out_data[1] ;
wire	\rv32.gpio2_io_out_data[2] ;
wire	\rv32.gpio2_io_out_data[3] ;
wire	\rv32.gpio2_io_out_data[4] ;
wire	\rv32.gpio2_io_out_data[5] ;
wire	\rv32.gpio2_io_out_data[6] ;
wire	\rv32.gpio2_io_out_data[7] ;
wire	\rv32.gpio2_io_out_en[0] ;
wire	\rv32.gpio2_io_out_en[1] ;
wire	\rv32.gpio2_io_out_en[2] ;
wire	\rv32.gpio2_io_out_en[3] ;
wire	\rv32.gpio2_io_out_en[4] ;
wire	\rv32.gpio2_io_out_en[5] ;
wire	\rv32.gpio2_io_out_en[6] ;
wire	\rv32.gpio2_io_out_en[7] ;
wire	\rv32.gpio3_io_out_data[0] ;
wire	\rv32.gpio3_io_out_data[1] ;
wire	\rv32.gpio3_io_out_data[2] ;
wire	\rv32.gpio3_io_out_data[3] ;
wire	\rv32.gpio3_io_out_data[4] ;
wire	\rv32.gpio3_io_out_data[5] ;
wire	\rv32.gpio3_io_out_data[6] ;
wire	\rv32.gpio3_io_out_data[7] ;
wire	\rv32.gpio3_io_out_en[0] ;
wire	\rv32.gpio3_io_out_en[1] ;
wire	\rv32.gpio3_io_out_en[2] ;
wire	\rv32.gpio3_io_out_en[3] ;
wire	\rv32.gpio3_io_out_en[4] ;
wire	\rv32.gpio3_io_out_en[5] ;
wire	\rv32.gpio3_io_out_en[6] ;
wire	\rv32.gpio3_io_out_en[7] ;
wire	\rv32.gpio4_io_out_data[0] ;
wire	\rv32.gpio4_io_out_data[1] ;
wire	\rv32.gpio4_io_out_data[2] ;
wire	\rv32.gpio4_io_out_data[3] ;
wire	\rv32.gpio4_io_out_data[4] ;
wire	\rv32.gpio4_io_out_data[5] ;
wire	\rv32.gpio4_io_out_data[6] ;
wire	\rv32.gpio4_io_out_data[7] ;
wire	\rv32.gpio4_io_out_en[0] ;
wire	\rv32.gpio4_io_out_en[1] ;
wire	\rv32.gpio4_io_out_en[2] ;
wire	\rv32.gpio4_io_out_en[3] ;
wire	\rv32.gpio4_io_out_en[4] ;
wire	\rv32.gpio4_io_out_en[5] ;
wire	\rv32.gpio4_io_out_en[6] ;
wire	\rv32.gpio4_io_out_en[7] ;
wire	\rv32.gpio5_io_out_data[0] ;
wire	\rv32.gpio5_io_out_data[1] ;
wire	\rv32.gpio5_io_out_data[2] ;
wire	\rv32.gpio5_io_out_data[3] ;
wire	\rv32.gpio5_io_out_data[4] ;
wire	\rv32.gpio5_io_out_data[5] ;
wire	\rv32.gpio5_io_out_data[6] ;
wire	\rv32.gpio5_io_out_data[7] ;
wire	\rv32.gpio5_io_out_en[0] ;
wire	\rv32.gpio5_io_out_en[1] ;
wire	\rv32.gpio5_io_out_en[2] ;
wire	\rv32.gpio5_io_out_en[3] ;
wire	\rv32.gpio5_io_out_en[4] ;
wire	\rv32.gpio5_io_out_en[5] ;
wire	\rv32.gpio5_io_out_en[6] ;
wire	\rv32.gpio5_io_out_en[7] ;
wire	\rv32.gpio6_io_out_data[0] ;
wire	\rv32.gpio6_io_out_data[1] ;
wire	\rv32.gpio6_io_out_data[2] ;
wire	\rv32.gpio6_io_out_data[3] ;
wire	\rv32.gpio6_io_out_data[4] ;
wire	\rv32.gpio6_io_out_data[5] ;
wire	\rv32.gpio6_io_out_data[6] ;
wire	\rv32.gpio6_io_out_data[7] ;
wire	\rv32.gpio6_io_out_en[0] ;
wire	\rv32.gpio6_io_out_en[1] ;
wire	\rv32.gpio6_io_out_en[2] ;
wire	\rv32.gpio6_io_out_en[3] ;
wire	\rv32.gpio6_io_out_en[4] ;
wire	\rv32.gpio6_io_out_en[5] ;
wire	\rv32.gpio6_io_out_en[6] ;
wire	\rv32.gpio6_io_out_en[7] ;
wire	\rv32.gpio7_io_out_data[0] ;
wire	\rv32.gpio7_io_out_data[1] ;
wire	\rv32.gpio7_io_out_data[2] ;
wire	\rv32.gpio7_io_out_data[3] ;
wire	\rv32.gpio7_io_out_data[4] ;
wire	\rv32.gpio7_io_out_data[5] ;
wire	\rv32.gpio7_io_out_data[6] ;
wire	\rv32.gpio7_io_out_data[7] ;
wire	\rv32.gpio7_io_out_en[0] ;
wire	\rv32.gpio7_io_out_en[1] ;
wire	\rv32.gpio7_io_out_en[2] ;
wire	\rv32.gpio7_io_out_en[3] ;
wire	\rv32.gpio7_io_out_en[4] ;
wire	\rv32.gpio7_io_out_en[5] ;
wire	\rv32.gpio7_io_out_en[6] ;
wire	\rv32.gpio7_io_out_en[7] ;
wire	\rv32.gpio8_io_out_data[0] ;
wire	\rv32.gpio8_io_out_data[1] ;
wire	\rv32.gpio8_io_out_data[2] ;
wire	\rv32.gpio8_io_out_data[3] ;
wire	\rv32.gpio8_io_out_data[4] ;
wire	\rv32.gpio8_io_out_data[5] ;
wire	\rv32.gpio8_io_out_data[6] ;
wire	\rv32.gpio8_io_out_data[7] ;
wire	\rv32.gpio8_io_out_en[0] ;
wire	\rv32.gpio8_io_out_en[1] ;
wire	\rv32.gpio8_io_out_en[2] ;
wire	\rv32.gpio8_io_out_en[3] ;
wire	\rv32.gpio8_io_out_en[4] ;
wire	\rv32.gpio8_io_out_en[5] ;
wire	\rv32.gpio8_io_out_en[6] ;
wire	\rv32.gpio8_io_out_en[7] ;
wire	\rv32.gpio9_io_out_data[0] ;
wire	\rv32.gpio9_io_out_data[1] ;
wire	\rv32.gpio9_io_out_data[2] ;
wire	\rv32.gpio9_io_out_data[3] ;
wire	\rv32.gpio9_io_out_data[4] ;
wire	\rv32.gpio9_io_out_data[5] ;
wire	\rv32.gpio9_io_out_data[6] ;
wire	\rv32.gpio9_io_out_data[7] ;
wire	\rv32.gpio9_io_out_en[0] ;
wire	\rv32.gpio9_io_out_en[1] ;
wire	\rv32.gpio9_io_out_en[2] ;
wire	\rv32.gpio9_io_out_en[3] ;
wire	\rv32.gpio9_io_out_en[4] ;
wire	\rv32.gpio9_io_out_en[5] ;
wire	\rv32.gpio9_io_out_en[6] ;
wire	\rv32.gpio9_io_out_en[7] ;
wire	\rv32.mem_ahb_haddr[0] ;
wire	\rv32.mem_ahb_haddr[10] ;
wire	\rv32.mem_ahb_haddr[11] ;
wire	\rv32.mem_ahb_haddr[12] ;
wire	\rv32.mem_ahb_haddr[13] ;
wire	\rv32.mem_ahb_haddr[14] ;
wire	\rv32.mem_ahb_haddr[15] ;
wire	\rv32.mem_ahb_haddr[16] ;
wire	\rv32.mem_ahb_haddr[17] ;
wire	\rv32.mem_ahb_haddr[18] ;
wire	\rv32.mem_ahb_haddr[19] ;
wire	\rv32.mem_ahb_haddr[1] ;
wire	\rv32.mem_ahb_haddr[20] ;
wire	\rv32.mem_ahb_haddr[21] ;
wire	\rv32.mem_ahb_haddr[22] ;
wire	\rv32.mem_ahb_haddr[23] ;
wire	\rv32.mem_ahb_haddr[24] ;
wire	\rv32.mem_ahb_haddr[25] ;
wire	\rv32.mem_ahb_haddr[26] ;
wire	\rv32.mem_ahb_haddr[27] ;
wire	\rv32.mem_ahb_haddr[28] ;
wire	\rv32.mem_ahb_haddr[29] ;
wire	\rv32.mem_ahb_haddr[2] ;
wire	\rv32.mem_ahb_haddr[30] ;
wire	\rv32.mem_ahb_haddr[31] ;
wire	\rv32.mem_ahb_haddr[3] ;
wire	\rv32.mem_ahb_haddr[4] ;
wire	\rv32.mem_ahb_haddr[5] ;
wire	\rv32.mem_ahb_haddr[6] ;
wire	\rv32.mem_ahb_haddr[7] ;
wire	\rv32.mem_ahb_haddr[8] ;
wire	\rv32.mem_ahb_haddr[9] ;
wire	\rv32.mem_ahb_hburst[0] ;
wire	\rv32.mem_ahb_hburst[1] ;
wire	\rv32.mem_ahb_hburst[2] ;
wire	\rv32.mem_ahb_hready ;
wire	\rv32.mem_ahb_hsize[0] ;
wire	\rv32.mem_ahb_hsize[1] ;
wire	\rv32.mem_ahb_hsize[2] ;
wire	\rv32.mem_ahb_htrans[0] ;
wire	\rv32.mem_ahb_htrans[1] ;
wire	\rv32.mem_ahb_hwdata[0] ;
wire	\rv32.mem_ahb_hwdata[10] ;
wire	\rv32.mem_ahb_hwdata[11] ;
wire	\rv32.mem_ahb_hwdata[12] ;
wire	\rv32.mem_ahb_hwdata[13] ;
wire	\rv32.mem_ahb_hwdata[14] ;
wire	\rv32.mem_ahb_hwdata[15] ;
wire	\rv32.mem_ahb_hwdata[16] ;
wire	\rv32.mem_ahb_hwdata[17] ;
wire	\rv32.mem_ahb_hwdata[18] ;
wire	\rv32.mem_ahb_hwdata[19] ;
wire	\rv32.mem_ahb_hwdata[1] ;
wire	\rv32.mem_ahb_hwdata[20] ;
wire	\rv32.mem_ahb_hwdata[21] ;
wire	\rv32.mem_ahb_hwdata[22] ;
wire	\rv32.mem_ahb_hwdata[23] ;
wire	\rv32.mem_ahb_hwdata[24] ;
wire	\rv32.mem_ahb_hwdata[25] ;
wire	\rv32.mem_ahb_hwdata[26] ;
wire	\rv32.mem_ahb_hwdata[27] ;
wire	\rv32.mem_ahb_hwdata[28] ;
wire	\rv32.mem_ahb_hwdata[29] ;
wire	\rv32.mem_ahb_hwdata[2] ;
wire	\rv32.mem_ahb_hwdata[30] ;
wire	\rv32.mem_ahb_hwdata[31] ;
wire	\rv32.mem_ahb_hwdata[3] ;
wire	\rv32.mem_ahb_hwdata[4] ;
wire	\rv32.mem_ahb_hwdata[5] ;
wire	\rv32.mem_ahb_hwdata[6] ;
wire	\rv32.mem_ahb_hwdata[7] ;
wire	\rv32.mem_ahb_hwdata[8] ;
wire	\rv32.mem_ahb_hwdata[9] ;
wire	\rv32.mem_ahb_hwrite ;
wire	\rv32.resetn_out ;
wire	\rv32.slave_ahb_hrdata[0] ;
wire	\rv32.slave_ahb_hrdata[10] ;
wire	\rv32.slave_ahb_hrdata[11] ;
wire	\rv32.slave_ahb_hrdata[12] ;
wire	\rv32.slave_ahb_hrdata[13] ;
wire	\rv32.slave_ahb_hrdata[14] ;
wire	\rv32.slave_ahb_hrdata[15] ;
wire	\rv32.slave_ahb_hrdata[16] ;
wire	\rv32.slave_ahb_hrdata[17] ;
wire	\rv32.slave_ahb_hrdata[18] ;
wire	\rv32.slave_ahb_hrdata[19] ;
wire	\rv32.slave_ahb_hrdata[1] ;
wire	\rv32.slave_ahb_hrdata[20] ;
wire	\rv32.slave_ahb_hrdata[21] ;
wire	\rv32.slave_ahb_hrdata[22] ;
wire	\rv32.slave_ahb_hrdata[23] ;
wire	\rv32.slave_ahb_hrdata[24] ;
wire	\rv32.slave_ahb_hrdata[25] ;
wire	\rv32.slave_ahb_hrdata[26] ;
wire	\rv32.slave_ahb_hrdata[27] ;
wire	\rv32.slave_ahb_hrdata[28] ;
wire	\rv32.slave_ahb_hrdata[29] ;
wire	\rv32.slave_ahb_hrdata[2] ;
wire	\rv32.slave_ahb_hrdata[30] ;
wire	\rv32.slave_ahb_hrdata[31] ;
wire	\rv32.slave_ahb_hrdata[3] ;
wire	\rv32.slave_ahb_hrdata[4] ;
wire	\rv32.slave_ahb_hrdata[5] ;
wire	\rv32.slave_ahb_hrdata[6] ;
wire	\rv32.slave_ahb_hrdata[7] ;
wire	\rv32.slave_ahb_hrdata[8] ;
wire	\rv32.slave_ahb_hrdata[9] ;
wire	\rv32.slave_ahb_hreadyout ;
wire	\rv32.slave_ahb_hresp ;
wire	\rv32.swj_JTAGIR[0] ;
wire	\rv32.swj_JTAGIR[1] ;
wire	\rv32.swj_JTAGIR[2] ;
wire	\rv32.swj_JTAGIR[3] ;
wire	\rv32.swj_JTAGNSW ;
wire	\rv32.swj_JTAGSTATE[0] ;
wire	\rv32.swj_JTAGSTATE[1] ;
wire	\rv32.swj_JTAGSTATE[2] ;
wire	\rv32.swj_JTAGSTATE[3] ;
wire	\rv32.sys_ctrl_clkSource[0] ;
wire	\rv32.sys_ctrl_clkSource[1] ;
wire	\rv32.sys_ctrl_hseBypass ;
wire	\rv32.sys_ctrl_hseEnable ;
wire	\rv32.sys_ctrl_pllEnable ;
wire	\rv32.sys_ctrl_sleep ;
wire	\rv32.sys_ctrl_standby ;
wire	\rv32.sys_ctrl_stop ;
wire	\sys_resetn~clkctrl_outclk ;
wire	\sys_resetn~combout ;
wire	\uart15_rx~input_o ;
//wire	\uart15_tx~output_o ;
wire	\~GND~combout ;
wire	\~VCC~combout ;
wire	hbi_272_0_9cb2c0024f9919c5_bp;
wire	hbi_272_1_9cb2c0024f9919c5_bp;
wire	[4:0] \pll_inst|auto_generated|clk ;
//wire	\pll_inst|auto_generated|clk [0];
wire	[4:0] \pll_inst|auto_generated|pll1_CLK_bus ;
//wire	\pll_inst|auto_generated|pll1_CLK_bus [0];
//wire	\pll_inst|auto_generated|clk [1];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [1];
//wire	\pll_inst|auto_generated|clk [2];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [2];
//wire	\pll_inst|auto_generated|clk [3];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [3];
//wire	\pll_inst|auto_generated|clk [4];
//wire	\pll_inst|auto_generated|pll1_CLK_bus [4];
wire	\pll_inst|auto_generated|pll1~FBOUT ;

wire vcc;
wire gnd;
assign vcc = 1'b1;
assign gnd = 1'b0;
wire unknown;
assign unknown = 1'bx;

// Location: BBOX_X1_Y1_N0
alta_rv32 rv32(
	.sys_clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ),
	.mem_ahb_hready(\rv32.mem_ahb_hready ),
	.mem_ahb_hreadyout(!\macro_inst|u_ahb2apb|hreadyout~q ),
	.mem_ahb_htrans({\rv32.mem_ahb_htrans[1] , \rv32.mem_ahb_htrans[0] }),
	.mem_ahb_hsize({\rv32.mem_ahb_hsize[2] , \rv32.mem_ahb_hsize[1] , \rv32.mem_ahb_hsize[0] }),
	.mem_ahb_hburst({\rv32.mem_ahb_hburst[2] , \rv32.mem_ahb_hburst[1] , \rv32.mem_ahb_hburst[0] }),
	.mem_ahb_hwrite(\rv32.mem_ahb_hwrite ),
	.mem_ahb_haddr({\rv32.mem_ahb_haddr[31] , \rv32.mem_ahb_haddr[30] , \rv32.mem_ahb_haddr[29] , \rv32.mem_ahb_haddr[28] , \rv32.mem_ahb_haddr[27] , \rv32.mem_ahb_haddr[26] , \rv32.mem_ahb_haddr[25] , \rv32.mem_ahb_haddr[24] , \rv32.mem_ahb_haddr[23] , \rv32.mem_ahb_haddr[22] , \rv32.mem_ahb_haddr[21] , \rv32.mem_ahb_haddr[20] , \rv32.mem_ahb_haddr[19] , \rv32.mem_ahb_haddr[18] , \rv32.mem_ahb_haddr[17] , \rv32.mem_ahb_haddr[16] , \rv32.mem_ahb_haddr[15] , \rv32.mem_ahb_haddr[14] , \rv32.mem_ahb_haddr[13] , \rv32.mem_ahb_haddr[12] , \rv32.mem_ahb_haddr[11] , \rv32.mem_ahb_haddr[10] , \rv32.mem_ahb_haddr[9] , \rv32.mem_ahb_haddr[8] , \rv32.mem_ahb_haddr[7] , \rv32.mem_ahb_haddr[6] , \rv32.mem_ahb_haddr[5] , \rv32.mem_ahb_haddr[4] , \rv32.mem_ahb_haddr[3] , \rv32.mem_ahb_haddr[2] , \rv32.mem_ahb_haddr[1] , \rv32.mem_ahb_haddr[0] }),
	.mem_ahb_hwdata({\rv32.mem_ahb_hwdata[31] , \rv32.mem_ahb_hwdata[30] , \rv32.mem_ahb_hwdata[29] , \rv32.mem_ahb_hwdata[28] , \rv32.mem_ahb_hwdata[27] , \rv32.mem_ahb_hwdata[26] , \rv32.mem_ahb_hwdata[25] , \rv32.mem_ahb_hwdata[24] , \rv32.mem_ahb_hwdata[23] , \rv32.mem_ahb_hwdata[22] , \rv32.mem_ahb_hwdata[21] , \rv32.mem_ahb_hwdata[20] , \rv32.mem_ahb_hwdata[19] , \rv32.mem_ahb_hwdata[18] , \rv32.mem_ahb_hwdata[17] , \rv32.mem_ahb_hwdata[16] , \rv32.mem_ahb_hwdata[15] , \rv32.mem_ahb_hwdata[14] , \rv32.mem_ahb_hwdata[13] , \rv32.mem_ahb_hwdata[12] , \rv32.mem_ahb_hwdata[11] , \rv32.mem_ahb_hwdata[10] , \rv32.mem_ahb_hwdata[9] , \rv32.mem_ahb_hwdata[8] , \rv32.mem_ahb_hwdata[7] , \rv32.mem_ahb_hwdata[6] , \rv32.mem_ahb_hwdata[5] , \rv32.mem_ahb_hwdata[4] , \rv32.mem_ahb_hwdata[3] , \rv32.mem_ahb_hwdata[2] , \rv32.mem_ahb_hwdata[1] , \rv32.mem_ahb_hwdata[0] }),
	.mem_ahb_hresp(\~GND~combout ),
	.mem_ahb_hrdata({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \macro_inst|u_ahb2apb|prdata [15], \macro_inst|u_ahb2apb|prdata [14], \macro_inst|u_ahb2apb|prdata [13], \macro_inst|u_ahb2apb|prdata [12], \macro_inst|u_ahb2apb|prdata [11], \macro_inst|u_ahb2apb|prdata [10], \macro_inst|u_ahb2apb|prdata [9], \macro_inst|u_ahb2apb|prdata [8], \macro_inst|u_ahb2apb|prdata [7], \macro_inst|u_ahb2apb|prdata [6], \macro_inst|u_ahb2apb|prdata [5], \macro_inst|u_ahb2apb|prdata [4], \macro_inst|u_ahb2apb|prdata [3], \macro_inst|u_ahb2apb|prdata [2], \macro_inst|u_ahb2apb|prdata [1], \macro_inst|u_ahb2apb|prdata [0]}),
	.slave_ahb_hsel(\~GND~combout ),
	.slave_ahb_hready(\~VCC~combout ),
	.slave_ahb_hreadyout(\rv32.slave_ahb_hreadyout ),
	.slave_ahb_htrans({\~GND~combout , \~GND~combout }),
	.slave_ahb_hsize({\~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hburst({\~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hwrite(\~GND~combout ),
	.slave_ahb_haddr({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hwdata({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.slave_ahb_hresp(\rv32.slave_ahb_hresp ),
	.slave_ahb_hrdata({\rv32.slave_ahb_hrdata[31] , \rv32.slave_ahb_hrdata[30] , \rv32.slave_ahb_hrdata[29] , \rv32.slave_ahb_hrdata[28] , \rv32.slave_ahb_hrdata[27] , \rv32.slave_ahb_hrdata[26] , \rv32.slave_ahb_hrdata[25] , \rv32.slave_ahb_hrdata[24] , \rv32.slave_ahb_hrdata[23] , \rv32.slave_ahb_hrdata[22] , \rv32.slave_ahb_hrdata[21] , \rv32.slave_ahb_hrdata[20] , \rv32.slave_ahb_hrdata[19] , \rv32.slave_ahb_hrdata[18] , \rv32.slave_ahb_hrdata[17] , \rv32.slave_ahb_hrdata[16] , \rv32.slave_ahb_hrdata[15] , \rv32.slave_ahb_hrdata[14] , \rv32.slave_ahb_hrdata[13] , \rv32.slave_ahb_hrdata[12] , \rv32.slave_ahb_hrdata[11] , \rv32.slave_ahb_hrdata[10] , \rv32.slave_ahb_hrdata[9] , \rv32.slave_ahb_hrdata[8] , \rv32.slave_ahb_hrdata[7] , \rv32.slave_ahb_hrdata[6] , \rv32.slave_ahb_hrdata[5] , \rv32.slave_ahb_hrdata[4] , \rv32.slave_ahb_hrdata[3] , \rv32.slave_ahb_hrdata[2] , \rv32.slave_ahb_hrdata[1] , \rv32.slave_ahb_hrdata[0] }),
	.gpio0_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio0_io_out_data({\rv32.gpio0_io_out_data[7] , \rv32.gpio0_io_out_data[6] , \rv32.gpio0_io_out_data[5] , \rv32.gpio0_io_out_data[4] , \rv32.gpio0_io_out_data[3] , \rv32.gpio0_io_out_data[2] , \rv32.gpio0_io_out_data[1] , \rv32.gpio0_io_out_data[0] }),
	.gpio0_io_out_en({\rv32.gpio0_io_out_en[7] , \rv32.gpio0_io_out_en[6] , \rv32.gpio0_io_out_en[5] , \rv32.gpio0_io_out_en[4] , \rv32.gpio0_io_out_en[3] , \rv32.gpio0_io_out_en[2] , \rv32.gpio0_io_out_en[1] , \rv32.gpio0_io_out_en[0] }),
	.gpio1_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio1_io_out_data({\rv32.gpio1_io_out_data[7] , \rv32.gpio1_io_out_data[6] , \rv32.gpio1_io_out_data[5] , \rv32.gpio1_io_out_data[4] , \rv32.gpio1_io_out_data[3] , \rv32.gpio1_io_out_data[2] , \rv32.gpio1_io_out_data[1] , \rv32.gpio1_io_out_data[0] }),
	.gpio1_io_out_en({\rv32.gpio1_io_out_en[7] , \rv32.gpio1_io_out_en[6] , \rv32.gpio1_io_out_en[5] , \rv32.gpio1_io_out_en[4] , \rv32.gpio1_io_out_en[3] , \rv32.gpio1_io_out_en[2] , \rv32.gpio1_io_out_en[1] , \rv32.gpio1_io_out_en[0] }),
	.sys_ctrl_clkSource({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.sys_ctrl_hseEnable(\rv32.sys_ctrl_hseEnable ),
	.sys_ctrl_hseBypass(\rv32.sys_ctrl_hseBypass ),
	.sys_ctrl_pllEnable(\rv32.sys_ctrl_pllEnable ),
	.sys_ctrl_pllReady(\PLL_LOCK~combout ),
	.sys_ctrl_sleep(\rv32.sys_ctrl_sleep ),
	.sys_ctrl_stop(\rv32.sys_ctrl_stop ),
	.sys_ctrl_standby(\rv32.sys_ctrl_standby ),
	.gpio2_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio2_io_out_data({\rv32.gpio2_io_out_data[7] , \rv32.gpio2_io_out_data[6] , \rv32.gpio2_io_out_data[5] , \rv32.gpio2_io_out_data[4] , \rv32.gpio2_io_out_data[3] , \rv32.gpio2_io_out_data[2] , \rv32.gpio2_io_out_data[1] , \rv32.gpio2_io_out_data[0] }),
	.gpio2_io_out_en({\rv32.gpio2_io_out_en[7] , \rv32.gpio2_io_out_en[6] , \rv32.gpio2_io_out_en[5] , \rv32.gpio2_io_out_en[4] , \rv32.gpio2_io_out_en[3] , \rv32.gpio2_io_out_en[2] , \rv32.gpio2_io_out_en[1] , \rv32.gpio2_io_out_en[0] }),
	.gpio3_io_in({gpio3_io_in[7], gpio3_io_in[6], gpio3_io_in[5], \GPIO3_4~input_o , \GPIO3_3~input_o , \GPIO3_2~input_o , \GPIO3_1~input_o , \GPIO3_0~input_o }),
	.gpio3_io_out_data({\rv32.gpio3_io_out_data[7] , \rv32.gpio3_io_out_data[6] , \rv32.gpio3_io_out_data[5] , \rv32.gpio3_io_out_data[4] , \rv32.gpio3_io_out_data[3] , \rv32.gpio3_io_out_data[2] , \rv32.gpio3_io_out_data[1] , \rv32.gpio3_io_out_data[0] }),
	.gpio3_io_out_en({\rv32.gpio3_io_out_en[7] , \rv32.gpio3_io_out_en[6] , \rv32.gpio3_io_out_en[5] , \rv32.gpio3_io_out_en[4] , \rv32.gpio3_io_out_en[3] , \rv32.gpio3_io_out_en[2] , \rv32.gpio3_io_out_en[1] , \rv32.gpio3_io_out_en[0] }),
	.gpio4_io_in({gpio4_io_in[7], gpio4_io_in[6], \macro_inst|u_uart[0]|u_regs|interrupts [5], \macro_inst|u_uart[0]|u_regs|interrupts [4], \macro_inst|u_uart[0]|u_regs|interrupts [3], \macro_inst|u_uart[0]|u_regs|interrupts [2], \macro_inst|u_uart[0]|u_regs|interrupts [1], \macro_inst|u_uart[0]|u_regs|interrupts [0]}),
	.gpio4_io_out_data({\rv32.gpio4_io_out_data[7] , \rv32.gpio4_io_out_data[6] , \rv32.gpio4_io_out_data[5] , \rv32.gpio4_io_out_data[4] , \rv32.gpio4_io_out_data[3] , \rv32.gpio4_io_out_data[2] , \rv32.gpio4_io_out_data[1] , \rv32.gpio4_io_out_data[0] }),
	.gpio4_io_out_en({\rv32.gpio4_io_out_en[7] , \rv32.gpio4_io_out_en[6] , \rv32.gpio4_io_out_en[5] , \rv32.gpio4_io_out_en[4] , \rv32.gpio4_io_out_en[3] , \rv32.gpio4_io_out_en[2] , \rv32.gpio4_io_out_en[1] , \rv32.gpio4_io_out_en[0] }),
	.gpio5_io_in({gpio5_io_in[7], gpio5_io_in[6], \macro_inst|u_uart[1]|u_regs|interrupts [5], \macro_inst|u_uart[1]|u_regs|interrupts [4], \macro_inst|u_uart[1]|u_regs|interrupts [3], \macro_inst|u_uart[1]|u_regs|interrupts [2], \macro_inst|u_uart[1]|u_regs|interrupts [1], \macro_inst|u_uart[1]|u_regs|interrupts [0]}),
	.gpio5_io_out_data({\rv32.gpio5_io_out_data[7] , \rv32.gpio5_io_out_data[6] , \rv32.gpio5_io_out_data[5] , \rv32.gpio5_io_out_data[4] , \rv32.gpio5_io_out_data[3] , \rv32.gpio5_io_out_data[2] , \rv32.gpio5_io_out_data[1] , \rv32.gpio5_io_out_data[0] }),
	.gpio5_io_out_en({\rv32.gpio5_io_out_en[7] , \rv32.gpio5_io_out_en[6] , \rv32.gpio5_io_out_en[5] , \rv32.gpio5_io_out_en[4] , \rv32.gpio5_io_out_en[3] , \rv32.gpio5_io_out_en[2] , \rv32.gpio5_io_out_en[1] , \rv32.gpio5_io_out_en[0] }),
	.gpio6_io_in({\UART3_UARTRXD~input_o , \GPIO6_6~input_o , gpio6_io_in[5], gpio6_io_in[4], gpio6_io_in[3], gpio6_io_in[2], gpio6_io_in[1], gpio6_io_in[0]}),
	.gpio6_io_out_data({\rv32.gpio6_io_out_data[7] , \rv32.gpio6_io_out_data[6] , \rv32.gpio6_io_out_data[5] , \rv32.gpio6_io_out_data[4] , \rv32.gpio6_io_out_data[3] , \rv32.gpio6_io_out_data[2] , \rv32.gpio6_io_out_data[1] , \rv32.gpio6_io_out_data[0] }),
	.gpio6_io_out_en({\rv32.gpio6_io_out_en[7] , \rv32.gpio6_io_out_en[6] , \rv32.gpio6_io_out_en[5] , \rv32.gpio6_io_out_en[4] , \rv32.gpio6_io_out_en[3] , \rv32.gpio6_io_out_en[2] , \rv32.gpio6_io_out_en[1] , \rv32.gpio6_io_out_en[0] }),
	.gpio7_io_in({gpio7_io_in[7], gpio7_io_in[6], gpio7_io_in[5], gpio7_io_in[4], gpio7_io_in[3], gpio7_io_in[2], \UART4_UARTRXD~input_o , gpio7_io_in[0]}),
	.gpio7_io_out_data({\rv32.gpio7_io_out_data[7] , \rv32.gpio7_io_out_data[6] , \rv32.gpio7_io_out_data[5] , \rv32.gpio7_io_out_data[4] , \rv32.gpio7_io_out_data[3] , \rv32.gpio7_io_out_data[2] , \rv32.gpio7_io_out_data[1] , \rv32.gpio7_io_out_data[0] }),
	.gpio7_io_out_en({\rv32.gpio7_io_out_en[7] , \rv32.gpio7_io_out_en[6] , \rv32.gpio7_io_out_en[5] , \rv32.gpio7_io_out_en[4] , \rv32.gpio7_io_out_en[3] , \rv32.gpio7_io_out_en[2] , \rv32.gpio7_io_out_en[1] , \rv32.gpio7_io_out_en[0] }),
	.gpio8_io_in({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.gpio8_io_out_data({\rv32.gpio8_io_out_data[7] , \rv32.gpio8_io_out_data[6] , \rv32.gpio8_io_out_data[5] , \rv32.gpio8_io_out_data[4] , \rv32.gpio8_io_out_data[3] , \rv32.gpio8_io_out_data[2] , \rv32.gpio8_io_out_data[1] , \rv32.gpio8_io_out_data[0] }),
	.gpio8_io_out_en({\rv32.gpio8_io_out_en[7] , \rv32.gpio8_io_out_en[6] , \rv32.gpio8_io_out_en[5] , \rv32.gpio8_io_out_en[4] , \rv32.gpio8_io_out_en[3] , \rv32.gpio8_io_out_en[2] , \rv32.gpio8_io_out_en[1] , \rv32.gpio8_io_out_en[0] }),
	.gpio9_io_in({gpio9_io_in[7], gpio9_io_in[6], gpio9_io_in[5], gpio9_io_in[4], gpio9_io_in[3], gpio9_io_in[2], \GPIO9_1~input_o , gpio9_io_in[0]}),
	.gpio9_io_out_data({\rv32.gpio9_io_out_data[7] , \rv32.gpio9_io_out_data[6] , \rv32.gpio9_io_out_data[5] , \rv32.gpio9_io_out_data[4] , \rv32.gpio9_io_out_data[3] , \rv32.gpio9_io_out_data[2] , \rv32.gpio9_io_out_data[1] , \rv32.gpio9_io_out_data[0] }),
	.gpio9_io_out_en({\rv32.gpio9_io_out_en[7] , \rv32.gpio9_io_out_en[6] , \rv32.gpio9_io_out_en[5] , \rv32.gpio9_io_out_en[4] , \rv32.gpio9_io_out_en[3] , \rv32.gpio9_io_out_en[2] , \rv32.gpio9_io_out_en[1] , \rv32.gpio9_io_out_en[0] }),
	.ext_resetn(\~VCC~combout ),
	.resetn_out(\rv32.resetn_out ),
	.dmactive(\rv32.dmactive ),
	.swj_JTAGNSW(\rv32.swj_JTAGNSW ),
	.swj_JTAGSTATE({\rv32.swj_JTAGSTATE[3] , \rv32.swj_JTAGSTATE[2] , \rv32.swj_JTAGSTATE[1] , \rv32.swj_JTAGSTATE[0] }),
	.swj_JTAGIR({\rv32.swj_JTAGIR[3] , \rv32.swj_JTAGIR[2] , \rv32.swj_JTAGIR[1] , \rv32.swj_JTAGIR[0] }),
	.ext_int({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACBREQ({\macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~q , \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~q , \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~q , \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~q }),
	.ext_dma_DMACLBREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACSREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACLSREQ({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.ext_dma_DMACCLR({\rv32.ext_dma_DMACCLR[3] , \rv32.ext_dma_DMACCLR[2] , \rv32.ext_dma_DMACCLR[1] , \rv32.ext_dma_DMACCLR[0] }),
	.ext_dma_DMACTC({\rv32.ext_dma_DMACTC[3] , \rv32.ext_dma_DMACTC[2] , \rv32.ext_dma_DMACTC[1] , \rv32.ext_dma_DMACTC[0] }),
	.local_int({\~GND~combout , \~GND~combout , \~GND~combout , \~GND~combout }),
	.test_mode({\~GND~combout , \~GND~combout }),
	.usb0_xcvr_clk(\~VCC~combout ),
	.usb0_id(\~VCC~combout ));

// Location: IOIBUF_X0_Y30_N1
// alta_io_ibuf \PIN_HSE~input (
alta_rio \PIN_HSE~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSE~input_o ),
	.regout(),
	.padio(PIN_HSE));
defparam \PIN_HSE~input .CFG_KEEP = 2'b00;
// defparam \PIN_HSE~input .simulate_z_as = "z";

// Location: IOIBUF_X0_Y30_N2
// alta_io_ibuf \PIN_HSI~input (
alta_rio \PIN_HSI~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_HSI~input_o ),
	.regout(),
	.padio(PIN_HSI));
defparam \PIN_HSI~input .CFG_KEEP = 2'b00;
// defparam \PIN_HSI~input .simulate_z_as = "z";

// Location: IOOBUF_X27_Y0_N1
// alta_io_obuf \SIM_CLK~output (
alta_rio \SIM_CLK~output (
	.datain(\macro_inst|sim_clk_reg~q ),
	.oe(vcc),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(SIM_CLK));
defparam \SIM_CLK~output .CFG_KEEP = 2'b00;
// defparam \SIM_CLK~output .open_drain_output = "false";

// Location: IOIBUF_X31_Y0_N0
// alta_io_ibuf \UART3_UARTRXD~input (
alta_rio \UART3_UARTRXD~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART3_UARTRXD~input_o ),
	.regout(),
	.padio(UART3_UARTRXD));
defparam \UART3_UARTRXD~input .CFG_KEEP = 2'b00;
// defparam \UART3_UARTRXD~input .simulate_z_as = "z";

// Location: IOIBUF_X31_Y0_N1
// alta_io_ibuf \GPIO3_2~input (
alta_rio \GPIO3_2~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO3_2~input_o ),
	.regout(),
	.padio(GPIO3_2));
defparam \GPIO3_2~input .CFG_KEEP = 2'b00;
// defparam \GPIO3_2~input .simulate_z_as = "z";

// Location: IOIBUF_X31_Y0_N2
// alta_io_ibuf \UART4_UARTRXD~input (
alta_rio \UART4_UARTRXD~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\UART4_UARTRXD~input_o ),
	.regout(),
	.padio(UART4_UARTRXD));
defparam \UART4_UARTRXD~input .CFG_KEEP = 2'b00;
// defparam \UART4_UARTRXD~input .simulate_z_as = "z";

// Location: IOIBUF_X31_Y0_N3
// alta_io_ibuf \uart15_rx~input (
alta_rio \uart15_rx~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\uart15_rx~input_o ),
	.regout(),
	.padio(uart15_rx));
defparam \uart15_rx~input .CFG_KEEP = 2'b00;
// defparam \uart15_rx~input .simulate_z_as = "z";

// Location: IOIBUF_X34_Y0_N0
// alta_io_ibuf \GPIO3_1~input (
alta_rio \GPIO3_1~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO3_1~input_o ),
	.regout(),
	.padio(GPIO3_1));
defparam \GPIO3_1~input .CFG_KEEP = 2'b00;
// defparam \GPIO3_1~input .simulate_z_as = "z";

// Location: IOIBUF_X34_Y0_N1
// alta_io_ibuf \GPIO3_3~input (
alta_rio \GPIO3_3~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO3_3~input_o ),
	.regout(),
	.padio(GPIO3_3));
defparam \GPIO3_3~input .CFG_KEEP = 2'b00;
// defparam \GPIO3_3~input .simulate_z_as = "z";

// Location: IOIBUF_X36_Y0_N0
// alta_io_ibuf \GPIO3_4~input (
alta_rio \GPIO3_4~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO3_4~input_o ),
	.regout(),
	.padio(GPIO3_4));
defparam \GPIO3_4~input .CFG_KEEP = 2'b00;
// defparam \GPIO3_4~input .simulate_z_as = "z";

// Location: IOOBUF_X36_Y0_N1
// alta_io_obuf \GPIO2_5~output (
alta_rio \GPIO2_5~output (
	.datain(\rv32.gpio2_io_out_data[5] ),
	.oe(\rv32.gpio2_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_5));
defparam \GPIO2_5~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_5~output .open_drain_output = "false";

// Location: IOOBUF_X38_Y0_N0
// alta_io_obuf \GPIO2_6~output (
alta_rio \GPIO2_6~output (
	.datain(\rv32.gpio2_io_out_data[6] ),
	.oe(\rv32.gpio2_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_6));
defparam \GPIO2_6~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_6~output .open_drain_output = "false";

// Location: IOOBUF_X38_Y0_N1
// alta_io_obuf \GPIO2_4~output (
alta_rio \GPIO2_4~output (
	.datain(\rv32.gpio2_io_out_data[4] ),
	.oe(\rv32.gpio2_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_4));
defparam \GPIO2_4~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_4~output .open_drain_output = "false";

// Location: IOOBUF_X40_Y0_N0
// alta_io_obuf \GPIO6_0~output (
alta_rio \GPIO6_0~output (
	.datain(\rv32.gpio6_io_out_data[0] ),
	.oe(\rv32.gpio6_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO6_0));
defparam \GPIO6_0~output .CFG_KEEP = 2'b00;
// defparam \GPIO6_0~output .open_drain_output = "false";

// Location: IOOBUF_X40_Y0_N1
// alta_io_obuf \GPIO6_4~output (
alta_rio \GPIO6_4~output (
	.datain(\rv32.gpio6_io_out_data[4] ),
	.oe(\rv32.gpio6_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO6_4));
defparam \GPIO6_4~output .CFG_KEEP = 2'b00;
// defparam \GPIO6_4~output .open_drain_output = "false";

// Location: IOOBUF_X40_Y0_N2
// alta_io_obuf \GPIO2_3~output (
alta_rio \GPIO2_3~output (
	.datain(\rv32.gpio2_io_out_data[3] ),
	.oe(\rv32.gpio2_io_out_en[3] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_3));
defparam \GPIO2_3~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_3~output .open_drain_output = "false";

// Location: IOOBUF_X40_Y0_N3
// alta_io_obuf \GPIO6_2~output (
alta_rio \GPIO6_2~output (
	.datain(\rv32.gpio6_io_out_data[2] ),
	.oe(\rv32.gpio6_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO6_2));
defparam \GPIO6_2~output .CFG_KEEP = 2'b00;
// defparam \GPIO6_2~output .open_drain_output = "false";

// Location: IOOBUF_X43_Y0_N0
// alta_io_obuf \uart15_tx~output (
alta_rio \uart15_tx~output (
	.datain(\rv32.gpio7_io_out_data[6] ),
	.oe(gpio8_io_out_en[7]),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(uart15_tx));
defparam \uart15_tx~output .CFG_KEEP = 2'b00;
// defparam \uart15_tx~output .open_drain_output = "false";

// Location: IOOBUF_X43_Y0_N1
// alta_io_obuf \GPIO2_7~output (
alta_rio \GPIO2_7~output (
	.datain(\rv32.gpio2_io_out_data[7] ),
	.oe(\rv32.gpio2_io_out_en[7] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_7));
defparam \GPIO2_7~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_7~output .open_drain_output = "false";

// Location: IOIBUF_X45_Y0_N0
// alta_io_ibuf \SIM_IO[1]~input (
// Location: IOOBUF_X45_Y0_N0
// alta_io_obuf \SIM_IO[1]~output (
alta_rio \SIM_IO[1]~output (
	.datain(!\macro_inst|u_uart[0]|u_tx[1]|uart_txd~q ),
	.oe(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[1]~input_o ),
	.regout(),
	.padio(SIM_IO[1]));
defparam \SIM_IO[1]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[1]~input .simulate_z_as = "z";
// defparam \SIM_IO[1]~output .open_drain_output = "false";

// Location: IOOBUF_X45_Y0_N1
// alta_io_obuf \UART4_UARTTXD~output (
alta_rio \UART4_UARTTXD~output (
	.datain(\rv32.gpio8_io_out_data[6] ),
	.oe(\rv32.gpio8_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(UART4_UARTTXD));
defparam \UART4_UARTTXD~output .CFG_KEEP = 2'b00;
// defparam \UART4_UARTTXD~output .open_drain_output = "false";

// Location: IOIBUF_X45_Y0_N2
// alta_io_ibuf \SIM_IO_15~input (
// Location: IOOBUF_X45_Y0_N2
// alta_io_obuf \SIM_IO_15~output (
alta_rio \SIM_IO_15~output (
	.datain(\rv32.gpio7_io_out_data[6] ),
	.oe(\macro_inst|SIM_IO_15~1_combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO_15~input_o ),
	.regout(),
	.padio(SIM_IO_15));
defparam \SIM_IO_15~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO_15~input .simulate_z_as = "z";
// defparam \SIM_IO_15~output .open_drain_output = "false";

// Location: IOIBUF_X47_Y0_N0
// alta_io_ibuf \SIM_IO_12~input (
// Location: IOOBUF_X47_Y0_N0
// alta_io_obuf \SIM_IO_12~output (
alta_rio \SIM_IO_12~output (
	.datain(\rv32.gpio8_io_out_data[0] ),
	.oe(\macro_inst|SIM_IO_12~1_combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO_12~input_o ),
	.regout(),
	.padio(SIM_IO_12));
defparam \SIM_IO_12~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO_12~input .simulate_z_as = "z";
// defparam \SIM_IO_12~output .open_drain_output = "false";

// Location: IOIBUF_X47_Y0_N1
// alta_io_ibuf \GPIO6_6~input (
// Location: IOOBUF_X47_Y0_N1
// alta_io_obuf \GPIO6_6~output (
alta_rio \GPIO6_6~output (
	.datain(\rv32.gpio6_io_out_data[6] ),
	.oe(\rv32.gpio6_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO6_6~input_o ),
	.regout(),
	.padio(GPIO6_6));
defparam \GPIO6_6~output .CFG_KEEP = 2'b00;
// defparam \GPIO6_6~input .simulate_z_as = "z";
// defparam \GPIO6_6~output .open_drain_output = "false";

// Location: IOIBUF_X47_Y0_N2
// alta_io_ibuf \SIM_IO_13~input (
// Location: IOOBUF_X47_Y0_N2
// alta_io_obuf \SIM_IO_13~output (
alta_rio \SIM_IO_13~output (
	.datain(\rv32.gpio8_io_out_data[2] ),
	.oe(\macro_inst|SIM_IO_13~1_combout ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO_13~input_o ),
	.regout(),
	.padio(SIM_IO_13));
defparam \SIM_IO_13~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO_13~input .simulate_z_as = "z";
// defparam \SIM_IO_13~output .open_drain_output = "false";

// Location: IOIBUF_X51_Y0_N0
// alta_io_ibuf \GPIO9_1~input (
// Location: IOOBUF_X51_Y0_N0
// alta_io_obuf \GPIO9_1~output (
alta_rio \GPIO9_1~output (
	.datain(\rv32.gpio9_io_out_data[1] ),
	.oe(\rv32.gpio9_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO9_1~input_o ),
	.regout(),
	.padio(GPIO9_1));
defparam \GPIO9_1~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_1~input .simulate_z_as = "z";
// defparam \GPIO9_1~output .open_drain_output = "false";

// Location: IOOBUF_X51_Y0_N1
// alta_io_obuf \GPIO9_5~output (
alta_rio \GPIO9_5~output (
	.datain(\rv32.gpio9_io_out_data[5] ),
	.oe(\rv32.gpio9_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_5));
defparam \GPIO9_5~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_5~output .open_drain_output = "false";

// Location: IOOBUF_X51_Y0_N2
// alta_io_obuf \UART3_UARTTXD~output (
alta_rio \UART3_UARTTXD~output (
	.datain(\rv32.gpio8_io_out_data[4] ),
	.oe(\rv32.gpio8_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(UART3_UARTTXD));
defparam \UART3_UARTTXD~output .CFG_KEEP = 2'b00;
// defparam \UART3_UARTTXD~output .open_drain_output = "false";

// Location: IOOBUF_X51_Y0_N3
// alta_io_obuf \GPIO9_0~output (
alta_rio \GPIO9_0~output (
	.datain(\rv32.gpio9_io_out_data[0] ),
	.oe(\rv32.gpio9_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_0));
defparam \GPIO9_0~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_0~output .open_drain_output = "false";

// Location: IOIBUF_X53_Y0_N0
// alta_io_ibuf \SIM_IO[0]~input (
// Location: IOOBUF_X53_Y0_N0
// alta_io_obuf \SIM_IO[0]~output (
alta_rio \SIM_IO[0]~output (
	.datain(!\macro_inst|u_uart[0]|u_tx[0]|uart_txd~q ),
	.oe(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[0]~input_o ),
	.regout(),
	.padio(SIM_IO[0]));
defparam \SIM_IO[0]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[0]~input .simulate_z_as = "z";
// defparam \SIM_IO[0]~output .open_drain_output = "false";

// Location: IOOBUF_X53_Y0_N1
// alta_io_obuf \GPIO9_2~output (
alta_rio \GPIO9_2~output (
	.datain(\rv32.gpio9_io_out_data[2] ),
	.oe(\rv32.gpio9_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_2));
defparam \GPIO9_2~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_2~output .open_drain_output = "false";

// Location: IOOBUF_X53_Y0_N2
// alta_io_obuf \GPIO9_7~output (
alta_rio \GPIO9_7~output (
	.datain(\rv32.gpio9_io_out_data[7] ),
	.oe(\rv32.gpio9_io_out_en[7] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_7));
defparam \GPIO9_7~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_7~output .open_drain_output = "false";

// Location: IOOBUF_X53_Y0_N3
// alta_io_obuf \GPIO9_6~output (
alta_rio \GPIO9_6~output (
	.datain(\rv32.gpio9_io_out_data[6] ),
	.oe(\rv32.gpio9_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_6));
defparam \GPIO9_6~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_6~output .open_drain_output = "false";

// Location: IOIBUF_X56_Y0_N1
// alta_io_ibuf \SIM_IO[11]~input (
// Location: IOOBUF_X56_Y0_N1
// alta_io_obuf \SIM_IO[11]~output (
alta_rio \SIM_IO[11]~output (
	.datain(!\macro_inst|u_uart[1]|u_tx[5]|uart_txd~q ),
	.oe(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[11]~input_o ),
	.regout(),
	.padio(SIM_IO[11]));
defparam \SIM_IO[11]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[11]~input .simulate_z_as = "z";
// defparam \SIM_IO[11]~output .open_drain_output = "false";

// Location: IOIBUF_X56_Y0_N2
// alta_io_ibuf \SIM_IO[5]~input (
// Location: IOOBUF_X56_Y0_N2
// alta_io_obuf \SIM_IO[5]~output (
alta_rio \SIM_IO[5]~output (
	.datain(!\macro_inst|u_uart[0]|u_tx[5]|uart_txd~q ),
	.oe(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[5]~input_o ),
	.regout(),
	.padio(SIM_IO[5]));
defparam \SIM_IO[5]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[5]~input .simulate_z_as = "z";
// defparam \SIM_IO[5]~output .open_drain_output = "false";

// Location: IOIBUF_X56_Y0_N3
// alta_io_ibuf \SIM_IO[7]~input (
// Location: IOOBUF_X56_Y0_N3
// alta_io_obuf \SIM_IO[7]~output (
alta_rio \SIM_IO[7]~output (
	.datain(!\macro_inst|u_uart[1]|u_tx[1]|uart_txd~q ),
	.oe(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[7]~input_o ),
	.regout(),
	.padio(SIM_IO[7]));
defparam \SIM_IO[7]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[7]~input .simulate_z_as = "z";
// defparam \SIM_IO[7]~output .open_drain_output = "false";

// Location: IOIBUF_X58_Y0_N0
// alta_io_ibuf \SIM_IO[6]~input (
// Location: IOOBUF_X58_Y0_N0
// alta_io_obuf \SIM_IO[6]~output (
alta_rio \SIM_IO[6]~output (
	.datain(!\macro_inst|u_uart[1]|u_tx[0]|uart_txd~q ),
	.oe(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[6]~input_o ),
	.regout(),
	.padio(SIM_IO[6]));
defparam \SIM_IO[6]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[6]~input .simulate_z_as = "z";
// defparam \SIM_IO[6]~output .open_drain_output = "false";

// Location: IOIBUF_X58_Y0_N1
// alta_io_ibuf \SIM_IO[8]~input (
// Location: IOOBUF_X58_Y0_N1
// alta_io_obuf \SIM_IO[8]~output (
alta_rio \SIM_IO[8]~output (
	.datain(!\macro_inst|u_uart[1]|u_tx[2]|uart_txd~q ),
	.oe(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[8]~input_o ),
	.regout(),
	.padio(SIM_IO[8]));
defparam \SIM_IO[8]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[8]~input .simulate_z_as = "z";
// defparam \SIM_IO[8]~output .open_drain_output = "false";

// Location: IOOBUF_X58_Y0_N2
// alta_io_obuf \GPIO1_1~output (
alta_rio \GPIO1_1~output (
	.datain(\rv32.gpio1_io_out_data[1] ),
	.oe(\rv32.gpio1_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_1));
defparam \GPIO1_1~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_1~output .open_drain_output = "false";

// Location: IOOBUF_X58_Y0_N3
// alta_io_obuf \GPIO1_2~output (
alta_rio \GPIO1_2~output (
	.datain(\rv32.gpio1_io_out_data[2] ),
	.oe(\rv32.gpio1_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_2));
defparam \GPIO1_2~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_2~output .open_drain_output = "false";

// Location: IOOBUF_X60_Y0_N0
// alta_io_obuf \GPIO1_0~output (
alta_rio \GPIO1_0~output (
	.datain(\rv32.gpio1_io_out_data[0] ),
	.oe(\rv32.gpio1_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_0));
defparam \GPIO1_0~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_0~output .open_drain_output = "false";

// Location: IOIBUF_X60_Y0_N1
// alta_io_ibuf \SIM_IO[3]~input (
// Location: IOOBUF_X60_Y0_N1
// alta_io_obuf \SIM_IO[3]~output (
alta_rio \SIM_IO[3]~output (
	.datain(!\macro_inst|u_uart[0]|u_tx[3]|uart_txd~q ),
	.oe(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[3]~input_o ),
	.regout(),
	.padio(SIM_IO[3]));
defparam \SIM_IO[3]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[3]~input .simulate_z_as = "z";
// defparam \SIM_IO[3]~output .open_drain_output = "false";

// Location: IOIBUF_X60_Y0_N2
// alta_io_ibuf \SIM_IO[2]~input (
// Location: IOOBUF_X60_Y0_N2
// alta_io_obuf \SIM_IO[2]~output (
alta_rio \SIM_IO[2]~output (
	.datain(!\macro_inst|u_uart[0]|u_tx[2]|uart_txd~q ),
	.oe(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[2]~input_o ),
	.regout(),
	.padio(SIM_IO[2]));
defparam \SIM_IO[2]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[2]~input .simulate_z_as = "z";
// defparam \SIM_IO[2]~output .open_drain_output = "false";

// Location: IOIBUF_X60_Y0_N3
// alta_io_ibuf \SIM_IO[9]~input (
// Location: IOOBUF_X60_Y0_N3
// alta_io_obuf \SIM_IO[9]~output (
alta_rio \SIM_IO[9]~output (
	.datain(!\macro_inst|u_uart[1]|u_tx[3]|uart_txd~q ),
	.oe(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[9]~input_o ),
	.regout(),
	.padio(SIM_IO[9]));
defparam \SIM_IO[9]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[9]~input .simulate_z_as = "z";
// defparam \SIM_IO[9]~output .open_drain_output = "false";

// Location: IOOBUF_X62_Y0_N0
// alta_io_obuf \GPIO2_1~output (
alta_rio \GPIO2_1~output (
	.datain(\rv32.gpio2_io_out_data[1] ),
	.oe(\rv32.gpio2_io_out_en[1] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_1));
defparam \GPIO2_1~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_1~output .open_drain_output = "false";

// Location: IOOBUF_X62_Y0_N1
// alta_io_obuf \GPIO2_2~output (
alta_rio \GPIO2_2~output (
	.datain(\rv32.gpio2_io_out_data[2] ),
	.oe(\rv32.gpio2_io_out_en[2] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_2));
defparam \GPIO2_2~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_2~output .open_drain_output = "false";

// Location: IOIBUF_X62_Y0_N2
// alta_io_ibuf \SIM_IO[4]~input (
// Location: IOOBUF_X62_Y0_N2
// alta_io_obuf \SIM_IO[4]~output (
alta_rio \SIM_IO[4]~output (
	.datain(!\macro_inst|u_uart[0]|u_tx[4]|uart_txd~q ),
	.oe(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[4]~input_o ),
	.regout(),
	.padio(SIM_IO[4]));
defparam \SIM_IO[4]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[4]~input .simulate_z_as = "z";
// defparam \SIM_IO[4]~output .open_drain_output = "false";

// Location: IOIBUF_X62_Y0_N3
// alta_io_ibuf \SIM_IO[10]~input (
// Location: IOOBUF_X62_Y0_N3
// alta_io_obuf \SIM_IO[10]~output (
alta_rio \SIM_IO[10]~output (
	.datain(!\macro_inst|u_uart[1]|u_tx[4]|uart_txd~q ),
	.oe(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\SIM_IO[10]~input_o ),
	.regout(),
	.padio(SIM_IO[10]));
defparam \SIM_IO[10]~output .CFG_KEEP = 2'b00;
// defparam \SIM_IO[10]~input .simulate_z_as = "z";
// defparam \SIM_IO[10]~output .open_drain_output = "false";

// Location: IOOBUF_X67_Y0_N0
// alta_io_obuf \GPIO1_5~output (
alta_rio \GPIO1_5~output (
	.datain(\rv32.gpio1_io_out_data[5] ),
	.oe(\rv32.gpio1_io_out_en[5] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_5));
defparam \GPIO1_5~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_5~output .open_drain_output = "false";

// Location: IOOBUF_X67_Y0_N1
// alta_io_obuf \GPIO1_7~output (
alta_rio \GPIO1_7~output (
	.datain(\rv32.gpio1_io_out_data[7] ),
	.oe(\rv32.gpio1_io_out_en[7] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_7));
defparam \GPIO1_7~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_7~output .open_drain_output = "false";

// Location: IOOBUF_X67_Y0_N2
// alta_io_obuf \GPIO1_6~output (
alta_rio \GPIO1_6~output (
	.datain(\rv32.gpio1_io_out_data[6] ),
	.oe(\rv32.gpio1_io_out_en[6] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_6));
defparam \GPIO1_6~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_6~output .open_drain_output = "false";

// Location: IOOBUF_X67_Y0_N3
// alta_io_obuf \GPIO1_4~output (
alta_rio \GPIO1_4~output (
	.datain(\rv32.gpio1_io_out_data[4] ),
	.oe(\rv32.gpio1_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_4));
defparam \GPIO1_4~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_4~output .open_drain_output = "false";

// Location: IOOBUF_X69_Y0_N0
// alta_io_obuf \GPIO2_0~output (
alta_rio \GPIO2_0~output (
	.datain(\rv32.gpio2_io_out_data[0] ),
	.oe(\rv32.gpio2_io_out_en[0] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO2_0));
defparam \GPIO2_0~output .CFG_KEEP = 2'b00;
// defparam \GPIO2_0~output .open_drain_output = "false";

// Location: IOOBUF_X69_Y0_N1
// alta_io_obuf \GPIO1_3~output (
alta_rio \GPIO1_3~output (
	.datain(\rv32.gpio1_io_out_data[3] ),
	.oe(\rv32.gpio1_io_out_en[3] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO1_3));
defparam \GPIO1_3~output .CFG_KEEP = 2'b00;
// defparam \GPIO1_3~output .open_drain_output = "false";

// Location: IOOBUF_X71_Y0_N0
// alta_io_obuf \GPIO9_4~output (
alta_rio \GPIO9_4~output (
	.datain(\rv32.gpio9_io_out_data[4] ),
	.oe(\rv32.gpio9_io_out_en[4] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_4));
defparam \GPIO9_4~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_4~output .open_drain_output = "false";

// Location: IOOBUF_X71_Y0_N3
// alta_io_obuf \GPIO9_3~output (
alta_rio \GPIO9_3~output (
	.datain(\rv32.gpio9_io_out_data[3] ),
	.oe(\rv32.gpio9_io_out_en[3] ),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(),
	.regout(),
	.padio(GPIO9_3));
defparam \GPIO9_3~output .CFG_KEEP = 2'b00;
// defparam \GPIO9_3~output .open_drain_output = "false";

// Location: IOIBUF_X94_Y31_N0
// alta_io_ibuf \GPIO3_0~input (
alta_rio \GPIO3_0~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\GPIO3_0~input_o ),
	.regout(),
	.padio(GPIO3_0));
defparam \GPIO3_0~input .CFG_KEEP = 2'b00;
// defparam \GPIO3_0~input .simulate_z_as = "z";

// Location: IOIBUF_X94_Y31_N1
// alta_io_ibuf \PIN_OSC~input (
alta_rio \PIN_OSC~input (
	.datain(gnd),
	.oe(gnd),
	.outclk(gnd),
	.outclkena(vcc),
	.inclk(gnd),
	.inclkena(vcc),
	.areset(gnd),
	.sreset(gnd),
	.combout(\PIN_OSC~input_o ),
	.regout(),
	.padio(PIN_OSC));
defparam \PIN_OSC~input .CFG_KEEP = 2'b00;
// defparam \PIN_OSC~input .simulate_z_as = "z";

// Location: PLL_1
alta_pllve \pll_inst|auto_generated|pll1 (
	.clkin(\PIN_HSE~input_o ),
	.clkfb(\pll_inst|auto_generated|pll1~FBOUT ),
	.pfden(vcc),
	.resetn(!\PLL_ENABLE~combout ),
	.clkout0(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkout1(\pll_inst|auto_generated|pll1_CLK_bus [1]),
	.clkout2(\pll_inst|auto_generated|pll1_CLK_bus [2]),
	.clkout3(\pll_inst|auto_generated|pll1_CLK_bus [3]),
	.clkout4(\pll_inst|auto_generated|pll1_CLK_bus [4]),
	.phasecounterselect({gnd, gnd, gnd}),
	.phaseupdown(gnd),
	.phasestep(gnd),
	.scanclk(gnd),
	.scanclkena(vcc),
	.scandata(gnd),
	.configupdate(gnd),
	.scandataout(),
	.scandone(),
	.phasedone(),
	.clkfbout(\pll_inst|auto_generated|pll1~FBOUT ),
	.lock(\auto_generated_inst.hbo_13_1797ab7b230f061a_bp ));
defparam \pll_inst|auto_generated|pll1 .CLKDIV0_EN      = 1'h1;
defparam \pll_inst|auto_generated|pll1 .CLKDIV1_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV2_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKDIV3_EN      = 1'h1;
defparam \pll_inst|auto_generated|pll1 .CLKDIV4_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_BYPASS    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_DEL       = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKFB_HIGH      = 8'h1D;
defparam \pll_inst|auto_generated|pll1 .CLKFB_LOW       = 8'h1D;
defparam \pll_inst|auto_generated|pll1 .CLKFB_PHASE     = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKFB_TRIM      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKIN_BYPASS    = 1'h1;
defparam \pll_inst|auto_generated|pll1 .CLKIN_HIGH      = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKIN_LOW       = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKIN_TRIM      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_HIGH    = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_LOW     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT0_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT1_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT2_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_HIGH    = 8'h01;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_LOW     = 8'h01;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT3_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_BYPASS  = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_CASCADE = 1'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_DEL     = 8'h00;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_HIGH    = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_LOW     = 8'hFF;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_PHASE   = 3'h0;
defparam \pll_inst|auto_generated|pll1 .CLKOUT4_TRIM    = 1'h0;
defparam \pll_inst|auto_generated|pll1 .FBDELAY_VAL     = 3'h4;
defparam \pll_inst|auto_generated|pll1 .FEEDBACK_MODE   = 3'h4;
defparam \pll_inst|auto_generated|pll1 .PLLOUTN_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .PLLOUTP_EN      = 1'h0;
defparam \pll_inst|auto_generated|pll1 .VCO_POST_DIV    = 1'h1;
//defparam \pll_inst|auto_generated|pll1 .auto_settings = "false";
//defparam \pll_inst|auto_generated|pll1 .bandwidth_type = "medium";
//defparam \pll_inst|auto_generated|pll1 .c0_high = 1;
//defparam \pll_inst|auto_generated|pll1 .c0_initial = 1;
//defparam \pll_inst|auto_generated|pll1 .c0_low = 1;
//defparam \pll_inst|auto_generated|pll1 .c0_mode = "even";
//defparam \pll_inst|auto_generated|pll1 .c0_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_high = 2;
//defparam \pll_inst|auto_generated|pll1 .c1_initial = 1;
//defparam \pll_inst|auto_generated|pll1 .c1_low = 2;
//defparam \pll_inst|auto_generated|pll1 .c1_mode = "even";
//defparam \pll_inst|auto_generated|pll1 .c1_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c1_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .c2_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c2_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c2_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .c3_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c3_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c3_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .c4_high = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_initial = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_low = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_mode = "bypass";
//defparam \pll_inst|auto_generated|pll1 .c4_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .c4_use_casc_in = "off";
//defparam \pll_inst|auto_generated|pll1 .charge_pump_current_bits = 1;
//defparam \pll_inst|auto_generated|pll1 .clk0_counter = "c0";
//defparam \pll_inst|auto_generated|pll1 .clk0_divide_by = 1;
//defparam \pll_inst|auto_generated|pll1 .clk0_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk0_multiply_by = 30;
//defparam \pll_inst|auto_generated|pll1 .clk0_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk1_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk1_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk1_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk1_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk1_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk2_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk2_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk2_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk2_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk2_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk3_counter = "c1";
//defparam \pll_inst|auto_generated|pll1 .clk3_divide_by = 1;
//defparam \pll_inst|auto_generated|pll1 .clk3_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk3_multiply_by = 15;
//defparam \pll_inst|auto_generated|pll1 .clk3_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .clk4_counter = "unused";
//defparam \pll_inst|auto_generated|pll1 .clk4_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk4_duty_cycle = 50;
//defparam \pll_inst|auto_generated|pll1 .clk4_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .clk4_phase_shift = 0;
//defparam \pll_inst|auto_generated|pll1 .compensate_clock = "clock0";
//defparam \pll_inst|auto_generated|pll1 .inclk0_input_frequency = 125000;
//defparam \pll_inst|auto_generated|pll1 .inclk1_input_frequency = 0;
//defparam \pll_inst|auto_generated|pll1 .loop_filter_c_bits = 0;
//defparam \pll_inst|auto_generated|pll1 .loop_filter_r_bits = 19;
//defparam \pll_inst|auto_generated|pll1 .m = 60;
//defparam \pll_inst|auto_generated|pll1 .m_initial = 1;
//defparam \pll_inst|auto_generated|pll1 .m_ph = 0;
//defparam \pll_inst|auto_generated|pll1 .n = 1;
//defparam \pll_inst|auto_generated|pll1 .operation_mode = "normal";
//defparam \pll_inst|auto_generated|pll1 .pfd_max = 200000;
//defparam \pll_inst|auto_generated|pll1 .pfd_min = 3076;
//defparam \pll_inst|auto_generated|pll1 .pll_compensation_delay = 7538;
//defparam \pll_inst|auto_generated|pll1 .self_reset_on_loss_lock = "off";
//defparam \pll_inst|auto_generated|pll1 .simulation_type = "timing";
//defparam \pll_inst|auto_generated|pll1 .switch_over_type = "auto";
//defparam \pll_inst|auto_generated|pll1 .vco_center = 1538;
//defparam \pll_inst|auto_generated|pll1 .vco_divide_by = 0;
//defparam \pll_inst|auto_generated|pll1 .vco_frequency_control = "auto";
//defparam \pll_inst|auto_generated|pll1 .vco_max = 3333;
//defparam \pll_inst|auto_generated|pll1 .vco_min = 1538;
//defparam \pll_inst|auto_generated|pll1 .vco_multiply_by = 0;
//defparam \pll_inst|auto_generated|pll1 .vco_phase_shift_step = 260;
//defparam \pll_inst|auto_generated|pll1 .vco_post_scale = 2;

// Location: CLKCTRL_G16
alta_io_gclk \PLL_ENABLE~clkctrl (
	.inclk (\PLL_ENABLE~combout ),
	.outclk(\PLL_ENABLE~clkctrl_outclk ));
//defparam \PLL_ENABLE~clkctrl .clock_type = "global clock";
//defparam \PLL_ENABLE~clkctrl .ena_register_mode = "none";

// Location: CLKCTRL_G17
alta_io_gclk \sys_resetn~clkctrl (
	.inclk (\sys_resetn~combout ),
	.outclk(\sys_resetn~clkctrl_outclk ));
//defparam \sys_resetn~clkctrl .clock_type = "global clock";
//defparam \sys_resetn~clkctrl .ena_register_mode = "none";

// Location: CLKCTRL_G3
alta_gclksw \gclksw_inst|gclk_switch__alta_gclksw (
	.resetn(vcc),
	.clkin0(\PIN_HSI~input_o ),
	.clkin1(1'bx),
	.clkin2(\pll_inst|auto_generated|pll1_CLK_bus [0]),
	.clkin3(1'bx),
	.select({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
	.clkout(\gclksw_inst|gclk_switch__alta_gclksw__clkout ));

// Location: CLKCTRL_G3
alta_io_gclk \gclksw_inst|gclk_switch (
	.inclk (\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
	.outclk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ));
//defparam \gclksw_inst|gclk_switch .clock_type = "global clock";
//defparam \gclksw_inst|gclk_switch .ena_register_mode = "none";

// Location: CLKCTRL_G4
alta_io_gclk bus_clk_gclk(
	.inclk (\pll_inst|auto_generated|pll1_CLK_bus [3]),
	.outclk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ));
//defparam bus_clk_gclk.clock_type = "global clock";
//defparam bus_clk_gclk.ena_register_mode = "falling edge";

// Location: FF_X43_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] (
// Location: LCCOMB_X43_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always3~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout_X43_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X43_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .mask = 16'hABAF;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Selector4~4_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector4~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .mask = 16'hFF10;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Selector2~4_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .mask = 16'h0E00;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] (
// Location: LCCOMB_X43_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Add4~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout_X43_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X43_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .mask = 16'hFF15;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY (
// Location: LCCOMB_X43_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|Selector4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always3~2 (
// Location: FF_X43_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X43_Y1_GND),
	.SyncReset(SyncReset_X43_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X43_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always3~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .mask = 16'hAA00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X43_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector2~6 (
// Location: FF_X43_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Selector2~5_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|Selector2~3_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .mask = 16'h00EA;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .mask = 16'h4C4C;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .mask = 16'hE0C0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always3~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector2~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .mask = 16'hF0E0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always3~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always3~1 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always3~1 .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] (
// Location: LCCOMB_X43_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always3~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Add4~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout_X43_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X43_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .mask = 16'hEFAB;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .mask = 16'h8080;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector1~0 (
// Location: FF_X43_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .mask = 16'h00DC;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP (
// Location: LCCOMB_X43_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X43_Y1_N0
alta_clkenctrl clken_ctrl_X43_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout_X43_Y1_SIG_SIG ));
defparam clken_ctrl_X43_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X43_Y1_N0
alta_asyncctrl asyncreset_ctrl_X43_Y1_N0(.Din(), .Dout(AsyncReset_X43_Y1_GND));
defparam asyncreset_ctrl_X43_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X43_Y1_N1
alta_clkenctrl clken_ctrl_X43_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y1_SIG_VCC ));
defparam clken_ctrl_X43_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X43_Y1_N1
alta_asyncctrl asyncreset_ctrl_X43_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y1_SIG ));
defparam asyncreset_ctrl_X43_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X43_Y1_N0
alta_syncctrl syncreset_ctrl_X43_Y1(.Din(), .Dout(SyncReset_X43_Y1_GND));
defparam syncreset_ctrl_X43_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X43_Y1_N1
alta_syncctrl syncload_ctrl_X43_Y1(.Din(), .Dout(SyncLoad_X43_Y1_VCC));
defparam syncload_ctrl_X43_Y1.SyncCtrlMux = 2'b01;
// Location: FF_X43_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] (
// Location: LCCOMB_X43_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] (
// Location: LCCOMB_X43_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_in [3]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_in [4]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .mask = 16'h0F0F;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Add1~0 (
// Location: FF_X43_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_in [4]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_in [3]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_in [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .mask = 16'h0CCF;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] (
// Location: LCCOMB_X43_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_in[2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_in [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_in[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_in [2]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[2] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] (
// Location: LCCOMB_X43_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [1]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(SyncReset_X43_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X43_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: FF_X43_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] (
// Location: LCCOMB_X43_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] (
// Location: LCCOMB_X43_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_in[3]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_in [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_in[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_in [3]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[3] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [4]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(SyncReset_X43_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X43_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: FF_X43_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] (
// Location: LCCOMB_X43_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] (
// Location: LCCOMB_X43_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .mask = 16'h1000;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always4~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X43_Y2_N0
alta_clkenctrl clken_ctrl_X43_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[4]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|always4~2_combout_X43_Y2_SIG_SIG ));
defparam clken_ctrl_X43_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X43_Y2_N0
alta_asyncctrl asyncreset_ctrl_X43_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y2_SIG ));
defparam asyncreset_ctrl_X43_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X43_Y2_N1
alta_clkenctrl clken_ctrl_X43_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X43_Y2_SIG_SIG ));
defparam clken_ctrl_X43_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X43_Y2_N0
alta_syncctrl syncreset_ctrl_X43_Y2(.Din(), .Dout(SyncReset_X43_Y2_GND));
defparam syncreset_ctrl_X43_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X43_Y2_N1
alta_syncctrl syncload_ctrl_X43_Y2(.Din(), .Dout(SyncLoad_X43_Y2_VCC));
defparam syncload_ctrl_X43_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X43_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] (
// Location: LCCOMB_X43_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Add4~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|always3~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout_X43_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X43_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .mask = 16'hFFD1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] (
// Location: LCCOMB_X43_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|Add4~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout_X43_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X43_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .mask = 16'hFF07;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Add4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Add4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .mask = 16'h0F1E;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] (
// Location: LCCOMB_X43_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|always3~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout_X43_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X43_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .mask = 16'hABAF;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector1~0 (
// Location: FF_X43_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector0~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector0~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .mask = 16'h4454;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|always4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .mask = 16'h1000;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always3~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|always3~1 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always3~1 .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] (
// Location: LCCOMB_X43_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Add4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(AsyncReset_X43_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .mask = 16'h0074;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: FF_X43_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] (
// Location: LCCOMB_X43_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ),
	.SyncReset(SyncReset_X43_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout__SyncLoad_X43_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X43_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] (
// Location: LCCOMB_X43_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ),
	.SyncReset(SyncReset_X43_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout__SyncLoad_X43_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X43_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] (
// Location: LCCOMB_X43_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ),
	.SyncReset(SyncReset_X43_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout__SyncLoad_X43_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X43_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] (
// Location: LCCOMB_X43_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [3]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ),
	.SyncReset(SyncReset_X43_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout__SyncLoad_X43_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .mask = 16'h5A5A;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X43_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Add4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Add4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [2]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .mask = 16'h555A;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Add4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Add4~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always2~1 (
// Location: FF_X43_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_bit (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_bit (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .mask = 16'h8080;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_bit .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X43_Y3_N0
alta_clkenctrl clken_ctrl_X43_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout_X43_Y3_SIG_SIG ));
defparam clken_ctrl_X43_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X43_Y3_N0
alta_asyncctrl asyncreset_ctrl_X43_Y3_N0(.Din(), .Dout(AsyncReset_X43_Y3_GND));
defparam asyncreset_ctrl_X43_Y3_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X43_Y3_N1
alta_clkenctrl clken_ctrl_X43_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y3_SIG_VCC ));
defparam clken_ctrl_X43_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y3_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X43_Y3_N1
alta_asyncctrl asyncreset_ctrl_X43_Y3_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y3_SIG ));
defparam asyncreset_ctrl_X43_Y3_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X43_Y3_N0
alta_syncctrl syncreset_ctrl_X43_Y3(.Din(), .Dout(SyncReset_X43_Y3_GND));
defparam syncreset_ctrl_X43_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X43_Y3_N1
alta_syncctrl syncload_ctrl_X43_Y3(.Din(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout ), .Dout(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout__SyncLoad_X43_Y3_SIG ));
defparam syncload_ctrl_X43_Y3.SyncCtrlMux = 2'b10;
// Location: FF_X43_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY (
// Location: LCCOMB_X43_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Selector3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|Selector4~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .mask = 16'hB9B1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector1~0 (
// Location: FF_X43_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Selector2~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .mask = 16'h2232;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Selector4~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector4~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .mask = 16'hABAA;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector2~6 (
// Location: FF_X43_Y4_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Selector2~5_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|Selector2~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .mask = 16'h0E0A;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Selector2~3_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always3~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .mask = 16'hCCC8;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .mask = 16'h00E0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector0~0 (
// Location: FF_X43_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Selector2~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .mask = 16'h3033;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X43_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .mask = 16'hEC00;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X43_Y4_N0
alta_clkenctrl clken_ctrl_X43_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X43_Y4_SIG_VCC ));
defparam clken_ctrl_X43_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X43_Y4_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X43_Y4_N0
alta_asyncctrl asyncreset_ctrl_X43_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X43_Y4_SIG ));
defparam asyncreset_ctrl_X43_Y4_N0.AsyncCtrlMux = 2'b10;
// Location: FF_X44_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] (
// Location: LCCOMB_X44_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] (
// Location: LCCOMB_X44_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Add4~1 (
// Location: FF_X44_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y1_SIG ),
	.SyncReset(SyncReset_X44_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Add4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .mask = 16'h11EE;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Add4~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .mask = 16'h1302;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt~1 .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] (
// Location: LCCOMB_X44_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Selector4~2_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .mask = 16'hC0C0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] (
// Location: LCCOMB_X44_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] (
// Location: LCCOMB_X44_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] (
// Location: LCCOMB_X44_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Add4~2 (
// Location: FF_X44_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y1_SIG ),
	.SyncReset(SyncReset_X44_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Add4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .mask = 16'h55AA;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .mask = 16'hFFF0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt[2]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always11~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always11~1 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [2]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [0]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always11~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~1 .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] (
// Location: LCCOMB_X44_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Add4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Add4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .mask = 16'h01FE;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] (
// Location: LCCOMB_X44_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X44_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X44_Y1_N0
alta_clkenctrl clken_ctrl_X44_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X44_Y1_SIG_SIG ));
defparam clken_ctrl_X44_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X44_Y1_N0
alta_asyncctrl asyncreset_ctrl_X44_Y1_N0(.Din(), .Dout(AsyncReset_X44_Y1_GND));
defparam asyncreset_ctrl_X44_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X44_Y1_N1
alta_clkenctrl clken_ctrl_X44_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[2]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X44_Y1_SIG_SIG ));
defparam clken_ctrl_X44_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X44_Y1_N1
alta_asyncctrl asyncreset_ctrl_X44_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y1_SIG ));
defparam asyncreset_ctrl_X44_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X44_Y1_N0
alta_syncctrl syncreset_ctrl_X44_Y1(.Din(), .Dout(SyncReset_X44_Y1_GND));
defparam syncreset_ctrl_X44_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X44_Y1_N1
alta_syncctrl syncload_ctrl_X44_Y1(.Din(), .Dout(SyncLoad_X44_Y1_VCC));
defparam syncload_ctrl_X44_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X44_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux7~2 (
// Location: FF_X44_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7]~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [7]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux7~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux6~2 (
// Location: FF_X44_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [6]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux6~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux0~2 (
// Location: FF_X44_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [0]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux0~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux2~2 (
// Location: FF_X44_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .mask = 16'hFA50;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux4~2 (
// Location: FF_X44_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .mask = 16'hFA50;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: FF_X44_Y2_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] (
// Location: LCCOMB_X44_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [0]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux3~2 (
// Location: FF_X44_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux3~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .mask = 16'hFA50;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: FF_X44_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] (
// Location: LCCOMB_X44_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always6~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always6~1 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_in [3]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_in [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .mask = 16'h2032;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux5~2 (
// Location: FF_X44_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][5]~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [5]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux5~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: FF_X44_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] (
// Location: LCCOMB_X44_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always11~1 (
// Location: FF_X44_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [3]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [2]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always11~0 (
// Location: FF_X44_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [6]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [4]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: FF_X44_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] (
// Location: LCCOMB_X44_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux1~2 (
// Location: FF_X44_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|fifo[1][1]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y2_GND),
	.SyncReset(SyncReset_X44_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux1~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .mask = 16'hF5A0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X44_Y2_N0
alta_clkenctrl clken_ctrl_X44_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ));
defparam clken_ctrl_X44_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X44_Y2_N0
alta_asyncctrl asyncreset_ctrl_X44_Y2_N0(.Din(), .Dout(AsyncReset_X44_Y2_GND));
defparam asyncreset_ctrl_X44_Y2_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X44_Y2_N1
alta_clkenctrl clken_ctrl_X44_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout_X44_Y2_SIG_SIG ));
defparam clken_ctrl_X44_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X44_Y2_N0
alta_syncctrl syncreset_ctrl_X44_Y2(.Din(), .Dout(SyncReset_X44_Y2_GND));
defparam syncreset_ctrl_X44_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X44_Y2_N1
alta_syncctrl syncload_ctrl_X44_Y2(.Din(), .Dout(SyncLoad_X44_Y2_VCC));
defparam syncload_ctrl_X44_Y2.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X44_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_parity~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .mask = 16'h2080;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .mask = 16'h1000;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector2~0 (
// Location: FF_X44_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Selector4~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: FF_X44_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] (
// Location: LCCOMB_X44_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_sample~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [1]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y3_GND),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_sample~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .mask = 16'h0055;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always6~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|always6~1 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_in [3]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_in [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .mask = 16'h2032;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3 (
// Location: FF_X44_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .mask = 16'hFFAA;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always11~1 (
// Location: FF_X44_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [2]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [3]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~4 (
// Location: FF_X44_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector4~3_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .mask = 16'hCB8B;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always11~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|always11~2 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|always11~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always11~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always11~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_parity~0 (
// Location: FF_X44_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_parity~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Add1~0 (
// Location: FF_X44_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X44_Y3_GND),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .mask = 16'h7711;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always11~0 (
// Location: FF_X44_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [6]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [5]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always2~0 (
// Location: FF_X44_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_baud_cnt [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X44_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~3 (
// Location: FF_X44_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ),
	.SyncReset(SyncReset_X44_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X44_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .mask = 16'h2200;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_shift_reg[5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X44_Y3_N0
alta_clkenctrl clken_ctrl_X44_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[5]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|always4~2_combout_X44_Y3_SIG_SIG ));
defparam clken_ctrl_X44_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X44_Y3_N0
alta_asyncctrl asyncreset_ctrl_X44_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X44_Y3_SIG ));
defparam asyncreset_ctrl_X44_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X44_Y3_N1
alta_clkenctrl clken_ctrl_X44_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[5]|rx_fifo|wrreq~0_combout_X44_Y3_SIG_SIG ));
defparam clken_ctrl_X44_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y3_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X44_Y3_N1
alta_asyncctrl asyncreset_ctrl_X44_Y3_N1(.Din(), .Dout(AsyncReset_X44_Y3_GND));
defparam asyncreset_ctrl_X44_Y3_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X44_Y3_N0
alta_syncctrl syncreset_ctrl_X44_Y3(.Din(), .Dout(SyncReset_X44_Y3_GND));
defparam syncreset_ctrl_X44_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X44_Y3_N1
alta_syncctrl syncload_ctrl_X44_Y3(.Din(), .Dout(SyncLoad_X44_Y3_VCC));
defparam syncload_ctrl_X44_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X44_Y4_N10
// alta_lcell_comb \gpio3_io_in[5] (
alta_slice \gpio3_io_in[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio3_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio3_io_in[5] .mask = 16'h0000;
defparam \gpio3_io_in[5] .mode = "logic";
defparam \gpio3_io_in[5] .modeMux = 1'b0;
defparam \gpio3_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio3_io_in[5] .ShiftMux = 1'b0;
defparam \gpio3_io_in[5] .BypassEn = 1'b0;
defparam \gpio3_io_in[5] .CarryEnb = 1'b1;
defparam \gpio3_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio3_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio3_io_in[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y4_N12
// alta_lcell_comb \gpio3_io_in[6] (
alta_slice \gpio3_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio3_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio3_io_in[6] .mask = 16'h0000;
defparam \gpio3_io_in[6] .mode = "logic";
defparam \gpio3_io_in[6] .modeMux = 1'b0;
defparam \gpio3_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio3_io_in[6] .ShiftMux = 1'b0;
defparam \gpio3_io_in[6] .BypassEn = 1'b0;
defparam \gpio3_io_in[6] .CarryEnb = 1'b1;
defparam \gpio3_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio3_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio3_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X44_Y4_N14
// alta_lcell_comb \gpio3_io_in[7] (
alta_slice \gpio3_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio3_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio3_io_in[7] .mask = 16'h0000;
defparam \gpio3_io_in[7] .mode = "logic";
defparam \gpio3_io_in[7] .modeMux = 1'b0;
defparam \gpio3_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio3_io_in[7] .ShiftMux = 1'b0;
defparam \gpio3_io_in[7] .BypassEn = 1'b0;
defparam \gpio3_io_in[7] .CarryEnb = 1'b1;
defparam \gpio3_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio3_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio3_io_in[7] .SyncLoadMux = 2'bxx;
// Location: FF_X44_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_parity (
// Location: LCCOMB_X44_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_parity (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X44_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X44_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_parity~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_parity .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X44_Y4_N0
alta_clkenctrl clken_ctrl_X44_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X44_Y4_SIG_VCC ));
defparam clken_ctrl_X44_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X44_Y4_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X44_Y4_N0
alta_asyncctrl asyncreset_ctrl_X44_Y4_N0(.Din(), .Dout(AsyncReset_X44_Y4_GND));
defparam asyncreset_ctrl_X44_Y4_N0.AsyncCtrlMux = 2'b00;
// Location: FF_X45_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_parity (
// Location: LCCOMB_X45_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_parity (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_parity~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X45_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_parity~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .mask = 16'h12DE;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] (
// Location: LCCOMB_X45_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout__SyncReset_X45_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X45_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] (
// Location: LCCOMB_X45_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout__SyncReset_X45_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X45_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] (
// Location: LCCOMB_X45_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout__SyncReset_X45_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .mask = 16'h3C3C;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X45_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_parity (
// Location: LCCOMB_X45_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_parity (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_parity~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X45_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_parity~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .mask = 16'h14BE;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] (
// Location: LCCOMB_X45_Y1_N18
// alta_lcell_comb \macro_inst|uart_rxd[1] (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] (
	.A(vcc),
	.B(vcc),
	.C(\SIM_IO[1]~input_o ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [1]),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_in [0]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .mask = 16'h0C0C;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector5~4 (
// Location: FF_X45_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|uart_txd (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|Selector5~2_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|uart_txd~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .mask = 16'h0300;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|always6~0 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|always6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [0]),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_parity~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [0]),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|always6~1 (
// Location: FF_X45_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_bit (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_bit (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|always6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector2~0 (
// Location: FF_X45_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|always0~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .mask = 16'hBA30;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|Selector5~3_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .mask = 16'h57DF;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] (
// Location: LCCOMB_X45_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout__SyncReset_X45_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X45_Y1_N0
alta_clkenctrl clken_ctrl_X45_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y1_SIG_VCC ));
defparam clken_ctrl_X45_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X45_Y1_N0
alta_asyncctrl asyncreset_ctrl_X45_Y1_N0(.Din(), .Dout(AsyncReset_X45_Y1_GND));
defparam asyncreset_ctrl_X45_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X45_Y1_N1
alta_clkenctrl clken_ctrl_X45_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y1_SIG_SIG ));
defparam clken_ctrl_X45_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X45_Y1_N1
alta_asyncctrl asyncreset_ctrl_X45_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y1_SIG ));
defparam asyncreset_ctrl_X45_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X45_Y1_N0
alta_syncctrl syncreset_ctrl_X45_Y1(.Din(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout ), .Dout(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout__SyncReset_X45_Y1_SIG ));
defparam syncreset_ctrl_X45_Y1.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X45_Y1_N1
alta_syncctrl syncload_ctrl_X45_Y1(.Din(), .Dout(SyncLoad_X45_Y1_GND));
defparam syncload_ctrl_X45_Y1.SyncCtrlMux = 2'b00;
// Location: FF_X45_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] (
// Location: LCCOMB_X45_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(SyncReset_X45_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout__SyncLoad_X45_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X45_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_parity (
// Location: LCCOMB_X45_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_parity (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X45_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_parity~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .mask = 16'h1000;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector1~0 (
// Location: FF_X45_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|Selector2~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .mask = 16'h3310;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always2~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always2~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always2~0 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] (
// Location: LCCOMB_X45_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(SyncReset_X45_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout__SyncLoad_X45_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X45_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|break_error (
// Location: LCCOMB_X45_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|break_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|break_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .mask = 16'hFCCC;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector0~0 (
// Location: FF_X45_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .mask = 16'h00F5;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always11~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always11~2 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|always11~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|always11~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always11~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] (
// Location: LCCOMB_X45_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(SyncReset_X45_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout__SyncLoad_X45_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X45_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] (
// Location: LCCOMB_X45_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\~GND~combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(SyncReset_X45_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout__SyncLoad_X45_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X45_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always2~1 (
// Location: FF_X45_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_bit (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_bit .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X45_Y2_N0
alta_clkenctrl clken_ctrl_X45_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y2_SIG_VCC ));
defparam clken_ctrl_X45_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X45_Y2_N0
alta_asyncctrl asyncreset_ctrl_X45_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y2_SIG ));
defparam asyncreset_ctrl_X45_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: ASYNCCTRL_X45_Y2_N1
alta_asyncctrl asyncreset_ctrl_X45_Y2_N1(.Din(), .Dout(AsyncReset_X45_Y2_GND));
defparam asyncreset_ctrl_X45_Y2_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X45_Y2_N0
alta_syncctrl syncreset_ctrl_X45_Y2(.Din(), .Dout(SyncReset_X45_Y2_GND));
defparam syncreset_ctrl_X45_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X45_Y2_N1
alta_syncctrl syncload_ctrl_X45_Y2(.Din(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout ), .Dout(\macro_inst|u_uart[0]|u_rx[4]|always6~1_combout__SyncLoad_X45_Y2_SIG ));
defparam syncload_ctrl_X45_Y2.SyncCtrlMux = 2'b10;
// Location: FF_X45_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] (
// Location: LCCOMB_X45_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_in [2]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(SyncReset_X45_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_in [3]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .mask = 16'h22AA;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X45_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|always8~0 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|always8~0 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP (
// Location: LCCOMB_X45_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Selector4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector4~6_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .mask = 16'hEEF0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] (
// Location: LCCOMB_X45_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_in [0]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(SyncReset_X45_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_in [1]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X45_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector2~2 (
// Location: FF_X45_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector2~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Selector2~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .mask = 16'h00EC;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|Selector0~4_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .mask = 16'h0E00;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY (
// Location: LCCOMB_X45_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector4~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector4~6_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector2~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector0~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .mask = 16'hCCC8;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector0~4 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] (
// Location: LCCOMB_X45_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_in [3]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_in [4]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .mask = 16'h0F0F;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Selector4~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Selector4~4_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector4~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .mask = 16'hFEFA;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|Selector4~6 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] (
// Location: LCCOMB_X45_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_in [4]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] (
// Location: LCCOMB_X45_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_in [2]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(SyncReset_X45_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_in [3]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .mask = 16'h0033;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X45_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|always3~2 (
// Location: FF_X45_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_in [1]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(SyncReset_X45_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|always3~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_in [2]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X45_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector0~3 (
// Location: FF_X45_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .mask = 16'h00F3;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] (
// Location: LCCOMB_X45_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_in [1]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ),
	.SyncReset(SyncReset_X45_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X45_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_in [2]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_in[2] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X45_Y3_N0
alta_clkenctrl clken_ctrl_X45_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X45_Y3_SIG_SIG ));
defparam clken_ctrl_X45_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X45_Y3_N0
alta_asyncctrl asyncreset_ctrl_X45_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y3_SIG ));
defparam asyncreset_ctrl_X45_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X45_Y3_N1
alta_clkenctrl clken_ctrl_X45_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y3_SIG_VCC ));
defparam clken_ctrl_X45_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y3_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X45_Y3_N0
alta_syncctrl syncreset_ctrl_X45_Y3(.Din(), .Dout(SyncReset_X45_Y3_GND));
defparam syncreset_ctrl_X45_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X45_Y3_N1
alta_syncctrl syncload_ctrl_X45_Y3(.Din(), .Dout(SyncLoad_X45_Y3_VCC));
defparam syncload_ctrl_X45_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X45_Y4_N12
// alta_lcell_comb \gpio4_io_in[6] (
alta_slice \gpio4_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[6] .mask = 16'h0000;
defparam \gpio4_io_in[6] .mode = "logic";
defparam \gpio4_io_in[6] .modeMux = 1'b0;
defparam \gpio4_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[6] .ShiftMux = 1'b0;
defparam \gpio4_io_in[6] .BypassEn = 1'b0;
defparam \gpio4_io_in[6] .CarryEnb = 1'b1;
defparam \gpio4_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N14
// alta_lcell_comb \gpio4_io_in[7] (
alta_slice \gpio4_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio4_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio4_io_in[7] .mask = 16'h0000;
defparam \gpio4_io_in[7] .mode = "logic";
defparam \gpio4_io_in[7] .modeMux = 1'b0;
defparam \gpio4_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio4_io_in[7] .ShiftMux = 1'b0;
defparam \gpio4_io_in[7] .BypassEn = 1'b0;
defparam \gpio4_io_in[7] .CarryEnb = 1'b1;
defparam \gpio4_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio4_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio4_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~7 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~7 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|overrun_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [1]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|break_error~q ),
	.D(\macro_inst|u_uart[0]|u_regs|break_error_ie [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~7 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[10] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X45_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|overrun_error_ie[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[1] .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[11] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X45_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_idle_ie[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X45_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~8 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~8 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_idle~q ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [1]),
	.C(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [1]),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_complete~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~8 .SyncLoadMux = 2'bxx;
// Location: FF_X45_Y4_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|interrupts[1] (
// Location: LCCOMB_X45_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~9 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts[1] (
	.A(\macro_inst|u_uart[0]|u_regs|interrupts~5_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|interrupts~7_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|interrupts~8_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|interrupts~6_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|interrupts [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|interrupts [1]));
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[1] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X45_Y4_N0
alta_clkenctrl clken_ctrl_X45_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X45_Y4_SIG_SIG ));
defparam clken_ctrl_X45_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X45_Y4_N0
alta_asyncctrl asyncreset_ctrl_X45_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X45_Y4_SIG ));
defparam asyncreset_ctrl_X45_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X45_Y4_N1
alta_clkenctrl clken_ctrl_X45_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X45_Y4_SIG_VCC ));
defparam clken_ctrl_X45_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X45_Y4_N1.ClkEnMux = 2'b01;
// Location: LCCOMB_X46_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector3~1 (
// Location: FF_X46_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|always0~0_combout ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|Selector3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .mask = 16'hFF80;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] (
// Location: LCCOMB_X46_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout__SyncReset_X46_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X46_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_parity (
// Location: LCCOMB_X46_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_parity (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_parity~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X46_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_parity~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .mask = 16'h335A;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] (
// Location: LCCOMB_X46_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout_X46_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|always6~1 (
// Location: FF_X46_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_bit (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_bit (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[1]|always6~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|always0~0 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .mask = 16'h0100;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|always0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] (
// Location: LCCOMB_X46_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout_X46_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .mask = 16'hEBEB;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .mask = 16'hFB88;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|always6~0 (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|always6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector4~1 (
// Location: FF_X46_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|Selector4~0_combout ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .mask = 16'hDCCC;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_parity (
// Location: LCCOMB_X46_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_parity (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X46_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_parity~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .mask = 16'hEEAA;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1 .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] (
// Location: LCCOMB_X46_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout_X46_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .mask = 16'hFAEB;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] (
// Location: LCCOMB_X46_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout__SyncReset_X46_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X46_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] (
// Location: LCCOMB_X46_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout__SyncReset_X46_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X46_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] (
// Location: LCCOMB_X46_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout__SyncReset_X46_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X46_Y1_N0
alta_clkenctrl clken_ctrl_X46_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X46_Y1_SIG_VCC ));
defparam clken_ctrl_X46_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X46_Y1_N0
alta_asyncctrl asyncreset_ctrl_X46_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y1_SIG ));
defparam asyncreset_ctrl_X46_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X46_Y1_N1
alta_clkenctrl clken_ctrl_X46_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_data_cnt[1]~1_combout_X46_Y1_SIG_SIG ));
defparam clken_ctrl_X46_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X46_Y1_N1
alta_asyncctrl asyncreset_ctrl_X46_Y1_N1(.Din(), .Dout(AsyncReset_X46_Y1_GND));
defparam asyncreset_ctrl_X46_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X46_Y1_N0
alta_syncctrl syncreset_ctrl_X46_Y1(.Din(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout ), .Dout(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout__SyncReset_X46_Y1_SIG ));
defparam syncreset_ctrl_X46_Y1.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X46_Y1_N1
alta_syncctrl syncload_ctrl_X46_Y1(.Din(), .Dout(SyncLoad_X46_Y1_GND));
defparam syncload_ctrl_X46_Y1.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X46_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .mask = 16'h4080;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux7~3 (
// Location: FF_X46_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y2_GND),
	.SyncReset(SyncReset_X46_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux7~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux6~3 (
// Location: FF_X46_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [6]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y2_GND),
	.SyncReset(SyncReset_X46_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux6~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux2~3 (
// Location: FF_X46_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [2]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y2_GND),
	.SyncReset(SyncReset_X46_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux2~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .mask = 16'hAAD8;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: FF_X46_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_dma_en [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_dma_en[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_dma_en [4]));
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux3~3 (
// Location: FF_X46_Y2_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [3]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y2_GND),
	.SyncReset(SyncReset_X46_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux3~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux0~3 (
// Location: FF_X46_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [0]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y2_GND),
	.SyncReset(SyncReset_X46_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .mask = 16'h6000;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_shift_reg [7]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_dma_en [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_dma_en [4]));
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 (
	.A(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux5~3 (
// Location: FF_X46_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [5]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y2_GND),
	.SyncReset(SyncReset_X46_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X46_Y2_N0
alta_clkenctrl clken_ctrl_X46_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X46_Y2_SIG_SIG ));
defparam clken_ctrl_X46_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X46_Y2_N0
alta_asyncctrl asyncreset_ctrl_X46_Y2_N0(.Din(), .Dout(AsyncReset_X46_Y2_GND));
defparam asyncreset_ctrl_X46_Y2_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X46_Y2_N1
alta_clkenctrl clken_ctrl_X46_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[4]~1_combout_X46_Y2_SIG_SIG ));
defparam clken_ctrl_X46_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y2_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X46_Y2_N1
alta_asyncctrl asyncreset_ctrl_X46_Y2_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y2_SIG ));
defparam asyncreset_ctrl_X46_Y2_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X46_Y2_N0
alta_syncctrl syncreset_ctrl_X46_Y2(.Din(), .Dout(SyncReset_X46_Y2_GND));
defparam syncreset_ctrl_X46_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X46_Y2_N1
alta_syncctrl syncload_ctrl_X46_Y2(.Din(), .Dout(SyncLoad_X46_Y2_VCC));
defparam syncload_ctrl_X46_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X46_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] (
// Location: LCCOMB_X46_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] (
// Location: LCCOMB_X46_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Add1~0 (
// Location: FF_X46_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_in [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .mask = 16'h7171;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] (
// Location: LCCOMB_X46_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] (
// Location: LCCOMB_X46_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|always4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .mask = 16'h0400;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] (
// Location: LCCOMB_X46_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always11~1 (
// Location: FF_X46_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [1]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [3]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(SyncReset_X46_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: FF_X46_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] (
// Location: LCCOMB_X46_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] (
// Location: LCCOMB_X46_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] (
// Location: LCCOMB_X46_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] (
// Location: LCCOMB_X46_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] (
// Location: LCCOMB_X46_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y3_GND),
	.SyncReset(SyncReset_X46_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_parity~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: FF_X46_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [5]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X46_Y3_GND),
	.SyncReset(SyncReset_X46_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y3_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always11~0 (
// Location: FF_X46_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [5]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [7]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ),
	.SyncReset(SyncReset_X46_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always6~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|always6~1 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_in [4]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .mask = 16'h008E;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always6~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X46_Y3_N0
alta_clkenctrl clken_ctrl_X46_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[1]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|always4~2_combout_X46_Y3_SIG_SIG ));
defparam clken_ctrl_X46_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X46_Y3_N0
alta_asyncctrl asyncreset_ctrl_X46_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y3_SIG ));
defparam asyncreset_ctrl_X46_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X46_Y3_N1
alta_clkenctrl clken_ctrl_X46_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X46_Y3_SIG_SIG ));
defparam clken_ctrl_X46_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y3_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X46_Y3_N1
alta_asyncctrl asyncreset_ctrl_X46_Y3_N1(.Din(), .Dout(AsyncReset_X46_Y3_GND));
defparam asyncreset_ctrl_X46_Y3_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X46_Y3_N0
alta_syncctrl syncreset_ctrl_X46_Y3(.Din(), .Dout(SyncReset_X46_Y3_GND));
defparam syncreset_ctrl_X46_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X46_Y3_N1
alta_syncctrl syncload_ctrl_X46_Y3(.Din(), .Dout(SyncLoad_X46_Y3_VCC));
defparam syncload_ctrl_X46_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X46_Y4_N12
// alta_lcell_comb \gpio5_io_in[6] (
alta_slice \gpio5_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio5_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio5_io_in[6] .mask = 16'h0000;
defparam \gpio5_io_in[6] .mode = "logic";
defparam \gpio5_io_in[6] .modeMux = 1'b0;
defparam \gpio5_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio5_io_in[6] .ShiftMux = 1'b0;
defparam \gpio5_io_in[6] .BypassEn = 1'b0;
defparam \gpio5_io_in[6] .CarryEnb = 1'b1;
defparam \gpio5_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio5_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio5_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y4_N14
// alta_lcell_comb \gpio5_io_in[7] (
alta_slice \gpio5_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio5_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio5_io_in[7] .mask = 16'h0000;
defparam \gpio5_io_in[7] .mode = "logic";
defparam \gpio5_io_in[7] .modeMux = 1'b0;
defparam \gpio5_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio5_io_in[7] .ShiftMux = 1'b0;
defparam \gpio5_io_in[7] .BypassEn = 1'b0;
defparam \gpio5_io_in[7] .CarryEnb = 1'b1;
defparam \gpio5_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio5_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio5_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X46_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~3 (
// Location: FF_X46_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|tx_dma_en [2]),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_dma_en [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5_combout_X46_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y4_SIG ),
	.SyncReset(SyncReset_X46_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_dma_en [3]));
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~1 (
// Location: FF_X46_Y4_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|rx_dma_en [2]),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector12~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_dma_en [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5_combout_X46_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y4_SIG ),
	.SyncReset(SyncReset_X46_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_dma_en [3]));
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .mask = 16'h3F00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0 .SyncLoadMux = 2'bxx;
// Location: FF_X46_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] (
// Location: LCCOMB_X46_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_dma_en [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4_combout_X46_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y4_SIG ),
	.SyncReset(SyncReset_X46_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_dma_en [2]));
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4 (
// Location: FF_X46_Y4_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_dma_en [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4_combout_X46_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y4_SIG ),
	.SyncReset(SyncReset_X46_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X46_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_dma_en [2]));
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X46_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .mask = 16'h3F00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X46_Y4_N0
alta_clkenctrl clken_ctrl_X46_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[3]~5_combout_X46_Y4_SIG_SIG ));
defparam clken_ctrl_X46_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X46_Y4_N0
alta_asyncctrl asyncreset_ctrl_X46_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X46_Y4_SIG ));
defparam asyncreset_ctrl_X46_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X46_Y4_N1
alta_clkenctrl clken_ctrl_X46_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[2]~4_combout_X46_Y4_SIG_SIG ));
defparam clken_ctrl_X46_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X46_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X46_Y4_N0
alta_syncctrl syncreset_ctrl_X46_Y4(.Din(), .Dout(SyncReset_X46_Y4_GND));
defparam syncreset_ctrl_X46_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X46_Y4_N1
alta_syncctrl syncload_ctrl_X46_Y4(.Din(), .Dout(SyncLoad_X46_Y4_VCC));
defparam syncload_ctrl_X46_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X47_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Add4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Add4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .mask = 16'h0F1E;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always3~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|always3~1 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~1 .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] (
// Location: LCCOMB_X47_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|always3~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout_X47_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .mask = 16'hFF07;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] (
// Location: LCCOMB_X47_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Add4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .mask = 16'h1130;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector1~0 (
// Location: FF_X47_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .mask = 16'h00DC;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] (
// Location: LCCOMB_X47_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|Add4~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout_X47_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .mask = 16'hCDCF;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] (
// Location: LCCOMB_X47_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Add4~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout_X47_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .mask = 16'hFDCD;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] (
// Location: LCCOMB_X47_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y1_SIG ),
	.SyncReset(SyncReset_X47_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout__SyncLoad_X47_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X47_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] (
// Location: LCCOMB_X47_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y1_SIG ),
	.SyncReset(SyncReset_X47_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout__SyncLoad_X47_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X47_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] (
// Location: LCCOMB_X47_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y1_SIG ),
	.SyncReset(SyncReset_X47_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout__SyncLoad_X47_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X47_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] (
// Location: LCCOMB_X47_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\~GND~combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y1_SIG ),
	.SyncReset(SyncReset_X47_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout__SyncLoad_X47_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X47_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .mask = 16'hFFAA;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always3~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|always3~2 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|always3~1_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .mask = 16'hAA00;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Selector2~3_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .mask = 16'hAAA8;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X47_Y1_N0
alta_clkenctrl clken_ctrl_X47_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt[0]~3_combout_X47_Y1_SIG_SIG ));
defparam clken_ctrl_X47_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X47_Y1_N0
alta_asyncctrl asyncreset_ctrl_X47_Y1_N0(.Din(), .Dout(AsyncReset_X47_Y1_GND));
defparam asyncreset_ctrl_X47_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X47_Y1_N1
alta_clkenctrl clken_ctrl_X47_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y1_SIG_VCC ));
defparam clken_ctrl_X47_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X47_Y1_N1
alta_asyncctrl asyncreset_ctrl_X47_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y1_SIG ));
defparam asyncreset_ctrl_X47_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X47_Y1_N0
alta_syncctrl syncreset_ctrl_X47_Y1(.Din(), .Dout(SyncReset_X47_Y1_GND));
defparam syncreset_ctrl_X47_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X47_Y1_N1
alta_syncctrl syncload_ctrl_X47_Y1(.Din(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout ), .Dout(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout__SyncLoad_X47_Y1_SIG ));
defparam syncload_ctrl_X47_Y1.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X47_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux6~5 (
// Location: FF_X47_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[6] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[6] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux6~4_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Mux6~2_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux6~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [6]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .mask = 16'h0CAA;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux5~5 (
// Location: FF_X47_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[5] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_regs|Mux5~4_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux5~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux5~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [5]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .mask = 16'h7250;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux4~5 (
// Location: FF_X47_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[4] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux4~4_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Mux4~2_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux4~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [4]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .mask = 16'h0CAA;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux2~5 (
// Location: FF_X47_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[2] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_uart[0]|u_regs|Mux2~4_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_regs|Mux2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux2~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [2]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .mask = 16'h4E44;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_sample~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux0~5 (
// Location: FF_X47_Y2_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[0] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_regs|Mux0~2_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux0~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux0~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [0]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .mask = 16'h7520;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux2~4 (
// Location: FF_X47_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][2]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_regs|Mux2~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux2~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux6~4 (
// Location: FF_X47_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_regs|Mux6~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux6~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux1~4 (
// Location: FF_X47_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][1]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_regs|Mux1~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux1~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux7~4 (
// Location: FF_X47_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][7]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_regs|Mux7~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux7~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux0~4 (
// Location: FF_X47_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux0~3_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][0]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux0~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .mask = 16'hE6A2;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux4~4 (
// Location: FF_X47_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux4~3_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][4]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux4~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .mask = 16'hE6A2;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux3~5 (
// Location: FF_X47_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[3] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux3~4_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_regs|Mux3~2_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux3~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [3]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .mask = 16'h30AA;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux3~4 (
// Location: FF_X47_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][3]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_regs|Mux3~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux3~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux5~4 (
// Location: FF_X47_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux5~3_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y2_GND),
	.SyncReset(SyncReset_X47_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .mask = 16'hE6A2;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X47_Y2_N0
alta_clkenctrl clken_ctrl_X47_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y2_SIG_VCC ));
defparam clken_ctrl_X47_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X47_Y2_N0
alta_asyncctrl asyncreset_ctrl_X47_Y2_N0(.Din(), .Dout(AsyncReset_X47_Y2_GND));
defparam asyncreset_ctrl_X47_Y2_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X47_Y2_N1
alta_clkenctrl clken_ctrl_X47_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|rx_fifo|wrreq~0_combout_X47_Y2_SIG_SIG ));
defparam clken_ctrl_X47_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X47_Y2_N0
alta_syncctrl syncreset_ctrl_X47_Y2(.Din(), .Dout(SyncReset_X47_Y2_GND));
defparam syncreset_ctrl_X47_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X47_Y2_N1
alta_syncctrl syncload_ctrl_X47_Y2(.Din(), .Dout(SyncLoad_X47_Y2_VCC));
defparam syncload_ctrl_X47_Y2.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X47_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .mask = 16'hC4C0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] (
// Location: LCCOMB_X47_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X47_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y3_GND),
	.SyncReset(SyncReset_X47_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .mask = 16'h7700;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: FF_X47_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY (
// Location: LCCOMB_X47_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Selector3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .mask = 16'hA2A2;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector1~0 (
// Location: FF_X47_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Selector0~4_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .mask = 16'h00BA;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector0~3 (
// Location: FF_X47_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .mask = 16'h00F5;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Selector3~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .mask = 16'hA0EC;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Selector0~4_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .mask = 16'h3200;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector2~2 (
// Location: FF_X47_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|Selector2~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .mask = 16'h00EA;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector2~0 (
// Location: FF_X47_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X47_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X47_Y3_GND),
	.SyncReset(SyncReset_X47_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_sample~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~2 .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP (
// Location: LCCOMB_X47_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|Selector4~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .mask = 16'hDCDE;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Selector3~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|Selector4~3_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .mask = 16'hEFCD;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Selector2~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|always3~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector0~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .mask = 16'hCCC8;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~4 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X47_Y3_N0
alta_clkenctrl clken_ctrl_X47_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout_X47_Y3_SIG_SIG ));
defparam clken_ctrl_X47_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X47_Y3_N0
alta_asyncctrl asyncreset_ctrl_X47_Y3_N0(.Din(), .Dout(AsyncReset_X47_Y3_GND));
defparam asyncreset_ctrl_X47_Y3_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X47_Y3_N1
alta_clkenctrl clken_ctrl_X47_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y3_SIG_VCC ));
defparam clken_ctrl_X47_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y3_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X47_Y3_N1
alta_asyncctrl asyncreset_ctrl_X47_Y3_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y3_SIG ));
defparam asyncreset_ctrl_X47_Y3_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X47_Y3_N0
alta_syncctrl syncreset_ctrl_X47_Y3(.Din(), .Dout(SyncReset_X47_Y3_GND));
defparam syncreset_ctrl_X47_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X47_Y3_N1
alta_syncctrl syncload_ctrl_X47_Y3(.Din(), .Dout(SyncLoad_X47_Y3_VCC));
defparam syncload_ctrl_X47_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X47_Y4_N0
// alta_lcell_comb \gpio6_io_in[0] (
alta_slice \gpio6_io_in[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[0]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[0] .mask = 16'h0000;
defparam \gpio6_io_in[0] .mode = "logic";
defparam \gpio6_io_in[0] .modeMux = 1'b0;
defparam \gpio6_io_in[0] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[0] .ShiftMux = 1'b0;
defparam \gpio6_io_in[0] .BypassEn = 1'b0;
defparam \gpio6_io_in[0] .CarryEnb = 1'b1;
defparam \gpio6_io_in[0] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[0] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N10
// alta_lcell_comb \gpio6_io_in[5] (
alta_slice \gpio6_io_in[5] (
	.A(\rv32.gpio8_io_out_en[3] ),
	.B(\rv32.gpio8_io_out_data[3] ),
	.C(vcc),
	.D(\SIM_IO_13~input_o ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[5] .mask = 16'hFF88;
defparam \gpio6_io_in[5] .mode = "logic";
defparam \gpio6_io_in[5] .modeMux = 1'b0;
defparam \gpio6_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[5] .ShiftMux = 1'b0;
defparam \gpio6_io_in[5] .BypassEn = 1'b0;
defparam \gpio6_io_in[5] .CarryEnb = 1'b1;
defparam \gpio6_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[5] .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y4_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] (
// Location: LCCOMB_X47_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X47_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y4_SIG ),
	.SyncReset(SyncReset_X47_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X47_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .mask = 16'h4400;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X47_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector2~0 (
// Location: FF_X47_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|always0~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .mask = 16'hBA30;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N2
// alta_lcell_comb \gpio6_io_in[1] (
alta_slice \gpio6_io_in[1] (
	.A(\SIM_IO_15~input_o ),
	.B(\uart15_rx~input_o ),
	.C(gpio8_io_out_en[7]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[1]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[1] .mask = 16'hCACA;
defparam \gpio6_io_in[1] .mode = "logic";
defparam \gpio6_io_in[1] .modeMux = 1'b0;
defparam \gpio6_io_in[1] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[1] .ShiftMux = 1'b0;
defparam \gpio6_io_in[1] .BypassEn = 1'b0;
defparam \gpio6_io_in[1] .CarryEnb = 1'b1;
defparam \gpio6_io_in[1] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[1] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .mask = 16'h060A;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: FF_X47_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt (
// Location: LCCOMB_X47_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X47_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .mask = 16'hFFC0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .mask = 16'hFB88;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector4~1 (
// Location: FF_X47_Y4_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|always0~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .mask = 16'hFF08;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N4
// alta_lcell_comb \gpio6_io_in[2] (
alta_slice \gpio6_io_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[2]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[2] .mask = 16'h0000;
defparam \gpio6_io_in[2] .mode = "logic";
defparam \gpio6_io_in[2] .modeMux = 1'b0;
defparam \gpio6_io_in[2] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[2] .ShiftMux = 1'b0;
defparam \gpio6_io_in[2] .BypassEn = 1'b0;
defparam \gpio6_io_in[2] .CarryEnb = 1'b1;
defparam \gpio6_io_in[2] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[2] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N6
// alta_lcell_comb \gpio6_io_in[3] (
alta_slice \gpio6_io_in[3] (
	.A(\rv32.gpio8_io_out_en[1] ),
	.B(\SIM_IO_12~input_o ),
	.C(vcc),
	.D(\rv32.gpio8_io_out_data[1] ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[3]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[3] .mask = 16'hEECC;
defparam \gpio6_io_in[3] .mode = "logic";
defparam \gpio6_io_in[3] .modeMux = 1'b0;
defparam \gpio6_io_in[3] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[3] .ShiftMux = 1'b0;
defparam \gpio6_io_in[3] .BypassEn = 1'b0;
defparam \gpio6_io_in[3] .CarryEnb = 1'b1;
defparam \gpio6_io_in[3] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[3] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X47_Y4_N8
// alta_lcell_comb \gpio6_io_in[4] (
alta_slice \gpio6_io_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio6_io_in[4]),
	.Cout(),
	.Q());
defparam \gpio6_io_in[4] .mask = 16'h0000;
defparam \gpio6_io_in[4] .mode = "logic";
defparam \gpio6_io_in[4] .modeMux = 1'b0;
defparam \gpio6_io_in[4] .FeedbackMux = 1'b0;
defparam \gpio6_io_in[4] .ShiftMux = 1'b0;
defparam \gpio6_io_in[4] .BypassEn = 1'b0;
defparam \gpio6_io_in[4] .CarryEnb = 1'b1;
defparam \gpio6_io_in[4] .AsyncResetMux = 2'bxx;
defparam \gpio6_io_in[4] .SyncResetMux = 2'bxx;
defparam \gpio6_io_in[4] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X47_Y4_N0
alta_clkenctrl clken_ctrl_X47_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X47_Y4_SIG_SIG ));
defparam clken_ctrl_X47_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X47_Y4_N0
alta_asyncctrl asyncreset_ctrl_X47_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X47_Y4_SIG ));
defparam asyncreset_ctrl_X47_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X47_Y4_N1
alta_clkenctrl clken_ctrl_X47_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X47_Y4_SIG_VCC ));
defparam clken_ctrl_X47_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X47_Y4_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X47_Y4_N1
alta_asyncctrl asyncreset_ctrl_X47_Y4_N1(.Din(), .Dout(AsyncReset_X47_Y4_GND));
defparam asyncreset_ctrl_X47_Y4_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X47_Y4_N0
alta_syncctrl syncreset_ctrl_X47_Y4(.Din(), .Dout(SyncReset_X47_Y4_GND));
defparam syncreset_ctrl_X47_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X47_Y4_N1
alta_syncctrl syncload_ctrl_X47_Y4(.Din(), .Dout(SyncLoad_X47_Y4_VCC));
defparam syncload_ctrl_X47_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X48_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~0 (
// Location: FF_X48_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .mask = 16'h7700;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .mask = 16'h1000;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: FF_X48_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] (
// Location: LCCOMB_X48_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_in [4]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always11~2 (
// Location: FF_X48_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|always11~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|always11~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always11~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7]),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always2~0 (
// Location: FF_X48_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|always8~0 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector4~0 (
// Location: FF_X48_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|rx_in [0]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_in [1]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always6~1 (
// Location: FF_X48_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_in [1]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_in [2]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .mask = 16'h4054;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Add4~1 (
// Location: FF_X48_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_in [2]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Add4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_in [3]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .mask = 16'h5566;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always11~0 (
// Location: FF_X48_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [6]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [5]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|always4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .mask = 16'h0200;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|always4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_sample~0 (
// Location: FF_X48_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_sample~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .mask = 16'h0055;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Add4~2 (
// Location: FF_X48_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Add4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .mask = 16'h33CC;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always11~1 (
// Location: FF_X48_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [2]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [3]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Add1~0 (
// Location: FF_X48_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ),
	.SyncReset(SyncReset_X48_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .mask = 16'h7711;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_shift_reg[5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X48_Y1_N0
alta_clkenctrl clken_ctrl_X48_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[3]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[3]|always4~2_combout_X48_Y1_SIG_SIG ));
defparam clken_ctrl_X48_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X48_Y1_N0
alta_asyncctrl asyncreset_ctrl_X48_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y1_SIG ));
defparam asyncreset_ctrl_X48_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X48_Y1_N1
alta_clkenctrl clken_ctrl_X48_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X48_Y1_SIG_SIG ));
defparam clken_ctrl_X48_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y1_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X48_Y1_N0
alta_syncctrl syncreset_ctrl_X48_Y1(.Din(), .Dout(SyncReset_X48_Y1_GND));
defparam syncreset_ctrl_X48_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X48_Y1_N1
alta_syncctrl syncload_ctrl_X48_Y1(.Din(), .Dout(SyncLoad_X48_Y1_VCC));
defparam syncload_ctrl_X48_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X48_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Selector4~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector4~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .mask = 16'hCDCC;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .mask = 16'hC0EA;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .mask = 16'hA000;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: FF_X48_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP (
// Location: LCCOMB_X48_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Selector4~4_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .mask = 16'hFC30;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector2~2 (
// Location: FF_X48_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Selector2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|Selector2~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector1~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .mask = 16'h00F8;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector1~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .mask = 16'hAAA8;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector0~0 (
// Location: FF_X48_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector1~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .mask = 16'h00F3;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux1~3 (
// Location: FF_X48_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][1]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [1]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X48_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X48_Y2_GND),
	.SyncReset(SyncReset_X48_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux1~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .mask = 16'hCCB8;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|always2~1 (
// Location: FF_X48_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_bit (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_bit (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_baud_cnt [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always3~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|always3~2 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .mask = 16'hAA00;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Selector4~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .mask = 16'hCB8B;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector1~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .mask = 16'h00A8;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: FF_X48_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY (
// Location: LCCOMB_X48_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux4~3 (
// Location: FF_X48_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|fifo[1][4]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [4]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X48_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X48_Y2_GND),
	.SyncReset(SyncReset_X48_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .mask = 16'hCCB8;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .mask = 16'hA8A0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X48_Y2_N0
alta_clkenctrl clken_ctrl_X48_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y2_SIG_VCC ));
defparam clken_ctrl_X48_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X48_Y2_N0
alta_asyncctrl asyncreset_ctrl_X48_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y2_SIG ));
defparam asyncreset_ctrl_X48_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X48_Y2_N1
alta_clkenctrl clken_ctrl_X48_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout_X48_Y2_SIG_SIG ));
defparam clken_ctrl_X48_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y2_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X48_Y2_N1
alta_asyncctrl asyncreset_ctrl_X48_Y2_N1(.Din(), .Dout(AsyncReset_X48_Y2_GND));
defparam asyncreset_ctrl_X48_Y2_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X48_Y2_N0
alta_syncctrl syncreset_ctrl_X48_Y2(.Din(), .Dout(SyncReset_X48_Y2_GND));
defparam syncreset_ctrl_X48_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X48_Y2_N1
alta_syncctrl syncload_ctrl_X48_Y2(.Din(), .Dout(SyncLoad_X48_Y2_VCC));
defparam syncload_ctrl_X48_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X48_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY (
// Location: LCCOMB_X48_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Selector4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|Selector4~3_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .mask = 16'hB9B1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Selector2~3_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .mask = 16'hCCC8;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always8~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|always8~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|Selector2~4_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .mask = 16'h3020;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .mask = 16'h7700;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector4~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .mask = 16'hC888;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always3~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always3~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector2~6 (
// Location: FF_X48_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Selector2~3_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|Selector2~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .mask = 16'h0F08;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X48_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP (
// Location: LCCOMB_X48_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector4~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .mask = 16'h0C00;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|Selector4~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector4~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector4~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .mask = 16'hCDCC;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Selector4~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X48_Y3_N0
alta_clkenctrl clken_ctrl_X48_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y3_SIG_VCC ));
defparam clken_ctrl_X48_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X48_Y3_N0
alta_asyncctrl asyncreset_ctrl_X48_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y3_SIG ));
defparam asyncreset_ctrl_X48_Y3_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X48_Y4_N0
// alta_lcell_comb \gpio7_io_in[0] (
alta_slice \gpio7_io_in[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[0]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[0] .mask = 16'h0000;
defparam \gpio7_io_in[0] .mode = "logic";
defparam \gpio7_io_in[0] .modeMux = 1'b0;
defparam \gpio7_io_in[0] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[0] .ShiftMux = 1'b0;
defparam \gpio7_io_in[0] .BypassEn = 1'b0;
defparam \gpio7_io_in[0] .CarryEnb = 1'b1;
defparam \gpio7_io_in[0] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[0] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N10
// alta_lcell_comb \gpio7_io_in[5] (
alta_slice \gpio7_io_in[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[5] .mask = 16'h0000;
defparam \gpio7_io_in[5] .mode = "logic";
defparam \gpio7_io_in[5] .modeMux = 1'b0;
defparam \gpio7_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[5] .ShiftMux = 1'b0;
defparam \gpio7_io_in[5] .BypassEn = 1'b0;
defparam \gpio7_io_in[5] .CarryEnb = 1'b1;
defparam \gpio7_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N12
// alta_lcell_comb \gpio7_io_in[6] (
alta_slice \gpio7_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[6] .mask = 16'h0000;
defparam \gpio7_io_in[6] .mode = "logic";
defparam \gpio7_io_in[6] .modeMux = 1'b0;
defparam \gpio7_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[6] .ShiftMux = 1'b0;
defparam \gpio7_io_in[6] .BypassEn = 1'b0;
defparam \gpio7_io_in[6] .CarryEnb = 1'b1;
defparam \gpio7_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N14
// alta_lcell_comb \gpio7_io_in[7] (
alta_slice \gpio7_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[7] .mask = 16'h0000;
defparam \gpio7_io_in[7] .mode = "logic";
defparam \gpio7_io_in[7] .modeMux = 1'b0;
defparam \gpio7_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[7] .ShiftMux = 1'b0;
defparam \gpio7_io_in[7] .BypassEn = 1'b0;
defparam \gpio7_io_in[7] .CarryEnb = 1'b1;
defparam \gpio7_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Add4~1 (
// Location: FF_X48_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X48_Y4_GND),
	.SyncReset(SyncReset_X48_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X48_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Add4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .mask = 16'h5566;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X48_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Add4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Add4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .mask = 16'h0F1E;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X48_Y4_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] (
// Location: LCCOMB_X48_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Add4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X48_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .mask = 16'h1130;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: FF_X48_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|break_error_ie[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|break_error_ie[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[9] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|break_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X48_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|break_error_ie[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|break_error_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N4
// alta_lcell_comb \gpio7_io_in[2] (
alta_slice \gpio7_io_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[2]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[2] .mask = 16'h0000;
defparam \gpio7_io_in[2] .mode = "logic";
defparam \gpio7_io_in[2] .modeMux = 1'b0;
defparam \gpio7_io_in[2] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[2] .ShiftMux = 1'b0;
defparam \gpio7_io_in[2] .BypassEn = 1'b0;
defparam \gpio7_io_in[2] .CarryEnb = 1'b1;
defparam \gpio7_io_in[2] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[2] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N6
// alta_lcell_comb \gpio7_io_in[3] (
alta_slice \gpio7_io_in[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[3]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[3] .mask = 16'h0000;
defparam \gpio7_io_in[3] .mode = "logic";
defparam \gpio7_io_in[3] .modeMux = 1'b0;
defparam \gpio7_io_in[3] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[3] .ShiftMux = 1'b0;
defparam \gpio7_io_in[3] .BypassEn = 1'b0;
defparam \gpio7_io_in[3] .CarryEnb = 1'b1;
defparam \gpio7_io_in[3] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[3] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X48_Y4_N8
// alta_lcell_comb \gpio7_io_in[4] (
alta_slice \gpio7_io_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio7_io_in[4]),
	.Cout(),
	.Q());
defparam \gpio7_io_in[4] .mask = 16'h0000;
defparam \gpio7_io_in[4] .mode = "logic";
defparam \gpio7_io_in[4] .modeMux = 1'b0;
defparam \gpio7_io_in[4] .FeedbackMux = 1'b0;
defparam \gpio7_io_in[4] .ShiftMux = 1'b0;
defparam \gpio7_io_in[4] .BypassEn = 1'b0;
defparam \gpio7_io_in[4] .CarryEnb = 1'b1;
defparam \gpio7_io_in[4] .AsyncResetMux = 2'bxx;
defparam \gpio7_io_in[4] .SyncResetMux = 2'bxx;
defparam \gpio7_io_in[4] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X48_Y4_N0
alta_clkenctrl clken_ctrl_X48_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X48_Y4_SIG_VCC ));
defparam clken_ctrl_X48_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y4_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X48_Y4_N0
alta_asyncctrl asyncreset_ctrl_X48_Y4_N0(.Din(), .Dout(AsyncReset_X48_Y4_GND));
defparam asyncreset_ctrl_X48_Y4_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X48_Y4_N1
alta_clkenctrl clken_ctrl_X48_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X48_Y4_SIG_SIG ));
defparam clken_ctrl_X48_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X48_Y4_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X48_Y4_N1
alta_asyncctrl asyncreset_ctrl_X48_Y4_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X48_Y4_SIG ));
defparam asyncreset_ctrl_X48_Y4_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X48_Y4_N0
alta_syncctrl syncreset_ctrl_X48_Y4(.Din(), .Dout(SyncReset_X48_Y4_GND));
defparam syncreset_ctrl_X48_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X48_Y4_N1
alta_syncctrl syncload_ctrl_X48_Y4(.Din(), .Dout(SyncLoad_X48_Y4_VCC));
defparam syncload_ctrl_X48_Y4.SyncCtrlMux = 2'b01;
// Location: FF_X49_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] (
// Location: LCCOMB_X49_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X49_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] (
// Location: LCCOMB_X49_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y1_SIG ),
	.SyncReset(SyncReset_X49_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout__SyncLoad_X49_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X49_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] (
// Location: LCCOMB_X49_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y1_SIG ),
	.SyncReset(SyncReset_X49_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout__SyncLoad_X49_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X49_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] (
// Location: LCCOMB_X49_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [3]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y1_SIG ),
	.SyncReset(SyncReset_X49_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout__SyncLoad_X49_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .mask = 16'h3C3C;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X49_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always2~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always2~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector4~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .mask = 16'hDD91;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .mask = 16'h0040;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_sample~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always6~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always6~1 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_in [4]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_in [2]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .mask = 16'h00D4;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .mask = 16'h0040;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|Selector4~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .mask = 16'h0C00;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .mask = 16'h4080;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] (
// Location: LCCOMB_X49_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X49_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .mask = 16'h4080;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] (
// Location: LCCOMB_X49_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y1_SIG ),
	.SyncReset(SyncReset_X49_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout__SyncLoad_X49_Y1_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;

// Location: CLKENCTRL_X49_Y1_N0
alta_clkenctrl clken_ctrl_X49_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|rx_fifo|wrreq~0_combout_X49_Y1_SIG_SIG ));
defparam clken_ctrl_X49_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X49_Y1_N0
alta_asyncctrl asyncreset_ctrl_X49_Y1_N0(.Din(), .Dout(AsyncReset_X49_Y1_GND));
defparam asyncreset_ctrl_X49_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X49_Y1_N1
alta_clkenctrl clken_ctrl_X49_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y1_SIG_VCC ));
defparam clken_ctrl_X49_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X49_Y1_N1
alta_asyncctrl asyncreset_ctrl_X49_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y1_SIG ));
defparam asyncreset_ctrl_X49_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X49_Y1_N0
alta_syncctrl syncreset_ctrl_X49_Y1(.Din(), .Dout(SyncReset_X49_Y1_GND));
defparam syncreset_ctrl_X49_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X49_Y1_N1
alta_syncctrl syncload_ctrl_X49_Y1(.Din(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout ), .Dout(\macro_inst|u_uart[0]|u_rx[2]|always6~1_combout__SyncLoad_X49_Y1_SIG ));
defparam syncload_ctrl_X49_Y1.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X49_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|always4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .mask = 16'h0200;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req (
// Location: LCCOMB_X49_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req (
	.A(\rv32.ext_dma_DMACCLR[1] ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_dma_en [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_dma_req~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .mask = 16'h4440;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_dma_req .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .mask = 16'h5000;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_sample~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always2~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|always2~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .mask = 16'h0200;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector1~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector1~2 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] (
// Location: LCCOMB_X49_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(SyncReset_X49_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout__SyncLoad_X49_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X49_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] (
// Location: LCCOMB_X49_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(SyncReset_X49_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout__SyncLoad_X49_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X49_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] (
// Location: LCCOMB_X49_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(SyncReset_X49_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout__SyncLoad_X49_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X49_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] (
// Location: LCCOMB_X49_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [3]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(SyncReset_X49_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout__SyncLoad_X49_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .mask = 16'h5A5A;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X49_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector1~4 (
// Location: FF_X49_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Selector1~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector1~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector1~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .mask = 16'h4454;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always2~1 (
// Location: FF_X49_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_bit (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_baud_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~6 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~6 (
	.A(\macro_inst|u_uart[0]|u_regs|parity_error_ie [1]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|parity_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|framing_error_ie [1]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|framing_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~6 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X49_Y2_N0
alta_clkenctrl clken_ctrl_X49_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X49_Y2_SIG_VCC ));
defparam clken_ctrl_X49_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X49_Y2_N0
alta_asyncctrl asyncreset_ctrl_X49_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y2_SIG ));
defparam asyncreset_ctrl_X49_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X49_Y2_N0
alta_syncctrl syncreset_ctrl_X49_Y2(.Din(), .Dout(SyncReset_X49_Y2_GND));
defparam syncreset_ctrl_X49_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X49_Y2_N1
alta_syncctrl syncload_ctrl_X49_Y2(.Din(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout ), .Dout(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout__SyncLoad_X49_Y2_SIG ));
defparam syncload_ctrl_X49_Y2.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X49_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always6~1 (
// Location: FF_X49_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_in [4]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_in [2]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_in [3]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .mask = 16'h00B2;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: FF_X49_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] (
// Location: LCCOMB_X49_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always3~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|always3~1_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always3~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .mask = 16'hAA00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X49_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_sample~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Add1~0 (
// Location: FF_X49_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_in [3]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_in [2]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .mask = 16'h3F03;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] (
// Location: LCCOMB_X49_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_in [4]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] (
// Location: LCCOMB_X49_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_in [0]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_in [1]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: FF_X49_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] (
// Location: LCCOMB_X49_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_sample~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_sample~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .mask = 16'h0033;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[1] .SyncLoadMux = 2'b01;
// Location: FF_X49_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] (
// Location: LCCOMB_X49_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always2~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X49_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always11~1 (
// Location: FF_X49_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [2]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [1]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X49_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always11~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|always11~2 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|always11~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always11~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always11~0 (
// Location: FF_X49_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [5]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X49_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] (
// Location: LCCOMB_X49_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_in [1]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_in [2]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[2] .SyncLoadMux = 2'b01;
// Location: FF_X49_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] (
// Location: LCCOMB_X49_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .mask = 16'hFFAA;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X49_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|always8~0 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|always3~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y3_N8
// alta_lcell_comb \macro_inst|SIM_IO_15~1 (
// Location: FF_X49_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] (
	.A(\rv32.gpio8_io_out_data[7] ),
	.B(\rv32.gpio7_io_out_en[6] ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [5]),
	.D(gpio8_io_out_en[7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ),
	.SyncReset(SyncReset_X49_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X49_Y3_VCC),
	.LutOut(\macro_inst|SIM_IO_15~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .mask = 16'h0088;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X49_Y3_N0
alta_clkenctrl clken_ctrl_X49_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X49_Y3_SIG_SIG ));
defparam clken_ctrl_X49_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X49_Y3_N0
alta_asyncctrl asyncreset_ctrl_X49_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X49_Y3_SIG ));
defparam asyncreset_ctrl_X49_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X49_Y3_N1
alta_clkenctrl clken_ctrl_X49_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[0]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|always4~2_combout_X49_Y3_SIG_SIG ));
defparam clken_ctrl_X49_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y3_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X49_Y3_N0
alta_syncctrl syncreset_ctrl_X49_Y3(.Din(), .Dout(SyncReset_X49_Y3_GND));
defparam syncreset_ctrl_X49_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X49_Y3_N1
alta_syncctrl syncload_ctrl_X49_Y3(.Din(), .Dout(SyncLoad_X49_Y3_VCC));
defparam syncload_ctrl_X49_Y3.SyncCtrlMux = 2'b01;
// Location: FF_X49_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] (
// Location: LCCOMB_X49_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|always3~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout_X49_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .mask = 16'hABAF;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] (
// Location: LCCOMB_X49_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Add4~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout_X49_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .mask = 16'hF0F7;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Add4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .mask = 16'h1310;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~1 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] (
// Location: LCCOMB_X49_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|Add4~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout_X49_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .mask = 16'hF1F3;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|always2~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_sample~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] (
// Location: LCCOMB_X49_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[4]|always3~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout_X49_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .mask = 16'hCDCF;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Add4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Add4~1 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .mask = 16'h0F5A;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Add4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Add4~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] (
// Location: LCCOMB_X49_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[4]|always3~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Add4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout_X49_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .mask = 16'hF8FD;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|always3~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|always3~1 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Add4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Add4~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always3~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|always3~1 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always3~1 .SyncLoadMux = 2'bxx;
// Location: FF_X49_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] (
// Location: LCCOMB_X49_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Add4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout_X49_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X49_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .mask = 16'hEAEF;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|Add4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|Add4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .mask = 16'h01FE;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X49_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .mask = 16'hFCFC;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X49_Y4_N0
alta_clkenctrl clken_ctrl_X49_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[1]|rx_data_cnt[1]~3_combout_X49_Y4_SIG_SIG ));
defparam clken_ctrl_X49_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X49_Y4_N0
alta_asyncctrl asyncreset_ctrl_X49_Y4_N0(.Din(), .Dout(AsyncReset_X49_Y4_GND));
defparam asyncreset_ctrl_X49_Y4_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X49_Y4_N1
alta_clkenctrl clken_ctrl_X49_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[4]|rx_data_cnt[0]~3_combout_X49_Y4_SIG_SIG ));
defparam clken_ctrl_X49_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X49_Y4_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X50_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_shift_reg [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] (
// Location: LCCOMB_X50_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X50_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always11~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always11~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [4]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always11~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~0 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] (
// Location: LCCOMB_X50_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X50_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(SyncReset_X50_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_stop~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .mask = 16'h0055;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[7] .SyncLoadMux = 2'b01;
// Location: FF_X50_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] (
// Location: LCCOMB_X50_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Add4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .mask = 16'h1130;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector0~0 (
// Location: FF_X50_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .mask = 16'h00F3;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en (
// Location: LCCOMB_X50_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .mask = 16'hDCFC;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always2~1 (
// Location: FF_X50_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_bit (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_sample~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [7]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X50_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(SyncReset_X50_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X50_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always8~0 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|always3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_idle_en~q ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .mask = 16'hFFF0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [6]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X50_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(SyncReset_X50_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y1_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: FF_X50_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_idle (
// Location: LCCOMB_X50_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_idle~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_idle (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|always8~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_idle~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .mask = 16'hDCFC;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_idle .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X50_Y1_N0
alta_clkenctrl clken_ctrl_X50_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[2]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[2]|always4~2_combout_X50_Y1_SIG_SIG ));
defparam clken_ctrl_X50_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X50_Y1_N0
alta_asyncctrl asyncreset_ctrl_X50_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y1_SIG ));
defparam asyncreset_ctrl_X50_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X50_Y1_N1
alta_clkenctrl clken_ctrl_X50_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y1_SIG_VCC ));
defparam clken_ctrl_X50_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X50_Y1_N1
alta_asyncctrl asyncreset_ctrl_X50_Y1_N1(.Din(), .Dout(AsyncReset_X50_Y1_GND));
defparam asyncreset_ctrl_X50_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X50_Y1_N0
alta_syncctrl syncreset_ctrl_X50_Y1(.Din(), .Dout(SyncReset_X50_Y1_GND));
defparam syncreset_ctrl_X50_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X50_Y1_N1
alta_syncctrl syncload_ctrl_X50_Y1(.Din(), .Dout(SyncLoad_X50_Y1_VCC));
defparam syncload_ctrl_X50_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X50_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .mask = 16'h1000;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|Selector0~1 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] (
// Location: LCCOMB_X50_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout__SyncLoad_X50_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X50_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] (
// Location: LCCOMB_X50_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout__SyncLoad_X50_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X50_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] (
// Location: LCCOMB_X50_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout__SyncLoad_X50_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X50_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] (
// Location: LCCOMB_X50_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\~GND~combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(SyncReset_X50_Y2_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout__SyncLoad_X50_Y2_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X50_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector0~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector0~0 (
	.A(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [0]),
	.B(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [1]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_parity (
// Location: LCCOMB_X50_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_parity (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_parity~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux1~5 (
// Location: FF_X50_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[1] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[0]|u_regs|Mux1~2_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux1~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux1~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [1]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .mask = 16'h7340;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always11~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|always11~2 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|always11~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|always11~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en (
// Location: LCCOMB_X50_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_idle_en~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .mask = 16'hFAAA;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|always2~1 (
// Location: FF_X50_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_bit (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[1]|always2~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_bit~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N28
// alta_lcell_ff \macro_inst|u_ahb2apb|hdone (
// Location: LCCOMB_X50_Y2_N28
// alta_lcell_comb \macro_inst|u_ahb2apb|hdone~0 (
alta_slice \macro_inst|u_ahb2apb|hdone (
	.A(\macro_inst|u_ahb2apb|hreadyout~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_ahb2apb|pvalid~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|hdone~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|hdone~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|hdone~q ));
defparam \macro_inst|u_ahb2apb|hdone .mask = 16'hAAA0;
defparam \macro_inst|u_ahb2apb|hdone .mode = "logic";
defparam \macro_inst|u_ahb2apb|hdone .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hdone .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|hdone .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hdone .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|hdone .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|hdone .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|hdone .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|hdone .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|interrupts[2] (
// Location: LCCOMB_X50_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~14 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts[2] (
	.A(\macro_inst|u_uart[0]|u_regs|interrupts~11_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|interrupts~10_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|interrupts~13_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|interrupts~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|interrupts [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~14_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|interrupts [2]));
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|always2~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_parity~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .mask = 16'h4080;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N6
// alta_lcell_ff \macro_inst|u_ahb2apb|hreadyout (
// Location: LCCOMB_X50_Y2_N6
// alta_lcell_comb \macro_inst|u_ahb2apb|hreadyout~0 (
alta_slice \macro_inst|u_ahb2apb|hreadyout (
	.A(\macro_inst|u_ahb2apb|pdone~q ),
	.B(\rv32.mem_ahb_htrans[1] ),
	.C(vcc),
	.D(\macro_inst|u_ahb2apb|hdone~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|hreadyout~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|hreadyout~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|hreadyout~q ));
defparam \macro_inst|u_ahb2apb|hreadyout .mask = 16'h5CFC;
defparam \macro_inst|u_ahb2apb|hreadyout .mode = "logic";
defparam \macro_inst|u_ahb2apb|hreadyout .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hreadyout .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|hreadyout .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hreadyout .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|hreadyout .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|hreadyout .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|hreadyout .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|hreadyout .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|break_error (
// Location: LCCOMB_X50_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|break_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|break_error (
	.A(\macro_inst|u_uart[0]|u_rx[0]|always11~2_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|break_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .mask = 16'hFAAA;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|break_error .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X50_Y2_N0
alta_clkenctrl clken_ctrl_X50_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y2_SIG_VCC ));
defparam clken_ctrl_X50_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X50_Y2_N0
alta_asyncctrl asyncreset_ctrl_X50_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y2_SIG ));
defparam asyncreset_ctrl_X50_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X50_Y2_N1
alta_clkenctrl clken_ctrl_X50_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X50_Y2_SIG_VCC ));
defparam clken_ctrl_X50_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y2_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X50_Y2_N1
alta_asyncctrl asyncreset_ctrl_X50_Y2_N1(.Din(), .Dout(AsyncReset_X50_Y2_GND));
defparam asyncreset_ctrl_X50_Y2_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X50_Y2_N0
alta_syncctrl syncreset_ctrl_X50_Y2(.Din(), .Dout(SyncReset_X50_Y2_GND));
defparam syncreset_ctrl_X50_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X50_Y2_N1
alta_syncctrl syncload_ctrl_X50_Y2(.Din(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout ), .Dout(\macro_inst|u_uart[0]|u_rx[1]|always6~1_combout__SyncLoad_X50_Y2_SIG ));
defparam syncload_ctrl_X50_Y2.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X50_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|comb~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|comb~1 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .mask = 16'h4040;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|comb~1 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt (
// Location: LCCOMB_X50_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ),
	.AsyncReset(AsyncReset_X50_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .mask = 16'hFAF0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector2~0 (
// Location: FF_X50_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|always0~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .mask = 16'hBA30;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector3~1 (
// Location: FF_X50_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|always0~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|Selector3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .mask = 16'hFF80;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .mask = 16'hEEC4;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] (
// Location: LCCOMB_X50_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout_X50_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_bit (
// Location: LCCOMB_X50_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_bit (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|always6~1_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y3_SIG ),
	.SyncReset(SyncReset_X50_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .mask = 16'hFFA0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_bit .SyncLoadMux = 2'b01;
// Location: LCCOMB_X50_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .mask = 16'h0078;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector4~1 (
// Location: FF_X50_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|Selector4~0_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .mask = 16'hDCCC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] (
// Location: LCCOMB_X50_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout_X50_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .mask = 16'hFAAF;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] (
// Location: LCCOMB_X50_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_read [4]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .mask = 16'h5F50;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X50_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] (
// Location: LCCOMB_X50_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout_X50_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X50_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .mask = 16'hFCED;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|always0~0 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .mask = 16'h0010;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|always0~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X50_Y3_N0
alta_clkenctrl clken_ctrl_X50_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X50_Y3_SIG_VCC ));
defparam clken_ctrl_X50_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X50_Y3_N0
alta_asyncctrl asyncreset_ctrl_X50_Y3_N0(.Din(), .Dout(AsyncReset_X50_Y3_GND));
defparam asyncreset_ctrl_X50_Y3_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X50_Y3_N1
alta_clkenctrl clken_ctrl_X50_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_data_cnt[2]~1_combout_X50_Y3_SIG_SIG ));
defparam clken_ctrl_X50_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y3_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X50_Y3_N1
alta_asyncctrl asyncreset_ctrl_X50_Y3_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y3_SIG ));
defparam asyncreset_ctrl_X50_Y3_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X50_Y3_N0
alta_syncctrl syncreset_ctrl_X50_Y3(.Din(), .Dout(SyncReset_X50_Y3_GND));
defparam syncreset_ctrl_X50_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X50_Y3_N1
alta_syncctrl syncload_ctrl_X50_Y3(.Din(), .Dout(SyncLoad_X50_Y3_VCC));
defparam syncload_ctrl_X50_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X50_Y4_N0
// alta_lcell_comb \gpio9_io_in[0] (
alta_slice \gpio9_io_in[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[0]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[0] .mask = 16'h0000;
defparam \gpio9_io_in[0] .mode = "logic";
defparam \gpio9_io_in[0] .modeMux = 1'b0;
defparam \gpio9_io_in[0] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[0] .ShiftMux = 1'b0;
defparam \gpio9_io_in[0] .BypassEn = 1'b0;
defparam \gpio9_io_in[0] .CarryEnb = 1'b1;
defparam \gpio9_io_in[0] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[0] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N10
// alta_lcell_comb \gpio9_io_in[5] (
alta_slice \gpio9_io_in[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[5]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[5] .mask = 16'h0000;
defparam \gpio9_io_in[5] .mode = "logic";
defparam \gpio9_io_in[5] .modeMux = 1'b0;
defparam \gpio9_io_in[5] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[5] .ShiftMux = 1'b0;
defparam \gpio9_io_in[5] .BypassEn = 1'b0;
defparam \gpio9_io_in[5] .CarryEnb = 1'b1;
defparam \gpio9_io_in[5] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[5] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N12
// alta_lcell_comb \gpio9_io_in[6] (
alta_slice \gpio9_io_in[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[6]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[6] .mask = 16'h0000;
defparam \gpio9_io_in[6] .mode = "logic";
defparam \gpio9_io_in[6] .modeMux = 1'b0;
defparam \gpio9_io_in[6] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[6] .ShiftMux = 1'b0;
defparam \gpio9_io_in[6] .BypassEn = 1'b0;
defparam \gpio9_io_in[6] .CarryEnb = 1'b1;
defparam \gpio9_io_in[6] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[6] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N14
// alta_lcell_comb \gpio9_io_in[7] (
alta_slice \gpio9_io_in[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[7]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[7] .mask = 16'h0000;
defparam \gpio9_io_in[7] .mode = "logic";
defparam \gpio9_io_in[7] .modeMux = 1'b0;
defparam \gpio9_io_in[7] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[7] .ShiftMux = 1'b0;
defparam \gpio9_io_in[7] .BypassEn = 1'b0;
defparam \gpio9_io_in[7] .CarryEnb = 1'b1;
defparam \gpio9_io_in[7] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[7] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .mask = 16'h0400;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N18
// alta_lcell_comb \macro_inst|SIM_IO_12~1 (
// Location: FF_X50_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] (
	.A(\rv32.gpio8_io_out_en[1] ),
	.B(\rv32.gpio8_io_out_data[1] ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\rv32.gpio8_io_out_en[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|parity_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X50_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y4_SIG ),
	.SyncReset(SyncReset_X50_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y4_VCC),
	.LutOut(\macro_inst|SIM_IO_12~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|parity_error_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X50_Y4_N22
// alta_lcell_comb \macro_inst|SIM_IO_13~1 (
// Location: FF_X50_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] (
	.A(\rv32.gpio8_io_out_data[3] ),
	.B(\rv32.gpio8_io_out_en[3] ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\rv32.gpio8_io_out_en[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|framing_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X50_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y4_SIG ),
	.SyncReset(SyncReset_X50_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X50_Y4_VCC),
	.LutOut(\macro_inst|SIM_IO_13~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|framing_error_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X50_Y4_N4
// alta_lcell_comb \gpio9_io_in[2] (
alta_slice \gpio9_io_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[2]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[2] .mask = 16'h0000;
defparam \gpio9_io_in[2] .mode = "logic";
defparam \gpio9_io_in[2] .modeMux = 1'b0;
defparam \gpio9_io_in[2] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[2] .ShiftMux = 1'b0;
defparam \gpio9_io_in[2] .BypassEn = 1'b0;
defparam \gpio9_io_in[2] .CarryEnb = 1'b1;
defparam \gpio9_io_in[2] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[2] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N6
// alta_lcell_comb \gpio9_io_in[3] (
alta_slice \gpio9_io_in[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[3]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[3] .mask = 16'h0000;
defparam \gpio9_io_in[3] .mode = "logic";
defparam \gpio9_io_in[3] .modeMux = 1'b0;
defparam \gpio9_io_in[3] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[3] .ShiftMux = 1'b0;
defparam \gpio9_io_in[3] .BypassEn = 1'b0;
defparam \gpio9_io_in[3] .CarryEnb = 1'b1;
defparam \gpio9_io_in[3] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[3] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X50_Y4_N8
// alta_lcell_comb \gpio9_io_in[4] (
alta_slice \gpio9_io_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio9_io_in[4]),
	.Cout(),
	.Q());
defparam \gpio9_io_in[4] .mask = 16'h0000;
defparam \gpio9_io_in[4] .mode = "logic";
defparam \gpio9_io_in[4] .modeMux = 1'b0;
defparam \gpio9_io_in[4] .FeedbackMux = 1'b0;
defparam \gpio9_io_in[4] .ShiftMux = 1'b0;
defparam \gpio9_io_in[4] .BypassEn = 1'b0;
defparam \gpio9_io_in[4] .CarryEnb = 1'b1;
defparam \gpio9_io_in[4] .AsyncResetMux = 2'bxx;
defparam \gpio9_io_in[4] .SyncResetMux = 2'bxx;
defparam \gpio9_io_in[4] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X50_Y4_N0
alta_clkenctrl clken_ctrl_X50_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X50_Y4_SIG_SIG ));
defparam clken_ctrl_X50_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X50_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X50_Y4_N0
alta_asyncctrl asyncreset_ctrl_X50_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X50_Y4_SIG ));
defparam asyncreset_ctrl_X50_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X50_Y4_N0
alta_syncctrl syncreset_ctrl_X50_Y4(.Din(), .Dout(SyncReset_X50_Y4_GND));
defparam syncreset_ctrl_X50_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X50_Y4_N1
alta_syncctrl syncload_ctrl_X50_Y4(.Din(), .Dout(SyncLoad_X50_Y4_VCC));
defparam syncload_ctrl_X50_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X51_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .mask = 16'hECA0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] (
// Location: LCCOMB_X51_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .mask = 16'hFFE1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .mask = 16'hFBC0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector2~0 (
// Location: FF_X51_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|always0~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .mask = 16'hBA30;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|Selector5~3_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .mask = 16'h57F7;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|always0~0 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .mask = 16'h0100;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|always0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] (
// Location: LCCOMB_X51_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] (
// Location: LCCOMB_X51_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout_X51_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .mask = 16'hFFC3;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector5~4 (
// Location: FF_X51_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|uart_txd (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|Selector5~2_combout ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|uart_txd~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .mask = 16'h0030;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .mask = 16'h00F0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector4~1 (
// Location: FF_X51_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_tx[5]|Selector4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .mask = 16'hBAAA;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_parity (
// Location: LCCOMB_X51_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_parity (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X51_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_parity~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector3~1 (
// Location: FF_X51_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_tx[5]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .mask = 16'hEAAA;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_PARITY~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .mask = 16'h00CC;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .mask = 16'hFFC0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X51_Y1_N0
alta_clkenctrl clken_ctrl_X51_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_data_cnt[0]~1_combout_X51_Y1_SIG_SIG ));
defparam clken_ctrl_X51_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X51_Y1_N0
alta_asyncctrl asyncreset_ctrl_X51_Y1_N0(.Din(), .Dout(AsyncReset_X51_Y1_GND));
defparam asyncreset_ctrl_X51_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X51_Y1_N1
alta_clkenctrl clken_ctrl_X51_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y1_SIG_VCC ));
defparam clken_ctrl_X51_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X51_Y1_N1
alta_asyncctrl asyncreset_ctrl_X51_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y1_SIG ));
defparam asyncreset_ctrl_X51_Y1_N1.AsyncCtrlMux = 2'b10;
// Location: FF_X51_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_complete (
// Location: LCCOMB_X51_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_complete~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_complete (
	.A(\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_complete~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .mask = 16'h2232;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|break_error (
// Location: LCCOMB_X51_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|break_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[1]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|break_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .mask = 16'hCCFC;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector0~0 (
// Location: FF_X51_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE (
	.A(\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .mask = 16'hFF50;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] (
// Location: LCCOMB_X51_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|always3~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Add4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .mask = 16'hECEF;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] (
// Location: LCCOMB_X51_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|tx_write [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .mask = 16'h5C0C;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|always3~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|always3~1 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~1 (
	.A(\macro_inst|u_uart[0]|u_regs|parity_error_ie [0]),
	.B(\macro_inst|u_uart[0]|u_regs|framing_error_ie [0]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|parity_error~q ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|framing_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .mask = 16'hECA0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~1 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] (
// Location: LCCOMB_X51_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|always3~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .mask = 16'hCDCF;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|overrun_error (
// Location: LCCOMB_X51_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|overrun_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|overrun_error (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|overrun_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|overrun_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .mask = 16'hFEFF;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[0]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|fifo_rden (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|fifo_rden (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .mask = 16'hF500;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .mask = 16'h0400;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[1]~13 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|parity_error (
// Location: LCCOMB_X51_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|parity_error~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|parity_error (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|parity_error~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|parity_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|parity_error (
// Location: LCCOMB_X51_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|parity_error~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|parity_error (
	.A(\macro_inst|u_uart[0]|u_rx[1]|parity_error~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_sample~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|parity_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] (
// Location: LCCOMB_X51_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_rx[0]|Add4~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout_X51_Y2_SIG_SIG ),
	.AsyncReset(AsyncReset_X51_Y2_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .mask = 16'hCDCF;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|overrun_error (
// Location: LCCOMB_X51_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|overrun_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|overrun_error (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|overrun_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|overrun_error .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X51_Y2_N0
alta_clkenctrl clken_ctrl_X51_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X51_Y2_SIG_VCC ));
defparam clken_ctrl_X51_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X51_Y2_N0
alta_asyncctrl asyncreset_ctrl_X51_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y2_SIG ));
defparam asyncreset_ctrl_X51_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X51_Y2_N1
alta_clkenctrl clken_ctrl_X51_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt[1]~3_combout_X51_Y2_SIG_SIG ));
defparam clken_ctrl_X51_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y2_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X51_Y2_N1
alta_asyncctrl asyncreset_ctrl_X51_Y2_N1(.Din(), .Dout(AsyncReset_X51_Y2_GND));
defparam asyncreset_ctrl_X51_Y2_N1.AsyncCtrlMux = 2'b00;
// Location: LCCOMB_X51_Y3_N0
// alta_lcell_comb \gpio8_io_out_en[7] (
alta_slice \gpio8_io_out_en[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\rv32.gpio8_io_out_en[7] ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(gpio8_io_out_en[7]),
	.Cout(),
	.Q());
defparam \gpio8_io_out_en[7] .mask = 16'h00FF;
defparam \gpio8_io_out_en[7] .mode = "logic";
defparam \gpio8_io_out_en[7] .modeMux = 1'b0;
defparam \gpio8_io_out_en[7] .FeedbackMux = 1'b0;
defparam \gpio8_io_out_en[7] .ShiftMux = 1'b0;
defparam \gpio8_io_out_en[7] .BypassEn = 1'b0;
defparam \gpio8_io_out_en[7] .CarryEnb = 1'b1;
defparam \gpio8_io_out_en[7] .AsyncResetMux = 2'bxx;
defparam \gpio8_io_out_en[7] .SyncResetMux = 2'bxx;
defparam \gpio8_io_out_en[7] .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y3_N10
// alta_lcell_ff \macro_inst|sim_clk_cnt[1] (
// Location: LCCOMB_X51_Y3_N10
// alta_lcell_comb \macro_inst|sim_clk_cnt[1]~10 (
alta_slice \macro_inst|sim_clk_cnt[1] (
	.A(\macro_inst|sim_clk_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[0]~9 ),
	.Qin(\macro_inst|sim_clk_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[1]~10_combout ),
	.Cout(\macro_inst|sim_clk_cnt[1]~11 ),
	.Q(\macro_inst|sim_clk_cnt [1]));
defparam \macro_inst|sim_clk_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|sim_clk_cnt[1] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X51_Y3_N12
// alta_lcell_ff \macro_inst|sim_clk_cnt[2] (
// Location: LCCOMB_X51_Y3_N12
// alta_lcell_comb \macro_inst|sim_clk_cnt[2]~12 (
alta_slice \macro_inst|sim_clk_cnt[2] (
	.A(\macro_inst|sim_clk_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[1]~11 ),
	.Qin(\macro_inst|sim_clk_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[2]~12_combout ),
	.Cout(\macro_inst|sim_clk_cnt[2]~13 ),
	.Q(\macro_inst|sim_clk_cnt [2]));
defparam \macro_inst|sim_clk_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|sim_clk_cnt[2] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X51_Y3_N14
// alta_lcell_ff \macro_inst|sim_clk_cnt[3] (
// Location: LCCOMB_X51_Y3_N14
// alta_lcell_comb \macro_inst|sim_clk_cnt[3]~14 (
alta_slice \macro_inst|sim_clk_cnt[3] (
	.A(vcc),
	.B(\macro_inst|sim_clk_cnt [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[2]~13 ),
	.Qin(\macro_inst|sim_clk_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[3]~14_combout ),
	.Cout(\macro_inst|sim_clk_cnt[3]~15 ),
	.Q(\macro_inst|sim_clk_cnt [3]));
defparam \macro_inst|sim_clk_cnt[3] .mask = 16'h3C3F;
defparam \macro_inst|sim_clk_cnt[3] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X51_Y3_N16
// alta_lcell_ff \macro_inst|sim_clk_cnt[4] (
// Location: LCCOMB_X51_Y3_N16
// alta_lcell_comb \macro_inst|sim_clk_cnt[4]~16 (
alta_slice \macro_inst|sim_clk_cnt[4] (
	.A(vcc),
	.B(\macro_inst|sim_clk_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[3]~15 ),
	.Qin(\macro_inst|sim_clk_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[4]~16_combout ),
	.Cout(\macro_inst|sim_clk_cnt[4]~17 ),
	.Q(\macro_inst|sim_clk_cnt [4]));
defparam \macro_inst|sim_clk_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|sim_clk_cnt[4] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[4] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[4] .SyncLoadMux = 2'b00;
// Location: FF_X51_Y3_N18
// alta_lcell_ff \macro_inst|sim_clk_cnt[5] (
// Location: LCCOMB_X51_Y3_N18
// alta_lcell_comb \macro_inst|sim_clk_cnt[5]~18 (
alta_slice \macro_inst|sim_clk_cnt[5] (
	.A(vcc),
	.B(\macro_inst|sim_clk_cnt [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[4]~17 ),
	.Qin(\macro_inst|sim_clk_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[5]~18_combout ),
	.Cout(\macro_inst|sim_clk_cnt[5]~19 ),
	.Q(\macro_inst|sim_clk_cnt [5]));
defparam \macro_inst|sim_clk_cnt[5] .mask = 16'h3C3F;
defparam \macro_inst|sim_clk_cnt[5] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[5] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[5] .SyncLoadMux = 2'b00;
// Location: FF_X51_Y3_N20
// alta_lcell_ff \macro_inst|sim_clk_cnt[6] (
// Location: LCCOMB_X51_Y3_N20
// alta_lcell_comb \macro_inst|sim_clk_cnt[6]~20 (
alta_slice \macro_inst|sim_clk_cnt[6] (
	.A(vcc),
	.B(\macro_inst|sim_clk_cnt [6]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[5]~19 ),
	.Qin(\macro_inst|sim_clk_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[6]~20_combout ),
	.Cout(\macro_inst|sim_clk_cnt[6]~21 ),
	.Q(\macro_inst|sim_clk_cnt [6]));
defparam \macro_inst|sim_clk_cnt[6] .mask = 16'hC30C;
defparam \macro_inst|sim_clk_cnt[6] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[6] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[6] .SyncLoadMux = 2'b00;
// Location: FF_X51_Y3_N22
// alta_lcell_ff \macro_inst|sim_clk_cnt[7] (
// Location: LCCOMB_X51_Y3_N22
// alta_lcell_comb \macro_inst|sim_clk_cnt[7]~22 (
alta_slice \macro_inst|sim_clk_cnt[7] (
	.A(\macro_inst|sim_clk_cnt [7]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|sim_clk_cnt[6]~21 ),
	.Qin(\macro_inst|sim_clk_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[7]~22_combout ),
	.Cout(),
	.Q(\macro_inst|sim_clk_cnt [7]));
defparam \macro_inst|sim_clk_cnt[7] .mask = 16'h5A5A;
defparam \macro_inst|sim_clk_cnt[7] .mode = "ripple";
defparam \macro_inst|sim_clk_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|sim_clk_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[7] .CarryEnb = 1'b1;
defparam \macro_inst|sim_clk_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[7] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[7] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X51_Y3_N24
// alta_lcell_comb \macro_inst|LessThan0~1 (
alta_slice \macro_inst|LessThan0~1 (
	.A(\macro_inst|sim_clk_cnt [7]),
	.B(\macro_inst|sim_clk_cnt [6]),
	.C(\macro_inst|sim_clk_cnt [5]),
	.D(\macro_inst|sim_clk_cnt [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|LessThan0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|LessThan0~1 .mask = 16'h0001;
defparam \macro_inst|LessThan0~1 .mode = "logic";
defparam \macro_inst|LessThan0~1 .modeMux = 1'b0;
defparam \macro_inst|LessThan0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|LessThan0~1 .ShiftMux = 1'b0;
defparam \macro_inst|LessThan0~1 .BypassEn = 1'b0;
defparam \macro_inst|LessThan0~1 .CarryEnb = 1'b1;
defparam \macro_inst|LessThan0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|LessThan0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|LessThan0~1 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y3_N26
// alta_lcell_ff \macro_inst|sim_clk_reg (
// Location: LCCOMB_X51_Y3_N26
// alta_lcell_comb \macro_inst|sim_clk_reg~0 (
alta_slice \macro_inst|sim_clk_reg (
	.A(\macro_inst|LessThan0~0_combout ),
	.B(\macro_inst|LessThan0~1_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|sim_clk_reg~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|sim_clk_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|sim_clk_reg~q ));
defparam \macro_inst|sim_clk_reg .mask = 16'h8787;
defparam \macro_inst|sim_clk_reg .mode = "logic";
defparam \macro_inst|sim_clk_reg .modeMux = 1'b0;
defparam \macro_inst|sim_clk_reg .FeedbackMux = 1'b1;
defparam \macro_inst|sim_clk_reg .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_reg .BypassEn = 1'b0;
defparam \macro_inst|sim_clk_reg .CarryEnb = 1'b1;
defparam \macro_inst|sim_clk_reg .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_reg .SyncResetMux = 2'bxx;
defparam \macro_inst|sim_clk_reg .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N28
// alta_lcell_comb \macro_inst|LessThan0~2 (
alta_slice \macro_inst|LessThan0~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|LessThan0~0_combout ),
	.D(\macro_inst|LessThan0~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|LessThan0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|LessThan0~2 .mask = 16'h0FFF;
defparam \macro_inst|LessThan0~2 .mode = "logic";
defparam \macro_inst|LessThan0~2 .modeMux = 1'b0;
defparam \macro_inst|LessThan0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|LessThan0~2 .ShiftMux = 1'b0;
defparam \macro_inst|LessThan0~2 .BypassEn = 1'b0;
defparam \macro_inst|LessThan0~2 .CarryEnb = 1'b1;
defparam \macro_inst|LessThan0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|LessThan0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|LessThan0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y3_N30
// alta_lcell_comb \macro_inst|LessThan0~0 (
alta_slice \macro_inst|LessThan0~0 (
	.A(\macro_inst|sim_clk_cnt [2]),
	.B(\macro_inst|sim_clk_cnt [3]),
	.C(\macro_inst|sim_clk_cnt [0]),
	.D(\macro_inst|sim_clk_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|LessThan0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|LessThan0~0 .mask = 16'h1333;
defparam \macro_inst|LessThan0~0 .mode = "logic";
defparam \macro_inst|LessThan0~0 .modeMux = 1'b0;
defparam \macro_inst|LessThan0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|LessThan0~0 .ShiftMux = 1'b0;
defparam \macro_inst|LessThan0~0 .BypassEn = 1'b0;
defparam \macro_inst|LessThan0~0 .CarryEnb = 1'b1;
defparam \macro_inst|LessThan0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|LessThan0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|LessThan0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X51_Y3_N8
// alta_lcell_ff \macro_inst|sim_clk_cnt[0] (
// Location: LCCOMB_X51_Y3_N8
// alta_lcell_comb \macro_inst|sim_clk_cnt[0]~8 (
alta_slice \macro_inst|sim_clk_cnt[0] (
	.A(vcc),
	.B(\macro_inst|sim_clk_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|sim_clk_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ),
	.SyncReset(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y3_GND),
	.LutOut(\macro_inst|sim_clk_cnt[0]~8_combout ),
	.Cout(\macro_inst|sim_clk_cnt[0]~9 ),
	.Q(\macro_inst|sim_clk_cnt [0]));
defparam \macro_inst|sim_clk_cnt[0] .mask = 16'h33CC;
defparam \macro_inst|sim_clk_cnt[0] .mode = "logic";
defparam \macro_inst|sim_clk_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|sim_clk_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|sim_clk_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|sim_clk_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|sim_clk_cnt[0] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X51_Y3_N0
alta_clkenctrl clken_ctrl_X51_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp_X51_Y3_SIG_VCC ));
defparam clken_ctrl_X51_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X51_Y3_N0
alta_asyncctrl asyncreset_ctrl_X51_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y3_SIG ));
defparam asyncreset_ctrl_X51_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X51_Y3_N0
alta_syncctrl syncreset_ctrl_X51_Y3(.Din(\macro_inst|LessThan0~2_combout ), .Dout(\macro_inst|LessThan0~2_combout__SyncReset_X51_Y3_SIG ));
defparam syncreset_ctrl_X51_Y3.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X51_Y3_N1
alta_syncctrl syncload_ctrl_X51_Y3(.Din(), .Dout(SyncLoad_X51_Y3_GND));
defparam syncload_ctrl_X51_Y3.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X51_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Add4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Add4~2 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .mask = 16'h3C3C;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux11~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux11~0 (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux11~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .mask = 16'h8A80;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Add4~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Add4~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .mask = 16'h03FC;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~11 (
// Location: FF_X51_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[0] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_dma_en [5]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_dma_en [4]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector12~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X51_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y4_SIG ),
	.SyncReset(\macro_inst|u_ahb2apb|paddr[7]__SyncReset_X51_Y4_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y4_GND),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [0]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X51_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~10 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~10 (
	.A(\macro_inst|u_uart[1]|u_regs|Selector12~1_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~7_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector12~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .mask = 16'h8F83;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~10 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~10 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector12~1_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~7_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector12~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .mask = 16'h8F83;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|Add4~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|Add4~0 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .mask = 16'h5556;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X51_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~11 (
// Location: FF_X51_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[0] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_dma_en [5]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|rx_dma_en [4]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector12~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X51_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y4_SIG ),
	.SyncReset(\macro_inst|u_ahb2apb|paddr[7]__SyncReset_X51_Y4_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X51_Y4_GND),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [0]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[0] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X51_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .mask = 16'hF0AA;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~8 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X51_Y4_N0
alta_clkenctrl clken_ctrl_X51_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X51_Y4_SIG_SIG ));
defparam clken_ctrl_X51_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X51_Y4_N0
alta_asyncctrl asyncreset_ctrl_X51_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X51_Y4_SIG ));
defparam asyncreset_ctrl_X51_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X51_Y4_N1
alta_clkenctrl clken_ctrl_X51_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X51_Y4_SIG_SIG ));
defparam clken_ctrl_X51_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X51_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X51_Y4_N0
alta_syncctrl syncreset_ctrl_X51_Y4(.Din(\macro_inst|u_ahb2apb|paddr [7]), .Dout(\macro_inst|u_ahb2apb|paddr[7]__SyncReset_X51_Y4_SIG ));
defparam syncreset_ctrl_X51_Y4.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X51_Y4_N1
alta_syncctrl syncload_ctrl_X51_Y4(.Din(), .Dout(SyncLoad_X51_Y4_GND));
defparam syncload_ctrl_X51_Y4.SyncCtrlMux = 2'b00;
// Location: FF_X52_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] (
// Location: LCCOMB_X52_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][2]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] (
// Location: LCCOMB_X52_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][5]~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [6]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .mask = 16'hAACC;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] (
// Location: LCCOMB_X52_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][0]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] (
// Location: LCCOMB_X52_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] (
// Location: LCCOMB_X52_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] (
// Location: LCCOMB_X52_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] (
// Location: LCCOMB_X52_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][7]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] (
// Location: LCCOMB_X52_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [5]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] (
// Location: LCCOMB_X52_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(SyncReset_X52_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: FF_X52_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X52_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X52_Y1_N0
alta_clkenctrl clken_ctrl_X52_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout_X52_Y1_SIG_SIG ));
defparam clken_ctrl_X52_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X52_Y1_N0
alta_asyncctrl asyncreset_ctrl_X52_Y1_N0(.Din(), .Dout(AsyncReset_X52_Y1_GND));
defparam asyncreset_ctrl_X52_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X52_Y1_N1
alta_clkenctrl clken_ctrl_X52_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[5]|tx_shift_reg[5]~1_combout_X52_Y1_SIG_SIG ));
defparam clken_ctrl_X52_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X52_Y1_N1
alta_asyncctrl asyncreset_ctrl_X52_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y1_SIG ));
defparam asyncreset_ctrl_X52_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X52_Y1_N0
alta_syncctrl syncreset_ctrl_X52_Y1(.Din(), .Dout(SyncReset_X52_Y1_GND));
defparam syncreset_ctrl_X52_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X52_Y1_N1
alta_syncctrl syncload_ctrl_X52_Y1(.Din(), .Dout(SyncLoad_X52_Y1_VCC));
defparam syncload_ctrl_X52_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X52_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector2~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector2~0 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [0]),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .mask = 16'hAEA4;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector1~0 (
// Location: FF_X52_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .mask = 16'hBA98;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X52_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .mask = 16'h0004;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~5 (
// Location: FF_X52_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] (
	.A(\macro_inst|u_uart[0]|u_regs|framing_error_ie [1]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|framing_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|framing_error_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[0] .SyncLoadMux = 2'b01;
// Location: FF_X52_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|framing_error (
// Location: LCCOMB_X52_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|framing_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|framing_error (
	.A(\macro_inst|u_uart[0]|u_rx[1]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|framing_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .mask = 16'h44F4;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|framing_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~7 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~7 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [1]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .mask = 16'hE3E0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~6 (
// Location: FF_X52_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] (
	.A(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [1]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X52_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector4~0 (
// Location: FF_X52_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[0]|u_regs|parity_error_ie [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|parity_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|parity_error_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .mask = 16'hBA98;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[0] .SyncLoadMux = 2'b01;
// Location: FF_X52_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|interrupts[0] (
// Location: LCCOMB_X52_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts[0] (
	.A(\macro_inst|u_uart[0]|u_regs|interrupts~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|interrupts~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|interrupts~3_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|interrupts~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|interrupts [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|interrupts [0]));
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector3~0 (
// Location: FF_X52_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|break_error_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|break_error_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[0]|u_regs|break_error_ie [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|break_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|break_error_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .mask = 16'hBA98;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X52_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~0 (
// Location: FF_X52_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .mask = 16'hD5C0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X52_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~2 (
// Location: FF_X52_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|overrun_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|break_error_ie [0]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[0]|u_rx[0]|break_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .mask = 16'hECA0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[0] .SyncLoadMux = 2'b01;
// Location: FF_X52_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|framing_error (
// Location: LCCOMB_X52_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|framing_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|framing_error (
	.A(\macro_inst|u_uart[0]|u_rx[0]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|framing_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .mask = 16'hF444;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|framing_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~3 (
// Location: FF_X52_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [0]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|rx_idle~q ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_complete~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(SyncReset_X52_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [0]));
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[0] .SyncLoadMux = 2'b01;
// Location: FF_X52_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_complete (
// Location: LCCOMB_X52_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_complete~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_complete (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_complete~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .mask = 16'h5444;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_complete .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~12 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~12 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_complete~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_complete~q ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .mask = 16'hFC22;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~12 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X52_Y2_N0
alta_clkenctrl clken_ctrl_X52_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~16_combout_X52_Y2_SIG_SIG ));
defparam clken_ctrl_X52_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X52_Y2_N0
alta_asyncctrl asyncreset_ctrl_X52_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y2_SIG ));
defparam asyncreset_ctrl_X52_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X52_Y2_N1
alta_clkenctrl clken_ctrl_X52_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y2_SIG_VCC ));
defparam clken_ctrl_X52_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y2_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X52_Y2_N0
alta_syncctrl syncreset_ctrl_X52_Y2(.Din(), .Dout(SyncReset_X52_Y2_GND));
defparam syncreset_ctrl_X52_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X52_Y2_N1
alta_syncctrl syncload_ctrl_X52_Y2(.Din(), .Dout(SyncLoad_X52_Y2_VCC));
defparam syncload_ctrl_X52_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X52_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_idle (
// Location: LCCOMB_X52_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_idle~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_idle (
	.A(\macro_inst|u_uart[0]|u_rx[1]|always8~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_idle~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .mask = 16'hBAFA;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_read[0] (
// Location: LCCOMB_X52_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_read~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_read[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_read [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_read~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_read [0]));
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[0] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] (
// Location: LCCOMB_X52_Y3_N14
// alta_lcell_comb \macro_inst|uart_rxd[11] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.C(\SIM_IO[11]~input_o ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X52_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [11]),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_in [0]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .mask = 16'h0303;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always2~1 (
// Location: FF_X52_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_bit (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req (
// Location: LCCOMB_X52_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_dma_en [0]),
	.C(vcc),
	.D(\rv32.ext_dma_DMACCLR[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_dma_req~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .mask = 16'h00C8;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_dma_req .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en (
// Location: LCCOMB_X52_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_idle_en~q ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .mask = 16'hFF70;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .mask = 16'h0020;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|Equal1~1 (
alta_slice \macro_inst|u_uart[0]|u_baud|Equal1~1 (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [8]),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [7]),
	.C(\macro_inst|u_uart[0]|u_baud|i_cnt [6]),
	.D(\macro_inst|u_uart[0]|u_baud|i_cnt [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|Equal1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~1 .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en (
// Location: LCCOMB_X52_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_idle_en~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .mask = 16'hFF70;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] (
// Location: LCCOMB_X52_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_read [0]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|Selector1~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .mask = 16'h5F50;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_idle (
// Location: LCCOMB_X52_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[0]|rx_idle~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_idle (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[0]|always8~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[0]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_idle~q ));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .mask = 16'hFF70;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_idle .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always2~0 (
// Location: FF_X52_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_in [0]),
	.D(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X52_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ),
	.SyncReset(SyncReset_X52_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_in [1]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[1] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X52_Y3_N0
alta_clkenctrl clken_ctrl_X52_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y3_SIG_VCC ));
defparam clken_ctrl_X52_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X52_Y3_N0
alta_asyncctrl asyncreset_ctrl_X52_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y3_SIG ));
defparam asyncreset_ctrl_X52_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X52_Y3_N1
alta_clkenctrl clken_ctrl_X52_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X52_Y3_SIG_SIG ));
defparam clken_ctrl_X52_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y3_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X52_Y3_N0
alta_syncctrl syncreset_ctrl_X52_Y3(.Din(), .Dout(SyncReset_X52_Y3_GND));
defparam syncreset_ctrl_X52_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X52_Y3_N1
alta_syncctrl syncload_ctrl_X52_Y3(.Din(), .Dout(SyncLoad_X52_Y3_VCC));
defparam syncload_ctrl_X52_Y3.SyncCtrlMux = 2'b01;
// Location: FF_X52_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY (
// Location: LCCOMB_X52_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Selector4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] (
// Location: LCCOMB_X52_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector4~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X52_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y4_SIG ),
	.SyncReset(SyncReset_X52_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .mask = 16'h88CC;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X52_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Selector4~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|Selector4~4_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector4~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .mask = 16'hFF8D;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|Selector4~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .mask = 16'hBBAE;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: FF_X52_Y4_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP (
// Location: LCCOMB_X52_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .mask = 16'hB3A0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X52_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~5 (
// Location: FF_X52_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] (
	.A(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [1]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X52_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y4_SIG ),
	.SyncReset(SyncReset_X52_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X52_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [1]));
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .mask = 16'hA0EC;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X52_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector4~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .mask = 16'hA2A0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector4~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X52_Y4_N0
alta_clkenctrl clken_ctrl_X52_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X52_Y4_SIG_VCC ));
defparam clken_ctrl_X52_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y4_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X52_Y4_N0
alta_asyncctrl asyncreset_ctrl_X52_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X52_Y4_SIG ));
defparam asyncreset_ctrl_X52_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X52_Y4_N1
alta_clkenctrl clken_ctrl_X52_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~17_combout_X52_Y4_SIG_SIG ));
defparam clken_ctrl_X52_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X52_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X52_Y4_N0
alta_syncctrl syncreset_ctrl_X52_Y4(.Din(), .Dout(SyncReset_X52_Y4_GND));
defparam syncreset_ctrl_X52_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X52_Y4_N1
alta_syncctrl syncload_ctrl_X52_Y4(.Din(), .Dout(SyncLoad_X52_Y4_VCC));
defparam syncload_ctrl_X52_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X53_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .mask = 16'h00F0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux11~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux11~1 (
	.A(\macro_inst|u_uart[0]|u_rx[0]|rx_fifo|counter ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux11~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .mask = 16'hFC22;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector5~4 (
// Location: FF_X53_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|uart_txd (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_tx[0]|Selector5~2_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|uart_txd~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .mask = 16'h000C;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux11~3 (
// Location: FF_X53_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|status_reg[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|status_reg[1] (
	.A(\macro_inst|u_uart[0]|u_regs|Mux11~0_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[0]|u_regs|Mux11~2_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|status_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X53_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux11~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|status_reg [1]));
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .mask = 16'h4545;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] (
// Location: LCCOMB_X53_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout__SyncReset_X53_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X53_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] (
// Location: LCCOMB_X53_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout__SyncReset_X53_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X53_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|comb~1 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .mask = 16'h0A00;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|comb~1 .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] (
// Location: LCCOMB_X53_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout__SyncReset_X53_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X53_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] (
// Location: LCCOMB_X53_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout__SyncReset_X53_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .mask = 16'h5A5A;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X53_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux12~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux12~0 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux12~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .mask = 16'hEE30;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|always6~1 (
// Location: FF_X53_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_bit (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_bit (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [3]),
	.D(\macro_inst|u_uart[0]|u_tx[0]|always6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|always6~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [0]),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|always6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux11~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux11~2 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux11~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] (
// Location: LCCOMB_X53_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_read [2]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .mask = 16'h3A3A;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] (
// Location: LCCOMB_X53_Y1_N8
// alta_lcell_comb \macro_inst|uart_rxd[0] (
alta_slice \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.D(\SIM_IO[0]~input_o ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[0]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X53_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [0]),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[0]|rx_in [0]));
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[0]|rx_in[0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X53_Y1_N0
alta_clkenctrl clken_ctrl_X53_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y1_SIG_VCC ));
defparam clken_ctrl_X53_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X53_Y1_N0
alta_asyncctrl asyncreset_ctrl_X53_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y1_SIG ));
defparam asyncreset_ctrl_X53_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X53_Y1_N1
alta_clkenctrl clken_ctrl_X53_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X53_Y1_SIG_SIG ));
defparam clken_ctrl_X53_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X53_Y1_N1
alta_asyncctrl asyncreset_ctrl_X53_Y1_N1(.Din(), .Dout(AsyncReset_X53_Y1_GND));
defparam asyncreset_ctrl_X53_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X53_Y1_N0
alta_syncctrl syncreset_ctrl_X53_Y1(.Din(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout ), .Dout(\macro_inst|u_uart[0]|u_tx[0]|tx_stop~combout__SyncReset_X53_Y1_SIG ));
defparam syncreset_ctrl_X53_Y1.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X53_Y1_N1
alta_syncctrl syncload_ctrl_X53_Y1(.Din(), .Dout(SyncLoad_X53_Y1_GND));
defparam syncload_ctrl_X53_Y1.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X53_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~17 (
// Location: FF_X53_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] (
	.A(\macro_inst|u_uart[0]|u_regs|break_error_ie [3]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|break_error~q ),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|overrun_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~17_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~15 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~15 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [3]),
	.C(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [3]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~15 .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|framing_error (
// Location: LCCOMB_X53_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|framing_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|framing_error (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|framing_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .mask = 16'h44F4;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|break_error (
// Location: LCCOMB_X53_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|break_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|break_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .mask = 16'hCCFC;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|break_error .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|parity_error (
// Location: LCCOMB_X53_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|parity_error~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|parity_error (
	.A(\macro_inst|u_uart[0]|u_rx[3]|parity_error~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_sample~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|parity_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|parity_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector4~1 (
// Location: FF_X53_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|Selector4~0_combout ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[0]|u_regs|parity_error_ie [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|parity_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|parity_error_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .mask = 16'hE6C4;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector1~1 (
// Location: FF_X53_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [2]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector1~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[3] .SyncLoadMux = 2'b01;
// Location: FF_X53_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_idle (
// Location: LCCOMB_X53_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_idle~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_idle (
	.A(\macro_inst|u_uart[0]|u_rx[3]|always8~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_idle~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .mask = 16'hAAFA;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|interrupts[3] (
// Location: LCCOMB_X53_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~19 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts[3] (
	.A(\macro_inst|u_uart[0]|u_regs|interrupts~15_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|interrupts~16_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|interrupts~18_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|interrupts~17_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|interrupts [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~19_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|interrupts [3]));
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~18 (
// Location: FF_X53_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_complete~q ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [3]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_idle~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~18_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .mask = 16'hECA0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[3] .SyncLoadMux = 2'b01;
// Location: FF_X53_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|overrun_error (
// Location: LCCOMB_X53_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|overrun_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|overrun_error (
	.A(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|overrun_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|overrun_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector3~1 (
// Location: FF_X53_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|break_error_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|break_error_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|break_error_ie [2]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|break_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|break_error_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~8 (
// Location: FF_X53_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [2]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector8~7_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~6 (
// Location: FF_X53_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|framing_error_ie [2]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector5~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|framing_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|framing_error_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~7 (
// Location: FF_X53_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [2]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~6_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ),
	.SyncReset(SyncReset_X53_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [3]));
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[3] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X53_Y2_N0
alta_clkenctrl clken_ctrl_X53_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~19_combout_X53_Y2_SIG_SIG ));
defparam clken_ctrl_X53_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X53_Y2_N0
alta_asyncctrl asyncreset_ctrl_X53_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y2_SIG ));
defparam asyncreset_ctrl_X53_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X53_Y2_N1
alta_clkenctrl clken_ctrl_X53_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y2_SIG_VCC ));
defparam clken_ctrl_X53_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y2_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X53_Y2_N0
alta_syncctrl syncreset_ctrl_X53_Y2(.Din(), .Dout(SyncReset_X53_Y2_GND));
defparam syncreset_ctrl_X53_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X53_Y2_N1
alta_syncctrl syncload_ctrl_X53_Y2(.Din(), .Dout(SyncLoad_X53_Y2_VCC));
defparam syncload_ctrl_X53_Y2.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X53_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|Equal1~3 (
// Location: FF_X53_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [15]),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [14]),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_baud|i_cnt [13]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_baud|Equal1~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .mask = 16'h0011;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|Equal1~4 (
alta_slice \macro_inst|u_uart[0]|u_baud|Equal1~4 (
	.A(\macro_inst|u_uart[0]|u_baud|Equal1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_baud|Equal1~3_combout ),
	.C(\macro_inst|u_uart[0]|u_baud|Equal1~1_combout ),
	.D(\macro_inst|u_uart[0]|u_baud|Equal1~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|Equal1~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|Equal1~0 (
alta_slice \macro_inst|u_uart[0]|u_baud|Equal1~0 (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [4]),
	.C(\macro_inst|u_uart[0]|u_baud|i_cnt [1]),
	.D(\macro_inst|u_uart[0]|u_baud|i_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|Equal1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_baud|always0~0 (
	.A(\macro_inst|u_uart[0]|u_baud|Equal1~4_combout ),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_baud|f_del~q ),
	.D(\macro_inst|u_uart[0]|u_regs|uart_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .mask = 16'h8AFF;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|always0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] (
// Location: LCCOMB_X53_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[0]|u_regs|tx_write [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector0~0 (
// Location: FF_X53_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE (
	.A(\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .mask = 16'hFF50;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START (
// Location: LCCOMB_X53_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .mask = 16'hCCEC;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] (
// Location: LCCOMB_X53_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|tx_write [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .mask = 16'h5C0C;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|always2~0 (
// Location: FF_X53_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|baud16 (
alta_slice \macro_inst|u_uart[0]|u_baud|baud16 (
	.A(\macro_inst|u_uart[0]|u_baud|Equal1~4_combout ),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_baud|f_del~q ),
	.D(\macro_inst|u_uart[0]|u_regs|uart_en~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_baud|baud16~q ));
defparam \macro_inst|u_uart[0]|u_baud|baud16 .mask = 16'h8A00;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|baud16 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|baud16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Add3~1 (
// Location: FF_X53_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Add3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .mask = 16'hFFAA;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|Add3~0 (
// Location: FF_X53_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|Add3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .mask = 16'h55AA;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1 (
// Location: FF_X53_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|fifo_rden (
// Location: FF_X53_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_IDLE~q ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .mask = 16'hBB00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|Equal1~2 (
alta_slice \macro_inst|u_uart[0]|u_baud|Equal1~2 (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [9]),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [11]),
	.C(\macro_inst|u_uart[0]|u_baud|i_cnt [10]),
	.D(\macro_inst|u_uart[0]|u_baud|i_cnt [12]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|Equal1~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .mask = 16'h0001;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|Equal1~2 .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] (
// Location: LCCOMB_X53_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X53_Y3_GND),
	.SyncReset(SyncReset_X53_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X53_Y3_N0
alta_clkenctrl clken_ctrl_X53_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_fifo|wrreq~0_combout_X53_Y3_SIG_SIG ));
defparam clken_ctrl_X53_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X53_Y3_N0
alta_asyncctrl asyncreset_ctrl_X53_Y3_N0(.Din(), .Dout(AsyncReset_X53_Y3_GND));
defparam asyncreset_ctrl_X53_Y3_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X53_Y3_N1
alta_clkenctrl clken_ctrl_X53_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y3_SIG_VCC ));
defparam clken_ctrl_X53_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y3_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X53_Y3_N1
alta_asyncctrl asyncreset_ctrl_X53_Y3_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y3_SIG ));
defparam asyncreset_ctrl_X53_Y3_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X53_Y3_N0
alta_syncctrl syncreset_ctrl_X53_Y3(.Din(), .Dout(SyncReset_X53_Y3_GND));
defparam syncreset_ctrl_X53_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X53_Y3_N1
alta_syncctrl syncload_ctrl_X53_Y3(.Din(), .Dout(SyncLoad_X53_Y3_VCC));
defparam syncload_ctrl_X53_Y3.SyncCtrlMux = 2'b01;
// Location: FF_X53_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] (
// Location: LCCOMB_X53_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Add1~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_in [3]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_in [2]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_in [0]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(SyncReset_X53_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_in [1]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .mask = 16'h7711;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: FF_X53_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_in [2]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(SyncReset_X53_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y4_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_in [3]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: FF_X53_Y4_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_in [0]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(SyncReset_X53_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y4_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_in [1]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X53_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Add4~2 (
// Location: FF_X53_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_in [0]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(SyncReset_X53_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Add4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_in [1]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .mask = 16'h33CC;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: FF_X53_Y4_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] (
// Location: LCCOMB_X53_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_in [4]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|interrupts[5] (
// Location: LCCOMB_X53_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~29 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts[5] (
	.A(\macro_inst|u_uart[0]|u_regs|interrupts~25_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|interrupts~28_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|interrupts~27_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|interrupts~26_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|interrupts [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~29_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|interrupts [5]));
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[5] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] (
// Location: LCCOMB_X53_Y4_N22
// alta_lcell_comb \macro_inst|uart_rxd[9] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(vcc),
	.D(\SIM_IO[9]~input_o ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [9]),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_in [0]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_read[1] (
// Location: LCCOMB_X53_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_read~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_read[1] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_read [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_read~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_read [1]));
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .mask = 16'h8080;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X53_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Add4~2 (
// Location: FF_X53_Y4_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0]),
	.C(\macro_inst|uart_rxd [10]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(SyncReset_X53_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X53_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Add4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_in [0]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .mask = 16'h33CC;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[0] .SyncLoadMux = 2'b01;
// Location: FF_X53_Y4_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_read[3] (
// Location: LCCOMB_X53_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_read~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_read[3] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_read [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_read~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_read [3]));
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .mask = 16'h8080;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[3] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] (
// Location: LCCOMB_X53_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|rx_read [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[1]|Selector0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[1]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] (
// Location: LCCOMB_X53_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_in[2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_in [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_in[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_in [2]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_in[2] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] (
// Location: LCCOMB_X53_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|rx_read [3]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X53_Y4_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] (
// Location: LCCOMB_X53_Y4_N8
// alta_lcell_comb \macro_inst|uart_rxd[7] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.C(vcc),
	.D(\SIM_IO[7]~input_o ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [7]),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_in [0]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .mask = 16'h0033;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X53_Y4_N0
alta_clkenctrl clken_ctrl_X53_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X53_Y4_SIG_SIG ));
defparam clken_ctrl_X53_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X53_Y4_N0
alta_asyncctrl asyncreset_ctrl_X53_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X53_Y4_SIG ));
defparam asyncreset_ctrl_X53_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X53_Y4_N1
alta_clkenctrl clken_ctrl_X53_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X53_Y4_SIG_VCC ));
defparam clken_ctrl_X53_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X53_Y4_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X53_Y4_N0
alta_syncctrl syncreset_ctrl_X53_Y4(.Din(), .Dout(SyncReset_X53_Y4_GND));
defparam syncreset_ctrl_X53_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X53_Y4_N1
alta_syncctrl syncload_ctrl_X53_Y4(.Din(), .Dout(SyncLoad_X53_Y4_VCC));
defparam syncload_ctrl_X53_Y4.SyncCtrlMux = 2'b01;
// Location: FF_X54_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] (
// Location: LCCOMB_X54_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .mask = 16'hAFAF;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_parity (
// Location: LCCOMB_X54_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_parity (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_parity~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt (
// Location: LCCOMB_X54_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_read[2] (
// Location: LCCOMB_X54_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_read~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_read[2] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_read [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_read~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_read [2]));
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector4~1 (
// Location: FF_X54_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_tx[0]|Selector4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .mask = 16'hAEAA;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|always0~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .mask = 16'h0010;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .mask = 16'h0F00;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector3~1 (
// Location: FF_X54_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_tx[0]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .mask = 16'hEAAA;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .mask = 16'hEFC0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] (
// Location: LCCOMB_X54_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .mask = 16'hFAAF;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] (
// Location: LCCOMB_X54_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout_X54_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .mask = 16'hFAEB;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|Selector2~0 (
// Location: FF_X54_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .mask = 16'h1540;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[0]|Selector5~3_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .mask = 16'h1FDF;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X54_Y1_N0
alta_clkenctrl clken_ctrl_X54_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_data_cnt[1]~1_combout_X54_Y1_SIG_SIG ));
defparam clken_ctrl_X54_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X54_Y1_N0
alta_asyncctrl asyncreset_ctrl_X54_Y1_N0(.Din(), .Dout(AsyncReset_X54_Y1_GND));
defparam asyncreset_ctrl_X54_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X54_Y1_N1
alta_clkenctrl clken_ctrl_X54_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y1_SIG_VCC ));
defparam clken_ctrl_X54_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X54_Y1_N1
alta_asyncctrl asyncreset_ctrl_X54_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y1_SIG ));
defparam asyncreset_ctrl_X54_Y1_N1.AsyncCtrlMux = 2'b10;
// Location: FF_X54_Y2_N0
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[12] (
alta_slice \macro_inst|u_ahb2apb|haddr[12] (
	.A(),
	.B(),
	.C(\rv32.mem_ahb_haddr[12] ),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [12]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [12]));
defparam \macro_inst|u_ahb2apb|haddr[12] .mask = 16'hFFFF;
defparam \macro_inst|u_ahb2apb|haddr[12] .mode = "ripple";
defparam \macro_inst|u_ahb2apb|haddr[12] .modeMux = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[12] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[12] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[12] .SyncLoadMux = 2'b01;
// Location: FF_X54_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|break_error_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|break_error_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[9] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|break_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|break_error_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|break_error_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[2] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y2_N12
// alta_lcell_ff \macro_inst|u_ahb2apb|hwrite (
// Location: LCCOMB_X54_Y2_N12
// alta_lcell_comb \~GND (
alta_slice \macro_inst|u_ahb2apb|hwrite (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwrite ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|hwrite~q ),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(\~GND~combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|hwrite~q ));
defparam \macro_inst|u_ahb2apb|hwrite .mask = 16'h0000;
defparam \macro_inst|u_ahb2apb|hwrite .mode = "logic";
defparam \macro_inst|u_ahb2apb|hwrite .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hwrite .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hwrite .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|hwrite .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|hwrite .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|hwrite .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|hwrite .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|hwrite .SyncLoadMux = 2'b01;
// Location: LCCOMB_X54_Y2_N14
// alta_lcell_comb \macro_inst|u_ahb2apb|always0~0 (
// Location: FF_X54_Y2_N14
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[7] (
alta_slice \macro_inst|u_ahb2apb|haddr[7] (
	.A(\rv32.mem_ahb_htrans[1] ),
	.B(vcc),
	.C(\rv32.mem_ahb_haddr[7] ),
	.D(\macro_inst|u_ahb2apb|hreadyout~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [7]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(\macro_inst|u_ahb2apb|always0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [7]));
defparam \macro_inst|u_ahb2apb|haddr[7] .mask = 16'h00AA;
defparam \macro_inst|u_ahb2apb|haddr[7] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[7] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[7] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X54_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .mask = 16'h0400;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~13 (
// Location: FF_X54_Y2_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_complete~q ),
	.B(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [2]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_idle~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~13_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[2] .SyncLoadMux = 2'b01;
// Location: FF_X54_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[8] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|parity_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|parity_error_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|parity_error_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~10 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~10 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [2]),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [2]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .mask = 16'hF444;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector2~1 (
// Location: FF_X54_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] (
	.A(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [3]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[2] .SyncLoadMux = 2'b01;
// Location: FF_X54_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~11 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~11 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|parity_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|parity_error_ie [2]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|framing_error~q ),
	.D(\macro_inst|u_uart[0]|u_regs|framing_error_ie [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~16 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~16 (
	.A(\macro_inst|u_uart[0]|u_regs|parity_error_ie [3]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|parity_error~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|framing_error~q ),
	.D(\macro_inst|u_uart[0]|u_regs|framing_error_ie [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~16_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~16 .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector0~1 (
// Location: FF_X54_Y2_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] (
	.A(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [3]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(SyncReset_X54_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X54_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector0~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[2] .SyncLoadMux = 2'b01;
// Location: FF_X54_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|framing_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|framing_error_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|framing_error_ie [2]));
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~12 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~12 (
	.A(\macro_inst|u_uart[0]|u_regs|break_error_ie [2]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|break_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [2]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|overrun_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~12 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X54_Y2_N0
alta_clkenctrl clken_ctrl_X54_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|u_ahb2apb|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X54_Y2_SIG_SIG ));
defparam clken_ctrl_X54_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X54_Y2_N0
alta_asyncctrl asyncreset_ctrl_X54_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y2_SIG ));
defparam asyncreset_ctrl_X54_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X54_Y2_N1
alta_clkenctrl clken_ctrl_X54_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~18_combout_X54_Y2_SIG_SIG ));
defparam clken_ctrl_X54_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X54_Y2_N0
alta_syncctrl syncreset_ctrl_X54_Y2(.Din(), .Dout(SyncReset_X54_Y2_GND));
defparam syncreset_ctrl_X54_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X54_Y2_N1
alta_syncctrl syncload_ctrl_X54_Y2(.Din(), .Dout(SyncLoad_X54_Y2_VCC));
defparam syncload_ctrl_X54_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X54_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[0] (
// Location: LCCOMB_X54_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[0]~16 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd[0]~_wirecell_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[0]~16_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[0]~17 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [0]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .mask = 16'h3333;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[5] (
// Location: LCCOMB_X54_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[5]~26 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[5] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [5]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [5]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[4]~25 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[5]~26_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[5]~27 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [5]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .mask = 16'hA505;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[5] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[6] (
// Location: LCCOMB_X54_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[6]~28 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[6] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [6]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [6]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[5]~27 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[6]~28_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[6]~29 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [6]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .mask = 16'h5AAF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[6] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[7] (
// Location: LCCOMB_X54_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[7]~30 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [7]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [7]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[6]~29 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[7]~30_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[7]~31 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [7]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .mask = 16'hC303;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[7] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[8] (
// Location: LCCOMB_X54_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[8]~32 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[8] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [8]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [8]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[7]~31 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[8]~32_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[8]~33 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [8]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[8] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[9] (
// Location: LCCOMB_X54_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[9]~34 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[9] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [9]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [9]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[8]~33 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[9]~34_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[9]~35 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [9]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .mask = 16'hC303;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[9] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[1] (
// Location: LCCOMB_X54_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[1]~18 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [1]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[0]~17 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[1]~18_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[1]~19 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [1]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .mask = 16'hC303;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[10] (
// Location: LCCOMB_X54_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[10]~36 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[10] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [10]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [10]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[9]~35 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[10]~36_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[10]~37 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [10]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[10] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[11] (
// Location: LCCOMB_X54_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[11]~38 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[11] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [11]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [11]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[10]~37 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[11]~38_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[11]~39 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [11]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .mask = 16'hA505;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[11] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[12] (
// Location: LCCOMB_X54_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[12]~40 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[12] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [12]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [12]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[11]~39 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[12]~40_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[12]~41 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [12]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[12] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[13] (
// Location: LCCOMB_X54_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[13]~42 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[13] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [13]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [13]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[12]~41 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[13]~42_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[13]~43 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [13]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .mask = 16'hA505;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[13] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[14] (
// Location: LCCOMB_X54_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[14]~44 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[14] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [14]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [14]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[13]~43 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[14]~44_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[14]~45 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [14]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[14] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[15] (
// Location: LCCOMB_X54_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[15]~46 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[15] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [15]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [15]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[14]~45 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[15]~46_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [15]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .mask = 16'hA5A5;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[15] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[2] (
// Location: LCCOMB_X54_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[2]~20 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [2]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[1]~19 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[2]~20_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[2]~21 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [2]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[3] (
// Location: LCCOMB_X54_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[3]~22 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_baud|i_cnt [3]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [3]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[2]~21 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[3]~22_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[3]~23 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [3]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .mask = 16'hA505;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[3] .SyncLoadMux = 2'b10;
// Location: FF_X54_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|i_cnt[4] (
// Location: LCCOMB_X54_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|i_cnt[4]~24 (
alta_slice \macro_inst|u_uart[0]|u_baud|i_cnt[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|i_cnt [4]),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [4]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|i_cnt[3]~23 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|i_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ),
	.SyncReset(SyncReset_X54_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ),
	.LutOut(\macro_inst|u_uart[0]|u_baud|i_cnt[4]~24_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|i_cnt[4]~25 ),
	.Q(\macro_inst|u_uart[0]|u_baud|i_cnt [4]));
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_baud|i_cnt[4] .SyncLoadMux = 2'b10;

// Location: CLKENCTRL_X54_Y3_N0
alta_clkenctrl clken_ctrl_X54_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y3_SIG_VCC ));
defparam clken_ctrl_X54_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X54_Y3_N0
alta_asyncctrl asyncreset_ctrl_X54_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y3_SIG ));
defparam asyncreset_ctrl_X54_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X54_Y3_N0
alta_syncctrl syncreset_ctrl_X54_Y3(.Din(), .Dout(SyncReset_X54_Y3_GND));
defparam syncreset_ctrl_X54_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X54_Y3_N1
alta_syncctrl syncload_ctrl_X54_Y3(.Din(\macro_inst|u_uart[0]|u_baud|always0~0_combout ), .Dout(\macro_inst|u_uart[0]|u_baud|always0~0_combout__SyncLoad_X54_Y3_SIG ));
defparam syncload_ctrl_X54_Y3.SyncCtrlMux = 2'b10;
// Location: FF_X54_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] (
// Location: LCCOMB_X54_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Add4~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .mask = 16'hFF15;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_write[2] (
// Location: LCCOMB_X54_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|tx_write~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_write[2] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_write [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_write~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_write [2]));
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .mask = 16'h8080;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[2] .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] (
// Location: LCCOMB_X54_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|always3~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .mask = 16'hABAF;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|always3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Add4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Add4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [3]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .mask = 16'h3336;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] (
// Location: LCCOMB_X54_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Add4~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|always3~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout_X54_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X54_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .mask = 16'hFFD1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always3~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|always3~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always3~2 .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] (
// Location: LCCOMB_X54_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Add4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .mask = 16'h1150;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Add4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Add4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .mask = 16'h11EE;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: FF_X54_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_parity (
// Location: LCCOMB_X54_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_parity (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X54_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_parity~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always6~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always6~1 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_in [3]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_in [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_in [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .mask = 16'h080E;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .mask = 16'hFFAA;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .mask = 16'h6000;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always8~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|always8~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X54_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .mask = 16'hCE0A;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X54_Y4_N0
alta_clkenctrl clken_ctrl_X54_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_data_cnt[1]~3_combout_X54_Y4_SIG_SIG ));
defparam clken_ctrl_X54_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X54_Y4_N0
alta_asyncctrl asyncreset_ctrl_X54_Y4_N0(.Din(), .Dout(AsyncReset_X54_Y4_GND));
defparam asyncreset_ctrl_X54_Y4_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X54_Y4_N1
alta_clkenctrl clken_ctrl_X54_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X54_Y4_SIG_VCC ));
defparam clken_ctrl_X54_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X54_Y4_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X54_Y4_N1
alta_asyncctrl asyncreset_ctrl_X54_Y4_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X54_Y4_SIG ));
defparam asyncreset_ctrl_X54_Y4_N1.AsyncCtrlMux = 2'b10;
// Location: FF_X56_Y10_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] (
// Location: LCCOMB_X56_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] (
// Location: LCCOMB_X56_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] (
// Location: LCCOMB_X56_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [6]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|fifo_rden (
// Location: FF_X56_Y10_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(SyncReset_X56_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .mask = 16'hCC44;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y10_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] (
// Location: LCCOMB_X56_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [2]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] (
// Location: LCCOMB_X56_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [7]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] (
// Location: LCCOMB_X56_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|tx_write [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(SyncReset_X56_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y10_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] (
// Location: LCCOMB_X56_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][4]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] (
// Location: LCCOMB_X56_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y10_GND),
	.SyncReset(SyncReset_X56_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .mask = 16'hFF88;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y10_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] (
// Location: LCCOMB_X56_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][7]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y10_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] (
// Location: LCCOMB_X56_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|fifo[1][3]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [4]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y10_N0
alta_clkenctrl clken_ctrl_X56_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg[7]~1_combout_X56_Y10_SIG_SIG ));
defparam clken_ctrl_X56_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y10_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y10_N0
alta_asyncctrl asyncreset_ctrl_X56_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y10_SIG ));
defparam asyncreset_ctrl_X56_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y10_N1
alta_clkenctrl clken_ctrl_X56_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout_X56_Y10_SIG_SIG ));
defparam clken_ctrl_X56_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y10_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y10_N1
alta_asyncctrl asyncreset_ctrl_X56_Y10_N1(.Din(), .Dout(AsyncReset_X56_Y10_GND));
defparam asyncreset_ctrl_X56_Y10_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y10_N0
alta_syncctrl syncreset_ctrl_X56_Y10(.Din(), .Dout(SyncReset_X56_Y10_GND));
defparam syncreset_ctrl_X56_Y10.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y10_N1
alta_syncctrl syncload_ctrl_X56_Y10(.Din(), .Dout(SyncLoad_X56_Y10_VCC));
defparam syncload_ctrl_X56_Y10.SyncCtrlMux = 2'b01;
// Location: FF_X56_Y11_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] (
// Location: LCCOMB_X56_Y11_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y11_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] (
// Location: LCCOMB_X56_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y11_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux1~3 (
// Location: FF_X56_Y11_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [1]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux1~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .mask = 16'hCCB8;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y11_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] (
// Location: LCCOMB_X56_Y11_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y11_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux6~3 (
// Location: FF_X56_Y11_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [6]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux6~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .mask = 16'hEE50;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y11_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] (
// Location: LCCOMB_X56_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux4~3 (
// Location: FF_X56_Y11_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [4]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .mask = 16'hEE50;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux5~3 (
// Location: FF_X56_Y11_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [5]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .mask = 16'hCCB8;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y11_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] (
// Location: LCCOMB_X56_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux2~3 (
// Location: FF_X56_Y11_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][2]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [2]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux2~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .mask = 16'hCCB8;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y11_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux0~3 (
// Location: FF_X56_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][0]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [0]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .mask = 16'hEE50;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y11_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] (
// Location: LCCOMB_X56_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux3~3 (
// Location: FF_X56_Y11_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][3]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [3]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux3~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .mask = 16'hEE50;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y11_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] (
// Location: LCCOMB_X56_Y11_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [5]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y11_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux7~3 (
// Location: FF_X56_Y11_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][7]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y11_GND),
	.SyncReset(SyncReset_X56_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux7~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .mask = 16'hEE50;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X56_Y11_N0
alta_clkenctrl clken_ctrl_X56_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ));
defparam clken_ctrl_X56_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y11_N0
alta_asyncctrl asyncreset_ctrl_X56_Y11_N0(.Din(), .Dout(AsyncReset_X56_Y11_GND));
defparam asyncreset_ctrl_X56_Y11_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X56_Y11_N1
alta_clkenctrl clken_ctrl_X56_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout_X56_Y11_SIG_SIG ));
defparam clken_ctrl_X56_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y11_N0
alta_syncctrl syncreset_ctrl_X56_Y11(.Din(), .Dout(SyncReset_X56_Y11_GND));
defparam syncreset_ctrl_X56_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y11_N1
alta_syncctrl syncload_ctrl_X56_Y11(.Din(), .Dout(SyncLoad_X56_Y11_VCC));
defparam syncload_ctrl_X56_Y11.SyncCtrlMux = 2'b01;
// Location: FF_X56_Y12_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] (
// Location: LCCOMB_X56_Y12_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [1]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0]~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] (
// Location: LCCOMB_X56_Y12_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] (
// Location: LCCOMB_X56_Y12_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [5]),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] (
// Location: LCCOMB_X56_Y12_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [6]),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][5]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] (
// Location: LCCOMB_X56_Y12_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][3]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [4]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] (
// Location: LCCOMB_X56_Y12_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [2]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][1]~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] (
// Location: LCCOMB_X56_Y12_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y12_GND),
	.SyncReset(SyncReset_X56_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y12_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .mask = 16'hFF88;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y12_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] (
// Location: LCCOMB_X56_Y12_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [3]),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][2]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] (
// Location: LCCOMB_X56_Y12_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|fifo[1][7]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y12_N0
alta_clkenctrl clken_ctrl_X56_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg[7]~1_combout_X56_Y12_SIG_SIG ));
defparam clken_ctrl_X56_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y12_N0
alta_asyncctrl asyncreset_ctrl_X56_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y12_SIG ));
defparam asyncreset_ctrl_X56_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y12_N1
alta_clkenctrl clken_ctrl_X56_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_fifo|wrreq~0_combout_X56_Y12_SIG_SIG ));
defparam clken_ctrl_X56_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y12_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y12_N1
alta_asyncctrl asyncreset_ctrl_X56_Y12_N1(.Din(), .Dout(AsyncReset_X56_Y12_GND));
defparam asyncreset_ctrl_X56_Y12_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y12_N0
alta_syncctrl syncreset_ctrl_X56_Y12(.Din(), .Dout(SyncReset_X56_Y12_GND));
defparam syncreset_ctrl_X56_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y12_N1
alta_syncctrl syncload_ctrl_X56_Y12(.Din(), .Dout(SyncLoad_X56_Y12_VCC));
defparam syncload_ctrl_X56_Y12.SyncCtrlMux = 2'b01;
// Location: FF_X56_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|break_error (
// Location: LCCOMB_X56_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|break_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|break_error (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|always11~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|break_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .mask = 16'hFFA0;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|break_error .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] (
// Location: LCCOMB_X56_Y1_N10
// alta_lcell_comb \macro_inst|uart_rxd[5] (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] (
	.A(vcc),
	.B(vcc),
	.C(\SIM_IO[5]~input_o ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [5]),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_in [0]));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .mask = 16'hFDFF;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[2]~14 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en (
// Location: LCCOMB_X56_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_fifo|counter ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_idle_en~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .mask = 16'hDCDC;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|always11~2 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|always11~2 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|always11~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|always11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|overrun_error (
// Location: LCCOMB_X56_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|overrun_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|overrun_error (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|overrun_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|overrun_error .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req (
// Location: LCCOMB_X56_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req (
	.A(\macro_inst|u_uart[0]|u_regs|tx_dma_en [0]),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.C(vcc),
	.D(\rv32.ext_dma_DMACCLR[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_dma_req~q ));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .mask = 16'h00A2;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_dma_req .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|framing_error (
// Location: LCCOMB_X56_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|framing_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|framing_error (
	.A(\macro_inst|u_uart[0]|u_rx[2]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|framing_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .mask = 16'hF222;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] (
// Location: LCCOMB_X56_Y1_N22
// alta_lcell_comb \~VCC (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[3]|rx_in [0]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(SyncReset_X56_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y1_VCC),
	.LutOut(\~VCC~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_in [1]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] (
// Location: LCCOMB_X56_Y1_N24
// alta_lcell_comb sys_resetn(
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] (
	.A(\rv32.resetn_out ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_in [2]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(SyncReset_X56_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y1_VCC),
	.LutOut(\sys_resetn~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_in [3]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .mask = 16'h5555;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] (
// Location: LCCOMB_X56_Y1_N26
// alta_lcell_comb \macro_inst|uart_rxd[2] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(\SIM_IO[2]~input_o ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [2]),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_in [0]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .mask = 16'h0505;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] (
// Location: LCCOMB_X56_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_in [4]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] (
// Location: LCCOMB_X56_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_in [1]),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(SyncReset_X56_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_stop~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_in [2]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .mask = 16'h0055;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|Add1~0 (
// Location: FF_X56_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] (
	.A(\macro_inst|u_uart[0]|u_rx[2]|rx_in [2]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_in [4]),
	.C(\macro_inst|u_uart[0]|u_rx[2]|rx_in [0]),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(SyncReset_X56_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|rx_in [1]));
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .mask = 16'h44DD;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[2]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_complete (
// Location: LCCOMB_X56_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_complete~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_complete (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_complete~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .mask = 16'h3310;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] (
// Location: LCCOMB_X56_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.B(vcc),
	.C(\macro_inst|uart_rxd [3]),
	.D(\macro_inst|u_uart[0]|u_regs|tx_write [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ),
	.SyncReset(SyncReset_X56_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_in [0]));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .mask = 16'h5500;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_in[0] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X56_Y1_N0
alta_clkenctrl clken_ctrl_X56_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y1_SIG_VCC ));
defparam clken_ctrl_X56_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y1_N0
alta_asyncctrl asyncreset_ctrl_X56_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y1_SIG ));
defparam asyncreset_ctrl_X56_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y1_N1
alta_clkenctrl clken_ctrl_X56_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X56_Y1_SIG_SIG ));
defparam clken_ctrl_X56_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y1_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y1_N0
alta_syncctrl syncreset_ctrl_X56_Y1(.Din(), .Dout(SyncReset_X56_Y1_GND));
defparam syncreset_ctrl_X56_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y1_N1
alta_syncctrl syncload_ctrl_X56_Y1(.Din(), .Dout(SyncLoad_X56_Y1_VCC));
defparam syncload_ctrl_X56_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X56_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~9 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~9 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector7~18_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector7~8_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .mask = 16'hB888;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~25 (
// Location: FF_X56_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [5]),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~25_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .mask = 16'hBA30;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~5 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|rx_idle~q ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector8~3_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector8~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~8 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~8 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|Selector7~7_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .mask = 16'hFFF0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~4 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_reg [4]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[4]|rx_idle~q ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .mask = 16'hCCE2;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector9~3 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|overrun_error~q ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|overrun_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .mask = 16'hF4A4;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~11 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~11 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_complete~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|Selector7~10_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .mask = 16'hAFF0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~14 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~14 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector7~10_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|Selector7~13_combout ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .mask = 16'hFAFA;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~2 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[0]|u_rx[0]|rx_idle~q ),
	.D(\macro_inst|u_uart[0]|u_rx[1]|rx_idle~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .mask = 16'hDC98;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~16 (
// Location: FF_X56_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[5] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector7~17_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector7~15_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~9_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~16_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [5]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .mask = 16'hC840;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~15 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~15 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector7~18_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector7~14_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~11_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .mask = 16'hCA0A;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~28 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~28 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_complete~q ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_idle~q ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [5]),
	.D(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~28_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~10 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~10 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_reg [5]),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_complete~q ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~13 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~13 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_complete~q ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_complete~q ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .mask = 16'hDDA0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~5 (
// Location: FF_X56_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [5]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector7~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X56_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y2_SIG ),
	.SyncReset(SyncReset_X56_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .mask = 16'hBBCC;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~3 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_idle~q ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector8~2_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[2]|rx_idle~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .mask = 16'hDAD0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y2_N0
alta_clkenctrl clken_ctrl_X56_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X56_Y2_SIG_SIG ));
defparam clken_ctrl_X56_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y2_N0
alta_asyncctrl asyncreset_ctrl_X56_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y2_SIG ));
defparam asyncreset_ctrl_X56_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y2_N1
alta_clkenctrl clken_ctrl_X56_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X56_Y2_SIG_SIG ));
defparam clken_ctrl_X56_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y2_N0
alta_syncctrl syncreset_ctrl_X56_Y2(.Din(), .Dout(SyncReset_X56_Y2_GND));
defparam syncreset_ctrl_X56_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y2_N1
alta_syncctrl syncload_ctrl_X56_Y2(.Din(), .Dout(SyncLoad_X56_Y2_VCC));
defparam syncload_ctrl_X56_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X56_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_idle (
// Location: LCCOMB_X56_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_idle~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_idle (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[4]|always8~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_idle~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .mask = 16'hFCCC;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_idle .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] (
// Location: LCCOMB_X56_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [5]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][4]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N12
// alta_lcell_ff \macro_inst|u_ahb2apb|apbState.apbSetup (
// Location: LCCOMB_X56_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1 (
alta_slice \macro_inst|u_ahb2apb|apbState.apbSetup (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_bit~q ),
	.C(\macro_inst|u_ahb2apb|psel~1_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|apbState.apbSetup~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(SyncReset_X56_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|apbState.apbSetup~q ));
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .mask = 16'hFF88;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .mode = "logic";
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|apbState.apbSetup .SyncLoadMux = 2'b01;
// Location: FF_X56_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] (
// Location: LCCOMB_X56_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][7]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .mask = 16'hF5A0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N16
// alta_lcell_comb \macro_inst|u_ahb2apb|always2~0 (
// Location: FF_X56_Y3_N16
// alta_lcell_ff \macro_inst|u_ahb2apb|pvalid (
alta_slice \macro_inst|u_ahb2apb|pvalid (
	.A(\macro_inst|u_ahb2apb|hreadyout~q ),
	.B(\macro_inst|u_ahb2apb|psel~q ),
	.C(\macro_inst|u_ahb2apb|pdone~q ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|pvalid~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|pvalid~q ));
defparam \macro_inst|u_ahb2apb|pvalid .mask = 16'h0202;
defparam \macro_inst|u_ahb2apb|pvalid .mode = "logic";
defparam \macro_inst|u_ahb2apb|pvalid .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pvalid .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pvalid .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pvalid .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|pvalid .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|pvalid .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|pvalid .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|pvalid .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_write[0] (
// Location: LCCOMB_X56_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|tx_write~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_write[0] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_write [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_write~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_write [0]));
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_idle (
// Location: LCCOMB_X56_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_idle~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_idle (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always8~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_idle~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .mask = 16'hFF50;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] (
// Location: LCCOMB_X56_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [4]),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][3]~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N22
// alta_lcell_comb \macro_inst|u_ahb2apb|Selector0~0 (
// Location: FF_X56_Y3_N22
// alta_lcell_ff \macro_inst|u_ahb2apb|apbState.apbIdle (
alta_slice \macro_inst|u_ahb2apb|apbState.apbIdle (
	.A(\macro_inst|u_ahb2apb|apbState.apbAccess~q ),
	.B(\macro_inst|u_ahb2apb|pvalid~q ),
	.C(vcc),
	.D(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|apbState.apbIdle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|apbState.apbIdle~q ));
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .mask = 16'hDCFC;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .mode = "logic";
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|apbState.apbIdle .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] (
// Location: LCCOMB_X56_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][0]~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .mask = 16'hAACC;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N26
// alta_lcell_comb \macro_inst|u_ahb2apb|Selector2~0 (
// Location: FF_X56_Y3_N26
// alta_lcell_ff \macro_inst|u_ahb2apb|apbState.apbAccess (
alta_slice \macro_inst|u_ahb2apb|apbState.apbAccess (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|apbState.apbSetup~q ),
	.C(vcc),
	.D(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|apbState.apbAccess~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|apbState.apbAccess~q ));
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .mask = 16'hCCFC;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .mode = "logic";
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|apbState.apbAccess .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] (
// Location: LCCOMB_X56_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [3]),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][2]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y3_N30
// alta_lcell_comb \macro_inst|u_ahb2apb|psel~1 (
alta_slice \macro_inst|u_ahb2apb|psel~1 (
	.A(\macro_inst|u_ahb2apb|apbState.apbAccess~q ),
	.B(\macro_inst|u_ahb2apb|pvalid~q ),
	.C(\macro_inst|u_ahb2apb|apbState.apbIdle~q ),
	.D(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|psel~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_ahb2apb|psel~1 .mask = 16'h8C0C;
defparam \macro_inst|u_ahb2apb|psel~1 .mode = "logic";
defparam \macro_inst|u_ahb2apb|psel~1 .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|psel~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|psel~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|psel~1 .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|psel~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|psel~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|psel~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|psel~1 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] (
// Location: LCCOMB_X56_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [7]),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][6]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] (
// Location: LCCOMB_X56_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][5]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .mask = 16'hFA50;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] (
// Location: LCCOMB_X56_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|fifo[1][1]~q ),
	.B(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .mask = 16'hAACC;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y3_N0
alta_clkenctrl clken_ctrl_X56_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y3_SIG_VCC ));
defparam clken_ctrl_X56_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y3_N0
alta_asyncctrl asyncreset_ctrl_X56_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y3_SIG ));
defparam asyncreset_ctrl_X56_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y3_N1
alta_clkenctrl clken_ctrl_X56_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[0]|tx_shift_reg[2]~1_combout_X56_Y3_SIG_SIG ));
defparam clken_ctrl_X56_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y3_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y3_N0
alta_syncctrl syncreset_ctrl_X56_Y3(.Din(), .Dout(SyncReset_X56_Y3_GND));
defparam syncreset_ctrl_X56_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y3_N1
alta_syncctrl syncload_ctrl_X56_Y3(.Din(), .Dout(SyncLoad_X56_Y3_VCC));
defparam syncload_ctrl_X56_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X56_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_sample~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2 (
// Location: FF_X56_Y4_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_dma_en [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_dma_en [2]));
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [0]),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y4_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_dma_en [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_dma_en [2]));
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .mask = 16'hFFC0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .mask = 16'h0500;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~0 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_regs|rx_dma_en [1]),
	.C(\macro_inst|u_uart[1]|u_regs|rx_dma_en [0]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .mask = 16'hAAD8;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N22
// alta_lcell_comb PLL_ENABLE(
alta_slice PLL_ENABLE(
	.A(vcc),
	.B(vcc),
	.C(\rv32.sys_ctrl_pllEnable ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_ENABLE~combout ),
	.Cout(),
	.Q());
defparam PLL_ENABLE.mask = 16'h0F0F;
defparam PLL_ENABLE.mode = "logic";
defparam PLL_ENABLE.modeMux = 1'b0;
defparam PLL_ENABLE.FeedbackMux = 1'b0;
defparam PLL_ENABLE.ShiftMux = 1'b0;
defparam PLL_ENABLE.BypassEn = 1'b0;
defparam PLL_ENABLE.CarryEnb = 1'b1;
defparam PLL_ENABLE.AsyncResetMux = 2'bxx;
defparam PLL_ENABLE.SyncResetMux = 2'bxx;
defparam PLL_ENABLE.SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~11 (
// Location: FF_X56_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] (
	.A(\macro_inst|u_uart[1]|u_regs|tx_dma_en [2]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_dma_en [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_dma_en [3]));
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Add4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Add4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .mask = 16'h5A5A;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Add4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Add4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .mask = 16'h01FE;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Add4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Add4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0]),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .mask = 16'h3636;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~1 (
// Location: FF_X56_Y4_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|rx_dma_en [2]),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector12~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_dma_en [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6_combout_X56_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ),
	.SyncReset(SyncReset_X56_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_dma_en [3]));
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X56_Y4_N0
alta_clkenctrl clken_ctrl_X56_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[2]~2_combout_X56_Y4_SIG_SIG ));
defparam clken_ctrl_X56_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y4_N0
alta_asyncctrl asyncreset_ctrl_X56_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y4_SIG ));
defparam asyncreset_ctrl_X56_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y4_N1
alta_clkenctrl clken_ctrl_X56_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6_combout_X56_Y4_SIG_SIG ));
defparam clken_ctrl_X56_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y4_N0
alta_syncctrl syncreset_ctrl_X56_Y4(.Din(), .Dout(SyncReset_X56_Y4_GND));
defparam syncreset_ctrl_X56_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y4_N1
alta_syncctrl syncload_ctrl_X56_Y4(.Din(), .Dout(SyncLoad_X56_Y4_VCC));
defparam syncload_ctrl_X56_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X56_Y5_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_sample~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector1~0 (
// Location: FF_X56_Y5_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_rx[1]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .mask = 16'h00DC;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y5_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt (
// Location: LCCOMB_X56_Y5_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .mask = 16'h0033;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector0~0 (
// Location: FF_X56_Y5_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .mask = 16'h00F5;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux8~0 (
// Location: FF_X56_Y5_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|status_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|status_reg[4] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|Mux10~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|status_reg[2]~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|status_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux8~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|status_reg [4]));
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .mask = 16'h05AF;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Add3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Add3~0 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .mask = 16'h55AA;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y5_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|status_reg[2] (
// Location: LCCOMB_X56_Y5_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|status_reg[2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_regs|status_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|Mux10~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|status_reg[2]~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|status_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y5_GND),
	.SyncReset(SyncReset_X56_Y5_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X56_Y5_INV ),
	.LutOut(\macro_inst|u_uart[1]|u_regs|status_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|status_reg [2]));
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[2] .SyncLoadMux = 2'b11;
// Location: LCCOMB_X56_Y5_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector0~0 (
// Location: FF_X56_Y5_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE (
	.A(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .mask = 16'h00F5;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux7~5 (
// Location: FF_X56_Y5_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_reg[7] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_reg[7] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_regs|Mux7~2_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux7~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux7~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_reg [7]));
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .mask = 16'h7520;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_reg[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .mask = 16'h1230;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector5~4 (
// Location: FF_X56_Y5_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|uart_txd (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|uart_txd (
	.A(\macro_inst|u_uart[1]|u_tx[5]|Selector5~2_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|uart_txd~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .mask = 16'h1100;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux10~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux10~0 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux10~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .mask = 16'hF053;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .mask = 16'h0088;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y5_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux10~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux10~1 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux10~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux10~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .mask = 16'h8F83;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux10~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y5_N0
alta_clkenctrl clken_ctrl_X56_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y5_SIG_VCC ));
defparam clken_ctrl_X56_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y5_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y5_N0
alta_asyncctrl asyncreset_ctrl_X56_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y5_SIG ));
defparam asyncreset_ctrl_X56_Y5_N0.AsyncCtrlMux = 2'b10;

// Location: ASYNCCTRL_X56_Y5_N1
alta_asyncctrl asyncreset_ctrl_X56_Y5_N1(.Din(), .Dout(AsyncReset_X56_Y5_GND));
defparam asyncreset_ctrl_X56_Y5_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y5_N0
alta_syncctrl syncreset_ctrl_X56_Y5(.Din(), .Dout(SyncReset_X56_Y5_GND));
defparam syncreset_ctrl_X56_Y5.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y5_N1
alta_syncctrl syncload_ctrl_X56_Y5(.Din(\macro_inst|u_ahb2apb|paddr [10]), .Dout(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X56_Y5_INV ));
defparam syncload_ctrl_X56_Y5.SyncCtrlMux = 2'b11;
// Location: LCCOMB_X56_Y6_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Add4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Add4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [3]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .mask = 16'h3336;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y6_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] (
// Location: LCCOMB_X56_Y6_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Add4~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|always3~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout_X56_Y6_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .mask = 16'hFFA3;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Selector2~4_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .mask = 16'h0E00;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y6_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] (
// Location: LCCOMB_X56_Y6_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y6_SIG ),
	.SyncReset(SyncReset_X56_Y6_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout__SyncLoad_X56_Y6_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y6_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] (
// Location: LCCOMB_X56_Y6_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y6_SIG ),
	.SyncReset(SyncReset_X56_Y6_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout__SyncLoad_X56_Y6_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y6_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] (
// Location: LCCOMB_X56_Y6_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y6_SIG ),
	.SyncReset(SyncReset_X56_Y6_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout__SyncLoad_X56_Y6_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X56_Y6_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector4~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .mask = 16'hAA00;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y6_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] (
// Location: LCCOMB_X56_Y6_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\~GND~combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y6_SIG ),
	.SyncReset(SyncReset_X56_Y6_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout__SyncLoad_X56_Y6_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: FF_X56_Y6_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] (
// Location: LCCOMB_X56_Y6_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Add4~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout_X56_Y6_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .mask = 16'hFF07;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always3~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|always3~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .mask = 16'hAA00;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|always3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [3]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|always3~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector2~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .mask = 16'hAAA8;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Add4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Add4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .mask = 16'h0F5A;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y6_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector2~6 (
// Location: FF_X56_Y6_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_rx[1]|Selector2~5_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Selector2~3_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .mask = 16'h00EA;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y6_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] (
// Location: LCCOMB_X56_Y6_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Add4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .mask = 16'h0072;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y6_N0
alta_clkenctrl clken_ctrl_X56_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout_X56_Y6_SIG_SIG ));
defparam clken_ctrl_X56_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y6_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y6_N0
alta_asyncctrl asyncreset_ctrl_X56_Y6_N0(.Din(), .Dout(AsyncReset_X56_Y6_GND));
defparam asyncreset_ctrl_X56_Y6_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X56_Y6_N1
alta_clkenctrl clken_ctrl_X56_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y6_SIG_VCC ));
defparam clken_ctrl_X56_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y6_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y6_N1
alta_asyncctrl asyncreset_ctrl_X56_Y6_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y6_SIG ));
defparam asyncreset_ctrl_X56_Y6_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X56_Y6_N0
alta_syncctrl syncreset_ctrl_X56_Y6(.Din(), .Dout(SyncReset_X56_Y6_GND));
defparam syncreset_ctrl_X56_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y6_N1
alta_syncctrl syncload_ctrl_X56_Y6(.Din(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout ), .Dout(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout__SyncLoad_X56_Y6_SIG ));
defparam syncload_ctrl_X56_Y6.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X56_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always8~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always8~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always8~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_write[0] (
// Location: LCCOMB_X56_Y7_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|tx_write~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_write[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_write [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_write~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_write [0]));
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector5~4 (
// Location: FF_X56_Y7_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|uart_txd (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|Selector5~2_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|uart_txd~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .mask = 16'h0300;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|uart_txd .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_parity (
// Location: LCCOMB_X56_Y7_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_parity (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_parity~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] (
// Location: LCCOMB_X56_Y7_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_regs|tx_write [0]),
	.B(\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .mask = 16'h3A0A;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector5~4 (
// Location: FF_X56_Y7_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|uart_txd (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|Selector5~2_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|uart_txd~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .mask = 16'h0300;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] (
// Location: LCCOMB_X56_Y7_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_parity (
// Location: LCCOMB_X56_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_parity (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_parity~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_parity~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .mask = 16'h335A;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en (
// Location: LCCOMB_X56_Y7_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_idle_en~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .mask = 16'hFF70;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always2~1 (
// Location: FF_X56_Y7_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_bit (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_bit (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt (
// Location: LCCOMB_X56_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .mask = 16'hFAF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y7_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en (
// Location: LCCOMB_X56_Y7_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_idle_en~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .mask = 16'hBAFA;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .mask = 16'h0078;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y7_N0
alta_clkenctrl clken_ctrl_X56_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y7_SIG_VCC ));
defparam clken_ctrl_X56_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y7_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y7_N0
alta_asyncctrl asyncreset_ctrl_X56_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y7_SIG ));
defparam asyncreset_ctrl_X56_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y7_N1
alta_clkenctrl clken_ctrl_X56_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_fifo|wrreq~0_combout_X56_Y7_SIG_SIG ));
defparam clken_ctrl_X56_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y7_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y7_N1
alta_asyncctrl asyncreset_ctrl_X56_Y7_N1(.Din(), .Dout(AsyncReset_X56_Y7_GND));
defparam asyncreset_ctrl_X56_Y7_N1.AsyncCtrlMux = 2'b00;
// Location: FF_X56_Y8_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START (
// Location: LCCOMB_X56_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .mask = 16'hFF40;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|always6~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|always6~0 (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|always6~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y8_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] (
// Location: LCCOMB_X56_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout_X56_Y8_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .mask = 16'hFCED;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y8_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] (
// Location: LCCOMB_X56_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout__SyncReset_X56_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X56_Y8_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] (
// Location: LCCOMB_X56_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout__SyncReset_X56_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X56_Y8_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] (
// Location: LCCOMB_X56_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout__SyncReset_X56_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X56_Y8_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] (
// Location: LCCOMB_X56_Y8_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [0]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout_X56_Y8_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .mask = 16'hFFA5;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y8_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] (
// Location: LCCOMB_X56_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout__SyncReset_X56_Y8_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X56_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .mask = 16'h3300;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|Selector5~3_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .mask = 16'h57F7;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y8_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] (
// Location: LCCOMB_X56_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout_X56_Y8_SIG_SIG ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y8_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP (
// Location: LCCOMB_X56_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|always6~1 (
// Location: FF_X56_Y8_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_bit (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_bit (
	.A(\macro_inst|u_uart[1]|u_tx[1]|always6~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_baud_cnt [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .mask = 16'hAA00;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_stop (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_stop .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y8_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_parity (
// Location: LCCOMB_X56_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_parity (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X56_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_parity~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|always0~0 (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .mask = 16'h0100;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|always0~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X56_Y8_N0
alta_clkenctrl clken_ctrl_X56_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X56_Y8_SIG_VCC ));
defparam clken_ctrl_X56_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y8_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X56_Y8_N0
alta_asyncctrl asyncreset_ctrl_X56_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y8_SIG ));
defparam asyncreset_ctrl_X56_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y8_N1
alta_clkenctrl clken_ctrl_X56_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[1]|tx_data_cnt[0]~1_combout_X56_Y8_SIG_SIG ));
defparam clken_ctrl_X56_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y8_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y8_N1
alta_asyncctrl asyncreset_ctrl_X56_Y8_N1(.Din(), .Dout(AsyncReset_X56_Y8_GND));
defparam asyncreset_ctrl_X56_Y8_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y8_N0
alta_syncctrl syncreset_ctrl_X56_Y8(.Din(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout ), .Dout(\macro_inst|u_uart[1]|u_tx[1]|tx_stop~combout__SyncReset_X56_Y8_SIG ));
defparam syncreset_ctrl_X56_Y8.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X56_Y8_N1
alta_syncctrl syncload_ctrl_X56_Y8(.Din(), .Dout(SyncLoad_X56_Y8_GND));
defparam syncload_ctrl_X56_Y8.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X56_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always11~1 (
// Location: FF_X56_Y9_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [3]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [2]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y9_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] (
// Location: LCCOMB_X56_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .mask = 16'h00CC;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[1] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] (
// Location: LCCOMB_X56_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_in [4]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_parity~0 (
// Location: FF_X56_Y9_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_parity~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|always4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [0]),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X56_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] (
// Location: LCCOMB_X56_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|fifo_rden (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .mask = 16'hDD00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y9_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] (
// Location: LCCOMB_X56_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector5~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [4]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .mask = 16'h2222;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .mask = 16'hF8CC;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Add1~0 (
// Location: FF_X56_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_in [4]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .mask = 16'h0AAF;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|comb~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|comb~1 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .mask = 16'h4400;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|comb~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X56_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always6~1 (
// Location: FF_X56_Y9_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_in [3]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_in [1]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_in [2]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .mask = 16'h2032;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[2] .SyncLoadMux = 2'b01;
// Location: FF_X56_Y9_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] (
// Location: LCCOMB_X56_Y9_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .mask = 16'hEECC;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always10~1 (
// Location: FF_X56_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_in [2]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always10~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_in [3]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .mask = 16'h93C9;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X56_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always11~0 (
// Location: FF_X56_Y9_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [7]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [5]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ),
	.SyncReset(SyncReset_X56_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X56_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_shift_reg[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X56_Y9_N0
alta_clkenctrl clken_ctrl_X56_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[1]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|always4~2_combout_X56_Y9_SIG_SIG ));
defparam clken_ctrl_X56_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X56_Y9_N0
alta_asyncctrl asyncreset_ctrl_X56_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X56_Y9_SIG ));
defparam asyncreset_ctrl_X56_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X56_Y9_N1
alta_clkenctrl clken_ctrl_X56_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X56_Y9_SIG_SIG ));
defparam clken_ctrl_X56_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X56_Y9_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X56_Y9_N0
alta_syncctrl syncreset_ctrl_X56_Y9(.Din(), .Dout(SyncReset_X56_Y9_GND));
defparam syncreset_ctrl_X56_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X56_Y9_N1
alta_syncctrl syncload_ctrl_X56_Y9(.Din(), .Dout(SyncLoad_X56_Y9_VCC));
defparam syncload_ctrl_X56_Y9.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X57_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .mask = 16'h006A;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] (
// Location: LCCOMB_X57_Y10_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(SyncReset_X57_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .mask = 16'h00CC;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|always0~0 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .mask = 16'h0004;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector3~1 (
// Location: FF_X57_Y10_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_tx[2]|always0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|Selector3~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .mask = 16'hF8F0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [0]),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector2~0 (
// Location: FF_X57_Y10_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_tx[2]|always0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector4~0 (
// Location: FF_X57_Y10_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_bit (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_bit (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|always6~1_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(SyncReset_X57_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .mask = 16'hEFC0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_bit .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y10_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|Selector5~3_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .mask = 16'h1FDF;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector4~1 (
// Location: FF_X57_Y10_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_tx[2]|always0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .mask = 16'hF2F0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START (
// Location: LCCOMB_X57_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_tx[2]|fifo_rden~combout ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .mask = 16'hBAAA;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y10_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always11~0 (
// Location: FF_X57_Y10_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [6]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [5]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(SyncReset_X57_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|comb~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|comb~1 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .mask = 16'h0A00;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|comb~1 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt (
// Location: LCCOMB_X57_Y10_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .mask = 16'hFFC0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] (
// Location: LCCOMB_X57_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_regs|tx_write [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(SyncReset_X57_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .mask = 16'h3300;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_parity~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_shift_reg [0]),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .mask = 16'hECA0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y10_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] (
// Location: LCCOMB_X57_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ),
	.SyncReset(SyncReset_X57_Y10_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y10_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .mask = 16'hEECC;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X57_Y10_N0
alta_clkenctrl clken_ctrl_X57_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[3]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y10_SIG_SIG ));
defparam clken_ctrl_X57_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y10_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y10_N0
alta_asyncctrl asyncreset_ctrl_X57_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y10_SIG ));
defparam asyncreset_ctrl_X57_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y10_N1
alta_clkenctrl clken_ctrl_X57_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y10_SIG_VCC ));
defparam clken_ctrl_X57_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y10_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y10_N1
alta_asyncctrl asyncreset_ctrl_X57_Y10_N1(.Din(), .Dout(AsyncReset_X57_Y10_GND));
defparam asyncreset_ctrl_X57_Y10_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y10_N0
alta_syncctrl syncreset_ctrl_X57_Y10(.Din(), .Dout(SyncReset_X57_Y10_GND));
defparam syncreset_ctrl_X57_Y10.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y10_N1
alta_syncctrl syncload_ctrl_X57_Y10(.Din(), .Dout(SyncLoad_X57_Y10_VCC));
defparam syncload_ctrl_X57_Y10.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y11_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] (
// Location: LCCOMB_X57_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] (
// Location: LCCOMB_X57_Y11_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [6]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] (
// Location: LCCOMB_X57_Y11_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] (
// Location: LCCOMB_X57_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] (
// Location: LCCOMB_X57_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always11~0 (
// Location: FF_X57_Y11_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [5]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] (
// Location: LCCOMB_X57_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] (
// Location: LCCOMB_X57_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [6]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] (
// Location: LCCOMB_X57_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always11~1 (
// Location: FF_X57_Y11_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [0]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [2]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y11_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] (
// Location: LCCOMB_X57_Y11_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y11_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_shift_reg [0]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y11_GND),
	.SyncReset(SyncReset_X57_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X57_Y11_N0
alta_clkenctrl clken_ctrl_X57_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[2]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|always4~2_combout_X57_Y11_SIG_SIG ));
defparam clken_ctrl_X57_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y11_N0
alta_asyncctrl asyncreset_ctrl_X57_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y11_SIG ));
defparam asyncreset_ctrl_X57_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y11_N1
alta_clkenctrl clken_ctrl_X57_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_fifo|wrreq~0_combout_X57_Y11_SIG_SIG ));
defparam clken_ctrl_X57_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y11_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y11_N1
alta_asyncctrl asyncreset_ctrl_X57_Y11_N1(.Din(), .Dout(AsyncReset_X57_Y11_GND));
defparam asyncreset_ctrl_X57_Y11_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y11_N0
alta_syncctrl syncreset_ctrl_X57_Y11(.Din(), .Dout(SyncReset_X57_Y11_GND));
defparam syncreset_ctrl_X57_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y11_N1
alta_syncctrl syncload_ctrl_X57_Y11(.Din(), .Dout(SyncLoad_X57_Y11_VCC));
defparam syncload_ctrl_X57_Y11.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y12_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] (
// Location: LCCOMB_X57_Y12_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] (
// Location: LCCOMB_X57_Y12_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [3]),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] (
// Location: LCCOMB_X57_Y12_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(SyncReset_X57_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y12_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .mask = 16'hFF88;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] (
// Location: LCCOMB_X57_Y12_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] (
// Location: LCCOMB_X57_Y12_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][6]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] (
// Location: LCCOMB_X57_Y12_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] (
// Location: LCCOMB_X57_Y12_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][1]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] (
// Location: LCCOMB_X57_Y12_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [0]),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][7]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] (
// Location: LCCOMB_X57_Y12_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|fifo[1][5]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [6]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y12_N0
alta_clkenctrl clken_ctrl_X57_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_shift_reg[5]~1_combout_X57_Y12_SIG_SIG ));
defparam clken_ctrl_X57_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y12_N0
alta_asyncctrl asyncreset_ctrl_X57_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y12_SIG ));
defparam asyncreset_ctrl_X57_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y12_N1
alta_clkenctrl clken_ctrl_X57_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout_X57_Y12_SIG_SIG ));
defparam clken_ctrl_X57_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y12_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y12_N1
alta_asyncctrl asyncreset_ctrl_X57_Y12_N1(.Din(), .Dout(AsyncReset_X57_Y12_GND));
defparam asyncreset_ctrl_X57_Y12_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y12_N0
alta_syncctrl syncreset_ctrl_X57_Y12(.Din(), .Dout(SyncReset_X57_Y12_GND));
defparam syncreset_ctrl_X57_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y12_N1
alta_syncctrl syncload_ctrl_X57_Y12(.Din(), .Dout(SyncLoad_X57_Y12_VCC));
defparam syncload_ctrl_X57_Y12.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START (
// Location: LCCOMB_X57_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .mask = 16'hAAEA;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] (
// Location: LCCOMB_X57_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~q ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_dma_en [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3_combout_X57_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(SyncReset_X57_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_dma_en [4]));
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .mask = 16'h2200;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] (
// Location: LCCOMB_X57_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|fifo_rden (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_dma_en [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3_combout_X57_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(SyncReset_X57_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|fifo_rden~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_dma_en [4]));
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .mask = 16'hCC44;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_complete (
// Location: LCCOMB_X57_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_complete~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_complete (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_complete~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .mask = 16'h3310;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_complete (
// Location: LCCOMB_X57_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_complete~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_complete (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_complete~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .mask = 16'h5444;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[2]|parity_error (
// Location: LCCOMB_X57_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[2]|parity_error~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[2]|parity_error (
	.A(\macro_inst|u_uart[0]|u_rx[2]|parity_error~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[2]|rx_sample~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[2]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[2]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[2]|parity_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[2]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] (
// Location: LCCOMB_X57_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_regs|tx_write [5]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .mask = 16'h0CAC;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt (
// Location: LCCOMB_X57_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en (
// Location: LCCOMB_X57_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_idle_en~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .mask = 16'hDCDC;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_read[4] (
// Location: LCCOMB_X57_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_read~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_read[4] (
	.A(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_read [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_read~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_read [4]));
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[4] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|overrun_error (
// Location: LCCOMB_X57_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|overrun_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|overrun_error (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|overrun_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .mask = 16'hDC50;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|overrun_error .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_read[5] (
// Location: LCCOMB_X57_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_read~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_read[5] (
	.A(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_read [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_read~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_read [5]));
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_read[5] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_write[5] (
// Location: LCCOMB_X57_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|tx_write~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_write[5] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_write [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_write~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_write [5]));
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[5] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] (
// Location: LCCOMB_X57_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|rx_read [5]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~q ),
	.C(\macro_inst|u_uart[0]|u_tx[5]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .mask = 16'h1444;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y1_N0
alta_clkenctrl clken_ctrl_X57_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y1_SIG_VCC ));
defparam clken_ctrl_X57_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y1_N0
alta_asyncctrl asyncreset_ctrl_X57_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y1_SIG ));
defparam asyncreset_ctrl_X57_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y1_N1
alta_clkenctrl clken_ctrl_X57_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[4]~3_combout_X57_Y1_SIG_SIG ));
defparam clken_ctrl_X57_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y1_N1
alta_asyncctrl asyncreset_ctrl_X57_Y1_N1(.Din(), .Dout(AsyncReset_X57_Y1_GND));
defparam asyncreset_ctrl_X57_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y1_N0
alta_syncctrl syncreset_ctrl_X57_Y1(.Din(), .Dout(SyncReset_X57_Y1_GND));
defparam syncreset_ctrl_X57_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y1_N1
alta_syncctrl syncload_ctrl_X57_Y1(.Din(), .Dout(SyncLoad_X57_Y1_VCC));
defparam syncload_ctrl_X57_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X57_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~0 (
// Location: FF_X57_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_regs|rx_dma_en [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_dma_en [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y2_SIG ),
	.SyncReset(SyncReset_X57_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_dma_en [0]));
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .mask = 16'hDC98;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~2 (
	.A(\macro_inst|u_uart[0]|u_rx[1]|framing_error~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_rx[0]|framing_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .mask = 16'hCBC8;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .mask = 16'hEFC0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|fifo_rden (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|fifo_rden (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .mask = 16'hF030;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux10~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux10~0 (
	.A(\macro_inst|u_uart[0]|u_tx[0]|tx_fifo|counter ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux10~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .mask = 16'hC1CD;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|comb~1 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_stop_cnt~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .mask = 16'h5000;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|comb~1 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y2_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] (
// Location: LCCOMB_X57_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_dma_en [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y2_SIG ),
	.SyncReset(SyncReset_X57_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_dma_en [1]));
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[1] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_dma_en [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_dma_en[0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_dma_en [0]));
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector11~2 (
	.A(\macro_inst|u_uart[0]|u_regs|tx_dma_en [1]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_regs|tx_dma_en [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .mask = 16'hCBC8;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector9~4 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|overrun_error~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|overrun_error~q ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector9~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .mask = 16'hCFA0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~3 (
	.A(\macro_inst|u_uart[0]|u_rx[2]|framing_error~q ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|framing_error~q ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector12~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .mask = 16'hCFA0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0 (
// Location: FF_X57_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_dma_en [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1_combout_X57_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y2_SIG ),
	.SyncReset(SyncReset_X57_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_dma_en [1]));
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~9 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~9 (
	.A(\macro_inst|u_uart[0]|u_regs|status_reg [1]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .mask = 16'hCEC2;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags[3]~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[3]~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux10~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux10~1 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux10~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .mask = 16'hA0DD;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux10~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~10 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~10 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector8~8_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector8~9_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .mask = 16'hEC2C;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~10 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y2_N0
alta_clkenctrl clken_ctrl_X57_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[0]~0_combout_X57_Y2_SIG_SIG ));
defparam clken_ctrl_X57_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y2_N0
alta_asyncctrl asyncreset_ctrl_X57_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y2_SIG ));
defparam asyncreset_ctrl_X57_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y2_N1
alta_clkenctrl clken_ctrl_X57_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[1]~1_combout_X57_Y2_SIG_SIG ));
defparam clken_ctrl_X57_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X57_Y2_N0
alta_syncctrl syncreset_ctrl_X57_Y2(.Din(), .Dout(SyncReset_X57_Y2_GND));
defparam syncreset_ctrl_X57_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y2_N1
alta_syncctrl syncload_ctrl_X57_Y2(.Din(), .Dout(SyncLoad_X57_Y2_VCC));
defparam syncload_ctrl_X57_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|overrun_error (
// Location: LCCOMB_X57_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|overrun_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|overrun_error (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|overrun_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .mask = 16'hEAC0;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|overrun_error .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|break_error_ie[4] (
// Location: LCCOMB_X57_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|status_reg[2]~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|break_error_ie[4] (
	.A(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|break_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|status_reg[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|break_error_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .mask = 16'hBB88;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~21 (
// Location: FF_X57_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] (
	.A(\macro_inst|u_uart[0]|u_regs|framing_error_ie [4]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|parity_error~q ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|framing_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|parity_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~21_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|parity_error_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .mask = 16'hEAC0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[11] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_idle_ie[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~20 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~20 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [4]),
	.C(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [4]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~20_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~20 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|interrupts[4] (
// Location: LCCOMB_X57_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~24 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts[4] (
	.A(\macro_inst|u_uart[0]|u_regs|interrupts~21_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|interrupts~20_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|interrupts~22_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|interrupts~23_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|interrupts [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~24_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|interrupts [4]));
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts[4] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] (
// Location: LCCOMB_X57_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .mask = 16'h22AA;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|parity_error (
// Location: LCCOMB_X57_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|parity_error~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|parity_error (
	.A(\macro_inst|u_uart[0]|u_rx[4]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|parity_error~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|parity_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|parity_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux8~0 (
// Location: FF_X57_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|status_reg[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|status_reg[4] (
	.A(\macro_inst|u_uart[0]|u_regs|status_reg[2]~1_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|Mux10~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|status_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux8~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|status_reg [4]));
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .mask = 16'h4477;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~23 (
// Location: FF_X57_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_complete~q ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [4]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_idle~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~23_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .mask = 16'hECA0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[4] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_complete (
// Location: LCCOMB_X57_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_complete~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_complete (
	.A(\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_complete~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .mask = 16'h3222;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~11 (
// Location: FF_X57_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] (
	.A(\macro_inst|u_uart[0]|u_regs|status_reg [4]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|framing_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|framing_error_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .mask = 16'hE2AA;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always10~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|always10~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always10~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|always2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_sample~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always10~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always10~2 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|framing_error (
// Location: LCCOMB_X57_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|framing_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|framing_error (
	.A(\macro_inst|u_uart[0]|u_rx[4]|Add1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|framing_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .mask = 16'hD5C0;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|framing_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~4 (
// Location: FF_X57_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] (
	.A(\macro_inst|u_uart[0]|u_regs|status_reg [2]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ),
	.SyncReset(SyncReset_X57_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_not_full_ie [4]));
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .mask = 16'hFC22;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_not_full_ie[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X57_Y3_N0
alta_clkenctrl clken_ctrl_X57_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y3_SIG_VCC ));
defparam clken_ctrl_X57_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y3_N0
alta_asyncctrl asyncreset_ctrl_X57_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y3_SIG ));
defparam asyncreset_ctrl_X57_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y3_N1
alta_clkenctrl clken_ctrl_X57_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout_X57_Y3_SIG_SIG ));
defparam clken_ctrl_X57_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y3_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y3_N1
alta_asyncctrl asyncreset_ctrl_X57_Y3_N1(.Din(), .Dout(AsyncReset_X57_Y3_GND));
defparam asyncreset_ctrl_X57_Y3_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y3_N0
alta_syncctrl syncreset_ctrl_X57_Y3(.Din(), .Dout(SyncReset_X57_Y3_GND));
defparam syncreset_ctrl_X57_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y3_N1
alta_syncctrl syncload_ctrl_X57_Y3(.Din(), .Dout(SyncLoad_X57_Y3_VCC));
defparam syncload_ctrl_X57_Y3.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] (
// Location: LCCOMB_X57_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout__SyncLoad_X57_Y4_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X57_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] (
// Location: LCCOMB_X57_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always3~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .mask = 16'hABAF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] (
// Location: LCCOMB_X57_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Add4~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .mask = 16'hF1F3;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .mask = 16'hFFCC;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector2~4_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .mask = 16'h3020;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] (
// Location: LCCOMB_X57_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout__SyncLoad_X57_Y4_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X57_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always3~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always3~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector2~6 (
// Location: FF_X57_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector2~3_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|Selector2~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector2~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .mask = 16'h0F08;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always2~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always2~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always2~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] (
// Location: LCCOMB_X57_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Add4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .mask = 16'h1150;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] (
// Location: LCCOMB_X57_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Add4~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|always3~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout_X57_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .mask = 16'hFBAB;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] (
// Location: LCCOMB_X57_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout__SyncLoad_X57_Y4_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X57_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] (
// Location: LCCOMB_X57_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\~GND~combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(SyncReset_X57_Y4_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout__SyncLoad_X57_Y4_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X57_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector1~0 (
// Location: FF_X57_Y4_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Selector2~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector2~4_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .mask = 16'h5510;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_START .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y4_N0
alta_clkenctrl clken_ctrl_X57_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[2]|rx_data_cnt[2]~3_combout_X57_Y4_SIG_SIG ));
defparam clken_ctrl_X57_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y4_N0
alta_asyncctrl asyncreset_ctrl_X57_Y4_N0(.Din(), .Dout(AsyncReset_X57_Y4_GND));
defparam asyncreset_ctrl_X57_Y4_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X57_Y4_N1
alta_clkenctrl clken_ctrl_X57_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y4_SIG_VCC ));
defparam clken_ctrl_X57_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y4_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y4_N1
alta_asyncctrl asyncreset_ctrl_X57_Y4_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y4_SIG ));
defparam asyncreset_ctrl_X57_Y4_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X57_Y4_N0
alta_syncctrl syncreset_ctrl_X57_Y4(.Din(), .Dout(SyncReset_X57_Y4_GND));
defparam syncreset_ctrl_X57_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y4_N1
alta_syncctrl syncload_ctrl_X57_Y4(.Din(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout ), .Dout(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout__SyncLoad_X57_Y4_SIG ));
defparam syncload_ctrl_X57_Y4.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X57_Y5_N10
// alta_lcell_comb PLL_LOCK(
alta_slice PLL_LOCK(
	.A(vcc),
	.B(\pll_inst|auto_generated|pll_lock_sync~q ),
	.C(\auto_generated_inst.hbo_13_1797ab7b230f061a_bp ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\PLL_LOCK~combout ),
	.Cout(),
	.Q());
defparam PLL_LOCK.mask = 16'hC0C0;
defparam PLL_LOCK.mode = "logic";
defparam PLL_LOCK.modeMux = 1'b0;
defparam PLL_LOCK.FeedbackMux = 1'b0;
defparam PLL_LOCK.ShiftMux = 1'b0;
defparam PLL_LOCK.BypassEn = 1'b0;
defparam PLL_LOCK.CarryEnb = 1'b1;
defparam PLL_LOCK.AsyncResetMux = 2'bxx;
defparam PLL_LOCK.SyncResetMux = 2'bxx;
defparam PLL_LOCK.SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .mask = 16'h0040;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y5_N14
// alta_lcell_ff \pll_inst|auto_generated|pll_lock_sync (
// Location: LCCOMB_X57_Y5_N14
// alta_lcell_comb \pll_inst|auto_generated|pll_lock_sync~feeder (
alta_slice \pll_inst|auto_generated|pll_lock_sync (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\pll_inst|auto_generated|pll_lock_sync~q ),
	.Clk(\auto_generated_inst.hbo_13_1797ab7b230f061a_bp_X57_Y5_SIG_VCC ),
	.AsyncReset(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X57_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
	.Cout(),
	.Q(\pll_inst|auto_generated|pll_lock_sync~q ));
defparam \pll_inst|auto_generated|pll_lock_sync .mask = 16'hFFFF;
defparam \pll_inst|auto_generated|pll_lock_sync .mode = "logic";
defparam \pll_inst|auto_generated|pll_lock_sync .modeMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .FeedbackMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .ShiftMux = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .BypassEn = 1'b0;
defparam \pll_inst|auto_generated|pll_lock_sync .CarryEnb = 1'b1;
defparam \pll_inst|auto_generated|pll_lock_sync .AsyncResetMux = 2'b10;
defparam \pll_inst|auto_generated|pll_lock_sync .SyncResetMux = 2'bxx;
defparam \pll_inst|auto_generated|pll_lock_sync .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always11~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always11~2 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always11~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|always11~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always11~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|Selector4~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .mask = 16'hD9D1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y5_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector6~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector6~2 (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_uart[0]|u_regs|rx_reg [6]),
	.C(\macro_inst|u_uart[0]|u_regs|Selector6~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|status_reg [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector6~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .mask = 16'h40E0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y5_N0
alta_clkenctrl clken_ctrl_X57_Y5_N0(.ClkIn(\auto_generated_inst.hbo_13_1797ab7b230f061a_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_13_1797ab7b230f061a_bp_X57_Y5_SIG_VCC ));
defparam clken_ctrl_X57_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y5_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y5_N0
alta_asyncctrl asyncreset_ctrl_X57_Y5_N0(.Din(\PLL_ENABLE~clkctrl_outclk ), .Dout(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X57_Y5_SIG ));
defparam asyncreset_ctrl_X57_Y5_N0.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X57_Y6_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector4~3 (
// Location: FF_X57_Y6_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Selector4~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y6_SIG ),
	.SyncReset(SyncReset_X57_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .mask = 16'h0088;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y6_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] (
// Location: LCCOMB_X57_Y6_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|always3~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout_X57_Y6_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .mask = 16'hFF07;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y6_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always11~1 (
// Location: FF_X57_Y6_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [1]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [3]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y6_SIG ),
	.SyncReset(SyncReset_X57_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y6_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3 (
// Location: FF_X57_Y6_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y6_SIG ),
	.SyncReset(SyncReset_X57_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .mask = 16'hFFAA;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[1] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X57_Y6_N0
alta_clkenctrl clken_ctrl_X57_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[3]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X57_Y6_SIG_SIG ));
defparam clken_ctrl_X57_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y6_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y6_N0
alta_asyncctrl asyncreset_ctrl_X57_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y6_SIG ));
defparam asyncreset_ctrl_X57_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y6_N1
alta_clkenctrl clken_ctrl_X57_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[1]|rx_data_cnt[0]~3_combout_X57_Y6_SIG_SIG ));
defparam clken_ctrl_X57_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y6_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y6_N1
alta_asyncctrl asyncreset_ctrl_X57_Y6_N1(.Din(), .Dout(AsyncReset_X57_Y6_GND));
defparam asyncreset_ctrl_X57_Y6_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y6_N0
alta_syncctrl syncreset_ctrl_X57_Y6(.Din(), .Dout(SyncReset_X57_Y6_GND));
defparam syncreset_ctrl_X57_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y6_N1
alta_syncctrl syncload_ctrl_X57_Y6(.Din(), .Dout(SyncLoad_X57_Y6_VCC));
defparam syncload_ctrl_X57_Y6.SyncCtrlMux = 2'b01;
// Location: FF_X57_Y7_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] (
// Location: LCCOMB_X57_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .mask = 16'h5400;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .mask = 16'h0400;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_read[2] (
// Location: LCCOMB_X57_Y7_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_read~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_read[2] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_read [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_read~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_read [2]));
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~13 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~13 (
	.A(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [2]),
	.B(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [2]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_idle~q ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_complete~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~13 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] (
// Location: LCCOMB_X57_Y7_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_read [3]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .mask = 16'h5F50;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector2~6 (
// Location: FF_X57_Y7_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_rx[3]|Selector2~5_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[3]|rx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|Selector2~3_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .mask = 16'h00EA;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|interrupts[1] (
// Location: LCCOMB_X57_Y7_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~9 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts[1] (
	.A(\macro_inst|u_uart[1]|u_regs|interrupts~6_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|interrupts~5_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|interrupts~7_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|interrupts~8_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|interrupts [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|interrupts [1]));
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] (
// Location: LCCOMB_X57_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|rx_read [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] (
// Location: LCCOMB_X57_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|rx_read [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_read[3] (
// Location: LCCOMB_X57_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_read~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_read[3] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_read [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_read~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_read [3]));
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .mask = 16'h8080;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y7_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~5 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [1]),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .mask = 16'h8F88;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~5 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_idle (
// Location: LCCOMB_X57_Y7_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_idle~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_idle (
	.A(\macro_inst|u_uart[1]|u_rx[2]|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_idle~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .mask = 16'hBAFA;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_idle .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_read[0] (
// Location: LCCOMB_X57_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_read~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_read[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_read [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_read~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_read [0]));
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[0] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y7_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|status_reg[0] (
// Location: LCCOMB_X57_Y7_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|status_reg[0]~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|status_reg[0] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_regs|Mux12~1_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|status_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y7_GND),
	.SyncReset(SyncReset_X57_Y7_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X57_Y7_INV ),
	.LutOut(\macro_inst|u_uart[1]|u_regs|status_reg[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|status_reg [0]));
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .mask = 16'hDD88;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[0] .SyncLoadMux = 2'b11;
// Location: LCCOMB_X57_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[3]|Selector0~0 (
// Location: FF_X57_Y7_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_rx[3]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[3]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[3]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .mask = 16'h00F3;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[3]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y7_N0
alta_clkenctrl clken_ctrl_X57_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[0]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y7_SIG_SIG ));
defparam clken_ctrl_X57_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y7_N0
alta_asyncctrl asyncreset_ctrl_X57_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y7_SIG ));
defparam asyncreset_ctrl_X57_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y7_N1
alta_clkenctrl clken_ctrl_X57_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y7_SIG_VCC ));
defparam clken_ctrl_X57_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y7_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y7_N1
alta_asyncctrl asyncreset_ctrl_X57_Y7_N1(.Din(), .Dout(AsyncReset_X57_Y7_GND));
defparam asyncreset_ctrl_X57_Y7_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y7_N0
alta_syncctrl syncreset_ctrl_X57_Y7(.Din(), .Dout(SyncReset_X57_Y7_GND));
defparam syncreset_ctrl_X57_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y7_N1
alta_syncctrl syncload_ctrl_X57_Y7(.Din(\macro_inst|u_ahb2apb|paddr [10]), .Dout(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X57_Y7_INV ));
defparam syncload_ctrl_X57_Y7.SyncCtrlMux = 2'b11;
// Location: FF_X57_Y8_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] (
// Location: LCCOMB_X57_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_in [4]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always11~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|always11~2 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|always11~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|always11~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y8_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] (
// Location: LCCOMB_X57_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_sample~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_sample~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_in [3]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Add1~0 (
// Location: FF_X57_Y8_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_in [2]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_in [4]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .mask = 16'h44DD;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always2~0 (
// Location: FF_X57_Y8_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [3]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y8_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] (
// Location: LCCOMB_X57_Y8_N2
// alta_lcell_comb \macro_inst|uart_rxd[6] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(vcc),
	.D(\SIM_IO[6]~input_o ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [6]),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_in [0]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|always4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y8_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] (
// Location: LCCOMB_X57_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_in[2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_in [1]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_in[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_in [2]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .mask = 16'h0400;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector4~2 (
// Location: FF_X57_Y8_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector4~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .mask = 16'h2200;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y8_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always11~1 (
// Location: FF_X57_Y8_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [2]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [0]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always11~0 (
// Location: FF_X57_Y8_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [4]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: FF_X57_Y8_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] (
// Location: LCCOMB_X57_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_regs|tx_write [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .mask = 16'h3300;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X57_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector2~2 (
// Location: FF_X57_Y8_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_sample~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ),
	.SyncReset(SyncReset_X57_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_shift_reg[7] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X57_Y8_N0
alta_clkenctrl clken_ctrl_X57_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X57_Y8_SIG_SIG ));
defparam clken_ctrl_X57_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y8_N0
alta_asyncctrl asyncreset_ctrl_X57_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y8_SIG ));
defparam asyncreset_ctrl_X57_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y8_N1
alta_clkenctrl clken_ctrl_X57_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[0]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[0]|always4~2_combout_X57_Y8_SIG_SIG ));
defparam clken_ctrl_X57_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y8_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X57_Y8_N0
alta_syncctrl syncreset_ctrl_X57_Y8(.Din(), .Dout(SyncReset_X57_Y8_GND));
defparam syncreset_ctrl_X57_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y8_N1
alta_syncctrl syncload_ctrl_X57_Y8(.Din(), .Dout(SyncLoad_X57_Y8_VCC));
defparam syncload_ctrl_X57_Y8.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X57_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector4~1 (
// Location: FF_X57_Y9_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .mask = 16'hFF40;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector3~1 (
// Location: FF_X57_Y9_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|Selector3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .mask = 16'hFF80;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] (
// Location: LCCOMB_X57_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout_X57_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .mask = 16'hFFE1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] (
// Location: LCCOMB_X57_Y9_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout__SyncReset_X57_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X57_Y9_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] (
// Location: LCCOMB_X57_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout__SyncReset_X57_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X57_Y9_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] (
// Location: LCCOMB_X57_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout__SyncReset_X57_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X57_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector2~0 (
// Location: FF_X57_Y9_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] (
// Location: LCCOMB_X57_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout__SyncReset_X57_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X57_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X57_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|always6~1 (
// Location: FF_X57_Y9_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_bit (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|always6~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .mask = 16'hCC00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|always6~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|always6~0 (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|always6~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_parity (
// Location: LCCOMB_X57_Y9_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_parity (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_parity~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START (
// Location: LCCOMB_X57_Y9_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .mask = 16'hFF40;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|always0~0 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .mask = 16'h0010;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X57_Y9_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_tx[0]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[0]|Selector5~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .mask = 16'h1DFF;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] (
// Location: LCCOMB_X57_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout_X57_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .mask = 16'hFFC3;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X57_Y9_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] (
// Location: LCCOMB_X57_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout_X57_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X57_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X57_Y9_N0
alta_clkenctrl clken_ctrl_X57_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X57_Y9_SIG_VCC ));
defparam clken_ctrl_X57_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y9_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X57_Y9_N0
alta_asyncctrl asyncreset_ctrl_X57_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X57_Y9_SIG ));
defparam asyncreset_ctrl_X57_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X57_Y9_N1
alta_clkenctrl clken_ctrl_X57_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[0]|tx_data_cnt[2]~1_combout_X57_Y9_SIG_SIG ));
defparam clken_ctrl_X57_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X57_Y9_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X57_Y9_N1
alta_asyncctrl asyncreset_ctrl_X57_Y9_N1(.Din(), .Dout(AsyncReset_X57_Y9_GND));
defparam asyncreset_ctrl_X57_Y9_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X57_Y9_N0
alta_syncctrl syncreset_ctrl_X57_Y9(.Din(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout ), .Dout(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout__SyncReset_X57_Y9_SIG ));
defparam syncreset_ctrl_X57_Y9.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X57_Y9_N1
alta_syncctrl syncload_ctrl_X57_Y9(.Din(), .Dout(SyncLoad_X57_Y9_GND));
defparam syncload_ctrl_X57_Y9.SyncCtrlMux = 2'b00;
// Location: FF_X58_Y10_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] (
// Location: LCCOMB_X58_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [0]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout_X58_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .mask = 16'hFFA5;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Add4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Add4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .mask = 16'h0F1E;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector5~4 (
// Location: FF_X58_Y10_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|uart_txd (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|Selector5~2_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|uart_txd~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .mask = 16'h0300;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .mask = 16'h3300;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Add4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Add4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .mask = 16'h5566;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y10_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] (
// Location: LCCOMB_X58_Y10_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout_X58_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .mask = 16'hFFE1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Add4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Add4~2 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .mask = 16'h33CC;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|always6~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|always6~1 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[2]|always6~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y10_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] (
// Location: LCCOMB_X58_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] (
// Location: LCCOMB_X58_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] (
// Location: LCCOMB_X58_Y10_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] (
// Location: LCCOMB_X58_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout__SyncReset_X58_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X58_Y10_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] (
// Location: LCCOMB_X58_Y10_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout_X58_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y10_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_parity (
// Location: LCCOMB_X58_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_parity (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_parity~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_stop (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_stop .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|always6~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|always6~0 (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.C(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|always6~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y10_N0
alta_clkenctrl clken_ctrl_X58_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y10_SIG_VCC ));
defparam clken_ctrl_X58_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y10_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y10_N0
alta_asyncctrl asyncreset_ctrl_X58_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y10_SIG ));
defparam asyncreset_ctrl_X58_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y10_N1
alta_clkenctrl clken_ctrl_X58_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[2]|tx_data_cnt[2]~1_combout_X58_Y10_SIG_SIG ));
defparam clken_ctrl_X58_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y10_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y10_N1
alta_asyncctrl asyncreset_ctrl_X58_Y10_N1(.Din(), .Dout(AsyncReset_X58_Y10_GND));
defparam asyncreset_ctrl_X58_Y10_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y10_N0
alta_syncctrl syncreset_ctrl_X58_Y10(.Din(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout ), .Dout(\macro_inst|u_uart[1]|u_tx[2]|tx_stop~combout__SyncReset_X58_Y10_SIG ));
defparam syncreset_ctrl_X58_Y10.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y10_N1
alta_syncctrl syncload_ctrl_X58_Y10(.Din(), .Dout(SyncLoad_X58_Y10_GND));
defparam syncload_ctrl_X58_Y10.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X58_Y11_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux2~4 (
// Location: FF_X58_Y11_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][2]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_regs|Mux2~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux2~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux3~4 (
// Location: FF_X58_Y11_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][3]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_regs|Mux3~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux3~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux0~5 (
// Location: FF_X58_Y11_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux0~4_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux0~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [0]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .mask = 16'h7430;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux6~4 (
// Location: FF_X58_Y11_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][6]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_regs|Mux6~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux6~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux4~4 (
// Location: FF_X58_Y11_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][4]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_regs|Mux4~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux4~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux6~5 (
// Location: FF_X58_Y11_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[6] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[6] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux6~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux6~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux6~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [6]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .mask = 16'h7340;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux5~5 (
// Location: FF_X58_Y11_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[5] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|Mux5~2_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Mux5~4_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux5~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [5]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .mask = 16'h44F0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux0~4 (
// Location: FF_X58_Y11_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][0]~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [0]),
	.D(\macro_inst|u_uart[1]|u_regs|Mux0~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux0~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux1~5 (
// Location: FF_X58_Y11_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[1] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux1~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux1~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux1~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [1]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .mask = 16'h7340;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux4~5 (
// Location: FF_X58_Y11_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[4] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|Mux4~4_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Mux4~2_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux4~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [4]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .mask = 16'h50CC;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux7~4 (
// Location: FF_X58_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[1]|u_regs|Mux7~3_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][7]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux7~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .mask = 16'hE6A2;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux7~5 (
// Location: FF_X58_Y11_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[7] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[7] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux7~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux7~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux7~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [7]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .mask = 16'h7340;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux3~5 (
// Location: FF_X58_Y11_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux3~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux3~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux3~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [3]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .mask = 16'h7340;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y11_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux1~4 (
// Location: FF_X58_Y11_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[1]|u_regs|Mux1~3_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][1]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux1~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .mask = 16'hE6A2;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y11_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux5~4 (
// Location: FF_X58_Y11_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[1]|u_regs|Mux5~3_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|fifo[1][5]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y11_GND),
	.SyncReset(SyncReset_X58_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .mask = 16'hE6A2;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X58_Y11_N0
alta_clkenctrl clken_ctrl_X58_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout_X58_Y11_SIG_SIG ));
defparam clken_ctrl_X58_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y11_N0
alta_asyncctrl asyncreset_ctrl_X58_Y11_N0(.Din(), .Dout(AsyncReset_X58_Y11_GND));
defparam asyncreset_ctrl_X58_Y11_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X58_Y11_N1
alta_clkenctrl clken_ctrl_X58_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y11_SIG_VCC ));
defparam clken_ctrl_X58_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y11_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X58_Y11_N0
alta_syncctrl syncreset_ctrl_X58_Y11(.Din(), .Dout(SyncReset_X58_Y11_GND));
defparam syncreset_ctrl_X58_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y11_N1
alta_syncctrl syncload_ctrl_X58_Y11(.Din(), .Dout(SyncLoad_X58_Y11_VCC));
defparam syncload_ctrl_X58_Y11.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X58_Y12_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|Selector0~4_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .mask = 16'h0A08;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector2~2 (
// Location: FF_X58_Y12_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Selector2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector2~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .mask = 16'h00EC;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] (
// Location: LCCOMB_X58_Y12_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(SyncReset_X58_Y12_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout__SyncLoad_X58_Y12_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X58_Y12_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] (
// Location: LCCOMB_X58_Y12_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(SyncReset_X58_Y12_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout__SyncLoad_X58_Y12_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X58_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] (
// Location: LCCOMB_X58_Y12_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(SyncReset_X58_Y12_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout__SyncLoad_X58_Y12_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X58_Y12_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y12_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] (
// Location: LCCOMB_X58_Y12_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [3]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(SyncReset_X58_Y12_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout__SyncLoad_X58_Y12_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .mask = 16'h5A5A;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X58_Y12_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .mask = 16'h0033;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always2~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always2~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [3]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector1~0 (
// Location: FF_X58_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector0~4_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .mask = 16'h00BA;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector4~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .mask = 16'hA0E0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector0~3 (
// Location: FF_X58_Y12_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .mask = 16'h00F5;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y12_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always2~1 (
// Location: FF_X58_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_bit (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_bit .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y12_N0
alta_clkenctrl clken_ctrl_X58_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y12_SIG_VCC ));
defparam clken_ctrl_X58_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y12_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y12_N0
alta_asyncctrl asyncreset_ctrl_X58_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y12_SIG ));
defparam asyncreset_ctrl_X58_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y12_N0
alta_syncctrl syncreset_ctrl_X58_Y12(.Din(), .Dout(SyncReset_X58_Y12_GND));
defparam syncreset_ctrl_X58_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y12_N1
alta_syncctrl syncload_ctrl_X58_Y12(.Din(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout ), .Dout(\macro_inst|u_uart[1]|u_rx[4]|always6~1_combout__SyncLoad_X58_Y12_SIG ));
defparam syncload_ctrl_X58_Y12.SyncCtrlMux = 2'b10;
// Location: FF_X58_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] (
// Location: LCCOMB_X58_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout_X58_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] (
// Location: LCCOMB_X58_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout_X58_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .mask = 16'hFCCF;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[5]|Selector0~0 (
// Location: FF_X58_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE (
	.A(\macro_inst|u_uart[0]|u_tx[5]|comb~1_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[5]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[5]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .mask = 16'hFF50;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector2~0 (
// Location: FF_X58_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|comb~1 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .mask = 16'h0088;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|comb~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector3~1 (
// Location: FF_X58_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_tx[4]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .mask = 16'hEAAA;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START (
// Location: LCCOMB_X58_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .mask = 16'hBAAA;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt (
// Location: LCCOMB_X58_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .mask = 16'hEAEA;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|status_reg[0] (
// Location: LCCOMB_X58_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|status_reg[0]~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|status_reg[0] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_tx[5]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_regs|Mux12~1_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|status_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y1_GND),
	.SyncReset(SyncReset_X58_Y1_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X58_Y1_INV ),
	.LutOut(\macro_inst|u_uart[0]|u_regs|status_reg[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|status_reg [0]));
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[0] .SyncLoadMux = 2'b11;
// Location: LCCOMB_X58_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector4~1 (
// Location: FF_X58_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_tx[4]|Selector4~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .mask = 16'hAEAA;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .mask = 16'hECE4;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .mask = 16'hFCCC;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .mask = 16'h006C;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] (
// Location: LCCOMB_X58_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout_X58_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X58_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .mask = 16'hFCED;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|always0~0 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .mask = 16'h0002;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Mux12~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|Mux12~1 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_regs|Mux12~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Mux12~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Mux12~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y1_N0
alta_clkenctrl clken_ctrl_X58_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_data_cnt[0]~1_combout_X58_Y1_SIG_SIG ));
defparam clken_ctrl_X58_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y1_N0
alta_asyncctrl asyncreset_ctrl_X58_Y1_N0(.Din(), .Dout(AsyncReset_X58_Y1_GND));
defparam asyncreset_ctrl_X58_Y1_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X58_Y1_N1
alta_clkenctrl clken_ctrl_X58_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y1_SIG_VCC ));
defparam clken_ctrl_X58_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y1_N1
alta_asyncctrl asyncreset_ctrl_X58_Y1_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y1_SIG ));
defparam asyncreset_ctrl_X58_Y1_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y1_N0
alta_syncctrl syncreset_ctrl_X58_Y1(.Din(), .Dout(SyncReset_X58_Y1_GND));
defparam syncreset_ctrl_X58_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y1_N1
alta_syncctrl syncload_ctrl_X58_Y1(.Din(\macro_inst|u_ahb2apb|paddr [10]), .Dout(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X58_Y1_INV ));
defparam syncload_ctrl_X58_Y1.SyncCtrlMux = 2'b11;
// Location: LCCOMB_X58_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~7 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector11~7 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|parity_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector11~6_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .mask = 16'hBCB0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16 (
// Location: FF_X58_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[2] (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y2_SIG ),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [2]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .mask = 16'hAA00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector10~0 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_rx[0]|break_error~q ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|break_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .mask = 16'hF4A4;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ibrd[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [1]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~8 (
// Location: FF_X58_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[1] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~7_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y2_SIG ),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [1]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .mask = 16'hB391;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector10~1 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|break_error~q ),
	.C(\macro_inst|u_uart[0]|u_rx[3]|break_error~q ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector10~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .mask = 16'hF588;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~9 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector11~9 (
	.A(\macro_inst|u_uart[0]|u_regs|fbrd [1]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~6 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector9~6 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|overrun_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector9~5_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector9~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .mask = 16'hBCB0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~7 (
// Location: FF_X58_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[3] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector9~6_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y2_SIG ),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [3]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .mask = 16'hD591;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector11~5 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_rx[2]|parity_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector11~4_combout ),
	.D(\macro_inst|u_uart[0]|u_rx[3]|parity_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .mask = 16'hF858;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~6 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector11~6 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_reg [1]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|parity_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector10~3 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector10~2_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.C(\macro_inst|u_uart[0]|u_rx[5]|break_error~q ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector10~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .mask = 16'hE6A2;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector10~4 (
	.A(\macro_inst|u_uart[0]|u_regs|ibrd [2]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector10~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .mask = 16'hB383;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector9~5 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_reg [3]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|overrun_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector10~2 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_reg [2]),
	.B(\macro_inst|u_uart[0]|u_rx[4]|break_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~2 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[10] (
// Location: LCCOMB_X58_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|always1~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[10] (
	.A(\macro_inst|u_uart[0]|u_regs|Decoder1~1_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y2_SIG ),
	.SyncReset(SyncReset_X58_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y2_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|always1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [10]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[10] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X58_Y2_N0
alta_clkenctrl clken_ctrl_X58_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ));
defparam clken_ctrl_X58_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y2_N0
alta_asyncctrl asyncreset_ctrl_X58_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y2_SIG ));
defparam asyncreset_ctrl_X58_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y2_N1
alta_clkenctrl clken_ctrl_X58_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X58_Y2_SIG_SIG ));
defparam clken_ctrl_X58_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y2_N0
alta_syncctrl syncreset_ctrl_X58_Y2(.Din(), .Dout(SyncReset_X58_Y2_GND));
defparam syncreset_ctrl_X58_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y2_N1
alta_syncctrl syncload_ctrl_X58_Y2(.Din(), .Dout(SyncLoad_X58_Y2_VCC));
defparam syncload_ctrl_X58_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X58_Y3_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_pready (
// Location: LCCOMB_X58_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_read0 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_pready (
	.A(\macro_inst|u_ahb2apb|pwrite~q ),
	.B(\macro_inst|u_ahb2apb|penable~q ),
	.C(\macro_inst|u_ahb2apb|psel~q ),
	.D(\macro_inst|u_ahb2apb|paddr [12]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_pready~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_read0~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_pready~q ));
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .mask = 16'h0010;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_pready .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] (
// Location: LCCOMB_X58_Y3_N10
// alta_lcell_comb \macro_inst|uart_rxd[8] (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] (
	.A(vcc),
	.B(vcc),
	.C(\SIM_IO[8]~input_o ),
	.D(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X58_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [8]),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_in [0]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|framing_error (
// Location: LCCOMB_X58_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|framing_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|framing_error (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|Selector0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|framing_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .mask = 16'h7350;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|break_error (
// Location: LCCOMB_X58_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|break_error~0 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|break_error (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|always11~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|break_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .mask = 16'hFF50;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .mask = 16'h0005;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N18
// alta_lcell_comb \macro_inst|u_ahb2apb|pwrite~0 (
alta_slice \macro_inst|u_ahb2apb|pwrite~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.D(\macro_inst|u_ahb2apb|apbState.apbAccess~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|pwrite~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_ahb2apb|pwrite~0 .mask = 16'hF000;
defparam \macro_inst|u_ahb2apb|pwrite~0 .mode = "logic";
defparam \macro_inst|u_ahb2apb|pwrite~0 .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pwrite~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pwrite~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pwrite~0 .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|pwrite~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|pwrite~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|pwrite~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|pwrite~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_pready (
// Location: LCCOMB_X58_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_read0 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_pready (
	.A(\macro_inst|u_ahb2apb|pwrite~q ),
	.B(\macro_inst|u_ahb2apb|penable~q ),
	.C(\macro_inst|u_ahb2apb|psel~q ),
	.D(\macro_inst|u_ahb2apb|paddr [12]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_pready~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_pready~q ));
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_pready .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|status_reg[2] (
// Location: LCCOMB_X58_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|status_reg[2]~feeder (
alta_slice \macro_inst|u_uart[0]|u_regs|status_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|Mux10~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|status_reg[2]~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|status_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y3_GND),
	.SyncReset(SyncReset_X58_Y3_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X58_Y3_INV ),
	.LutOut(\macro_inst|u_uart[0]|u_regs|status_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|status_reg [2]));
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|status_reg[2] .SyncLoadMux = 2'b11;
// Location: LCCOMB_X58_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .mask = 16'h00F0;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ShiftLeft0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N24
// alta_lcell_comb \macro_inst|u_ahb2apb|Selector22~0 (
// Location: FF_X58_Y3_N24
// alta_lcell_ff \macro_inst|u_ahb2apb|penable (
alta_slice \macro_inst|u_ahb2apb|penable (
	.A(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.B(\macro_inst|u_ahb2apb|apbState.apbAccess~q ),
	.C(vcc),
	.D(\macro_inst|u_ahb2apb|apbState.apbIdle~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|penable~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|Selector22~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|penable~q ));
defparam \macro_inst|u_ahb2apb|penable .mask = 16'h7370;
defparam \macro_inst|u_ahb2apb|penable .mode = "logic";
defparam \macro_inst|u_ahb2apb|penable .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|penable .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|penable .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|penable .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|penable .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|penable .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|penable .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|penable .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .mask = 16'h0400;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[4]~20 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|parity_error (
// Location: LCCOMB_X58_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|parity_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|parity_error (
	.A(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always10~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|parity_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|parity_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .mask = 16'hDCFC;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[5]|parity_error (
// Location: LCCOMB_X58_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[5]|parity_error~1 (
alta_slice \macro_inst|u_uart[0]|u_rx[5]|parity_error (
	.A(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|parity_error~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[5]|rx_sample~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[5]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[5]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[5]|parity_error~q ));
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .mask = 16'hDC50;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[5]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|parity_error (
// Location: LCCOMB_X58_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|parity_error~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|parity_error (
	.A(\macro_inst|u_uart[1]|u_rx[0]|parity_error~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_sample~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|parity_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N6
// alta_lcell_ff \macro_inst|u_ahb2apb|pdone (
// Location: LCCOMB_X58_Y3_N6
// alta_lcell_comb \macro_inst|u_ahb2apb|pdone~0 (
alta_slice \macro_inst|u_ahb2apb|pdone (
	.A(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.B(\macro_inst|u_ahb2apb|psel~q ),
	.C(vcc),
	.D(\macro_inst|u_ahb2apb|penable~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|pdone~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|pdone~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|pdone~q ));
defparam \macro_inst|u_ahb2apb|pdone .mask = 16'h0800;
defparam \macro_inst|u_ahb2apb|pdone .mode = "logic";
defparam \macro_inst|u_ahb2apb|pdone .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pdone .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|pdone .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pdone .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|pdone .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|pdone .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|pdone .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|pdone .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y3_N8
// alta_lcell_ff \macro_inst|u_ahb2apb|psel (
// Location: LCCOMB_X58_Y3_N8
// alta_lcell_comb \macro_inst|u_ahb2apb|psel~0 (
alta_slice \macro_inst|u_ahb2apb|psel (
	.A(\macro_inst|u_ahb2apb|pvalid~q ),
	.B(\macro_inst|u_ahb2apb|apbState.apbIdle~q ),
	.C(vcc),
	.D(\macro_inst|u_ahb2apb|pwrite~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|psel~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|psel~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|psel~q ));
defparam \macro_inst|u_ahb2apb|psel .mask = 16'hBAF2;
defparam \macro_inst|u_ahb2apb|psel .mode = "logic";
defparam \macro_inst|u_ahb2apb|psel .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|psel .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|psel .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|psel .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|psel .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|psel .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|psel .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|psel .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y3_N0
alta_clkenctrl clken_ctrl_X58_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X58_Y3_SIG_SIG ));
defparam clken_ctrl_X58_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y3_N0
alta_asyncctrl asyncreset_ctrl_X58_Y3_N0(.Din(), .Dout(AsyncReset_X58_Y3_GND));
defparam asyncreset_ctrl_X58_Y3_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X58_Y3_N1
alta_clkenctrl clken_ctrl_X58_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y3_SIG_VCC ));
defparam clken_ctrl_X58_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y3_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y3_N1
alta_asyncctrl asyncreset_ctrl_X58_Y3_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y3_SIG ));
defparam asyncreset_ctrl_X58_Y3_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X58_Y3_N0
alta_syncctrl syncreset_ctrl_X58_Y3(.Din(), .Dout(SyncReset_X58_Y3_GND));
defparam syncreset_ctrl_X58_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y3_N1
alta_syncctrl syncload_ctrl_X58_Y3(.Din(\macro_inst|u_ahb2apb|paddr [10]), .Dout(\macro_inst|u_ahb2apb|paddr[10]__SyncLoad_X58_Y3_INV ));
defparam syncload_ctrl_X58_Y3.SyncCtrlMux = 2'b11;
// Location: LCCOMB_X58_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags~10 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags~10 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .mask = 16'h0400;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~7 (
// Location: FF_X58_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_ahb2apb|paddr [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_dma_en [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_dma_en [5]));
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .mask = 16'h55DD;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector2~3_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|always3~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .mask = 16'hF0E0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux12~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux12~1 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux12~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux12~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .mask = 16'hF588;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~11 (
// Location: FF_X58_Y4_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] (
	.A(\macro_inst|u_uart[0]|u_regs|tx_dma_en [4]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_dma_en [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2_combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(SyncReset_X58_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_dma_en [5]));
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .mask = 16'hBBC0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_dma_en[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 (
	.A(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 (
	.A(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Equal2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|always8~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|always8~1 (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|always8~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux12~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux12~0 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux12~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .mask = 16'hE5E0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux12~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_ahb2apb|paddr [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .mask = 16'h0010;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags[5]~16_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[5]~16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~12 (
// Location: FF_X58_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[1] (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X58_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~12_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [1]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .mask = 16'h0500;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 (
alta_slice \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|clear_flags[4]~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .mask = 16'hFBFF;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|clear_flags[4]~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y4_N0
alta_clkenctrl clken_ctrl_X58_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_dma_en[5]~2_combout_X58_Y4_SIG_SIG ));
defparam clken_ctrl_X58_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y4_N0
alta_asyncctrl asyncreset_ctrl_X58_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y4_SIG ));
defparam asyncreset_ctrl_X58_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y4_N1
alta_clkenctrl clken_ctrl_X58_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X58_Y4_SIG_SIG ));
defparam clken_ctrl_X58_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y4_N0
alta_syncctrl syncreset_ctrl_X58_Y4(.Din(), .Dout(SyncReset_X58_Y4_GND));
defparam syncreset_ctrl_X58_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y4_N1
alta_syncctrl syncload_ctrl_X58_Y4(.Din(), .Dout(SyncLoad_X58_Y4_VCC));
defparam syncload_ctrl_X58_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X58_Y5_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always3~1_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y5_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP (
// Location: LCCOMB_X58_Y5_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .mask = 16'hEEF0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .mask = 16'h5F00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y5_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|uart_en (
// Location: LCCOMB_X58_Y5_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|uart_en~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|uart_en (
	.A(\rv32.mem_ahb_hwdata[0] ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|always6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|uart_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|uart_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|uart_en~q ));
defparam \macro_inst|u_uart[0]|u_regs|uart_en .mask = 16'hB8F0;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|uart_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|uart_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags[2]~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .mask = 16'hFDFF;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[2]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Selector3~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Selector3~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|Selector4~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector4~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .mask = 16'hFEEE;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|ibrd[0]~_wirecell (
// Location: FF_X58_Y5_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|fbrd[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|fbrd[0] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_regs|ibrd [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|fbrd [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X58_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(SyncReset_X58_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y5_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|ibrd[0]~_wirecell_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|fbrd [0]));
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y5_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .mask = 16'hA0A0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y5_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|break_error (
// Location: LCCOMB_X58_Y5_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|break_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|break_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .mask = 16'hFCCC;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|break_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y5_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[2]|tx_complete (
// Location: LCCOMB_X58_Y5_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[2]|tx_complete~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[2]|tx_complete (
	.A(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_tx[2]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[2]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[2]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[2]|tx_complete~q ));
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .mask = 16'h5444;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[2]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y5_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY (
// Location: LCCOMB_X58_Y5_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Selector3~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y5_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Equal2~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Equal2~2 (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [2]),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .mask = 16'h0008;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~2 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y5_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|overrun_error (
// Location: LCCOMB_X58_Y5_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|overrun_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|overrun_error (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|overrun_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|overrun_error .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y5_N0
alta_clkenctrl clken_ctrl_X58_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y5_SIG_VCC ));
defparam clken_ctrl_X58_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y5_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y5_N0
alta_asyncctrl asyncreset_ctrl_X58_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y5_SIG ));
defparam asyncreset_ctrl_X58_Y5_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y5_N1
alta_clkenctrl clken_ctrl_X58_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always2~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X58_Y5_SIG_SIG ));
defparam clken_ctrl_X58_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y5_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y5_N0
alta_syncctrl syncreset_ctrl_X58_Y5(.Din(), .Dout(SyncReset_X58_Y5_GND));
defparam syncreset_ctrl_X58_Y5.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y5_N1
alta_syncctrl syncload_ctrl_X58_Y5(.Din(), .Dout(SyncLoad_X58_Y5_VCC));
defparam syncload_ctrl_X58_Y5.SyncCtrlMux = 2'b01;
// Location: FF_X58_Y6_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY (
// Location: LCCOMB_X58_Y6_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Selector4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Selector4~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector4~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector4~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .mask = 16'hF1F0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~5 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_complete (
// Location: LCCOMB_X58_Y6_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_complete~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_complete (
	.A(\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_complete~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .mask = 16'h3222;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_complete .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always11~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always11~2 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always11~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|always11~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_idle (
// Location: LCCOMB_X58_Y6_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_idle~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_idle (
	.A(\macro_inst|u_uart[1]|u_rx[1]|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_idle~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .mask = 16'hBAFA;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Selector4~3_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .mask = 16'hB9B1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always8~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|always8~0 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~q ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always8~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_idle (
// Location: LCCOMB_X58_Y6_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_idle~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_idle (
	.A(\macro_inst|u_uart[1]|u_rx[0]|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_idle~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .mask = 16'hBAFA;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_idle .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP (
// Location: LCCOMB_X58_Y6_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector4~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y6_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .mask = 16'hE0A0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y6_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] (
// Location: LCCOMB_X58_Y6_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ),
	.SyncReset(SyncReset_X58_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|Selector4~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[2] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X58_Y6_N0
alta_clkenctrl clken_ctrl_X58_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y6_SIG_VCC ));
defparam clken_ctrl_X58_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y6_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y6_N0
alta_asyncctrl asyncreset_ctrl_X58_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y6_SIG ));
defparam asyncreset_ctrl_X58_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y6_N1
alta_clkenctrl clken_ctrl_X58_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y6_SIG_SIG ));
defparam clken_ctrl_X58_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y6_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y6_N0
alta_syncctrl syncreset_ctrl_X58_Y6(.Din(), .Dout(SyncReset_X58_Y6_GND));
defparam syncreset_ctrl_X58_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y6_N1
alta_syncctrl syncload_ctrl_X58_Y6(.Din(), .Dout(SyncLoad_X58_Y6_VCC));
defparam syncload_ctrl_X58_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X58_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~12 (
// Location: FF_X58_Y7_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|overrun_error~q ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|break_error~q ),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[1]|u_regs|break_error_ie [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(SyncReset_X58_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~12_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .mask = 16'hECA0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[2] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y7_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[11] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_idle_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[2] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y7_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|overrun_error (
// Location: LCCOMB_X58_Y7_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|overrun_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|overrun_error (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|overrun_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|overrun_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y7_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector9~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|overrun_error~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|overrun_error~q ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector9~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .mask = 16'hCFA0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y7_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|parity_error (
// Location: LCCOMB_X58_Y7_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|parity_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|parity_error (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always10~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|parity_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|parity_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .mask = 16'hDCFC;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|parity_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y7_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always10~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always10~2 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|always2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|always10~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_sample~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always10~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~2 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y7_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] (
// Location: LCCOMB_X58_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Selector4~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_PARITY~q ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|framing_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(SyncReset_X58_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Selector4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|framing_error_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[2] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y7_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|break_error_ie[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|break_error_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[9] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|break_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|break_error_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|break_error_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~10 (
// Location: FF_X58_Y7_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [2]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(SyncReset_X58_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .mask = 16'hBA30;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X58_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector9~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|overrun_error~q ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|overrun_error~q ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .mask = 16'hFC0A;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|interrupts[0] (
// Location: LCCOMB_X58_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts[0] (
	.A(\macro_inst|u_uart[1]|u_regs|interrupts~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|interrupts~3_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|interrupts~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|interrupts~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|interrupts [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|interrupts [0]));
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y7_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~11 (
// Location: FF_X58_Y7_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|framing_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|framing_error_ie [2]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_rx[2]|parity_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|parity_error_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(SyncReset_X58_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|parity_error_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[2] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y7_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [2]));
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y7_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|interrupts[2] (
// Location: LCCOMB_X58_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~14 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts[2] (
	.A(\macro_inst|u_uart[1]|u_regs|interrupts~13_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|interrupts~11_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|interrupts~10_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|interrupts~12_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|interrupts [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~14_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|interrupts [2]));
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y7_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~0 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [0]),
	.C(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .mask = 16'hAE0C;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~0 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y7_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|overrun_error (
// Location: LCCOMB_X58_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|overrun_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|overrun_error (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|overrun_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|overrun_error .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y7_N0
alta_clkenctrl clken_ctrl_X58_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[2]~9_combout_X58_Y7_SIG_SIG ));
defparam clken_ctrl_X58_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X58_Y7_N0
alta_asyncctrl asyncreset_ctrl_X58_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y7_SIG ));
defparam asyncreset_ctrl_X58_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y7_N1
alta_clkenctrl clken_ctrl_X58_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y7_SIG_VCC ));
defparam clken_ctrl_X58_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y7_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X58_Y7_N0
alta_syncctrl syncreset_ctrl_X58_Y7(.Din(), .Dout(SyncReset_X58_Y7_GND));
defparam syncreset_ctrl_X58_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y7_N1
alta_syncctrl syncload_ctrl_X58_Y7(.Din(), .Dout(SyncLoad_X58_Y7_VCC));
defparam syncload_ctrl_X58_Y7.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X58_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|Selector0~0 (
// Location: FF_X58_Y8_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .mask = 16'hFF30;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en (
// Location: LCCOMB_X58_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .mask = 16'hAAFA;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|framing_error (
// Location: LCCOMB_X58_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|framing_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|framing_error (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|framing_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .mask = 16'hF222;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|break_error (
// Location: LCCOMB_X58_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|break_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|break_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .mask = 16'hFCCC;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_parity~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .mask = 16'h2800;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] (
// Location: LCCOMB_X58_Y8_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(SyncReset_X58_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout__SyncLoad_X58_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X58_Y8_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|parity_error (
// Location: LCCOMB_X58_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|parity_error~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|parity_error (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|parity_error~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|parity_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|parity_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en (
// Location: LCCOMB_X58_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .mask = 16'hFAAA;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux11~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux11~2 (
	.A(\macro_inst|u_uart[1]|u_regs|Mux11~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_fifo|counter ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .mask = 16'hEA4A;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_parity (
// Location: LCCOMB_X58_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_parity (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(AsyncReset_X58_Y8_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_parity~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always6~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|always6~1 (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_in [4]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_in [2]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_in [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .mask = 16'h0D04;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y8_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|always2~1 (
// Location: FF_X58_Y8_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_bit (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|always2~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_bit~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y8_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] (
// Location: LCCOMB_X58_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(SyncReset_X58_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout__SyncLoad_X58_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X58_Y8_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] (
// Location: LCCOMB_X58_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(SyncReset_X58_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout__SyncLoad_X58_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X58_Y8_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] (
// Location: LCCOMB_X58_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [3]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ),
	.SyncReset(SyncReset_X58_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout__SyncLoad_X58_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .mask = 16'h3C3C;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;

// Location: CLKENCTRL_X58_Y8_N0
alta_clkenctrl clken_ctrl_X58_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y8_SIG_VCC ));
defparam clken_ctrl_X58_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y8_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y8_N0
alta_asyncctrl asyncreset_ctrl_X58_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y8_SIG ));
defparam asyncreset_ctrl_X58_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: ASYNCCTRL_X58_Y8_N1
alta_asyncctrl asyncreset_ctrl_X58_Y8_N1(.Din(), .Dout(AsyncReset_X58_Y8_GND));
defparam asyncreset_ctrl_X58_Y8_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y8_N0
alta_syncctrl syncreset_ctrl_X58_Y8(.Din(), .Dout(SyncReset_X58_Y8_GND));
defparam syncreset_ctrl_X58_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y8_N1
alta_syncctrl syncload_ctrl_X58_Y8(.Din(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout ), .Dout(\macro_inst|u_uart[1]|u_rx[0]|always6~1_combout__SyncLoad_X58_Y8_SIG ));
defparam syncload_ctrl_X58_Y8.SyncCtrlMux = 2'b10;
// Location: FF_X58_Y9_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_write[4] (
// Location: LCCOMB_X58_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|tx_write~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_write[4] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_write [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_write~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_write [4]));
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[4] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|overrun_error (
// Location: LCCOMB_X58_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|overrun_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|overrun_error (
	.A(\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|overrun_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|overrun_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] (
// Location: LCCOMB_X58_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[0]|tx_stop (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[0]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_in [0]),
	.D(\macro_inst|u_uart[1]|u_tx[0]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X58_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(SyncReset_X58_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X58_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[0]|tx_stop~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_in [1]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .mask = 16'h0033;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: FF_X58_Y9_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_write[1] (
// Location: LCCOMB_X58_Y9_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|tx_write~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_write[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_write [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_write~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_write [1]));
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags[1]~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[1]~13 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] (
// Location: LCCOMB_X58_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|rx_read [1]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector0~0 (
// Location: FF_X58_Y9_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_read[1] (
// Location: LCCOMB_X58_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_read~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_read[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_read [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_read~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_read [1]));
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[1] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_complete (
// Location: LCCOMB_X58_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_complete~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_complete (
	.A(\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_complete~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .mask = 16'h2232;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_complete .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Add4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Add4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .mask = 16'h55AA;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_read[4] (
// Location: LCCOMB_X58_Y9_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_read~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_read[4] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_read [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_read~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_read [4]));
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[4] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en (
// Location: LCCOMB_X58_Y9_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|rx_idle_en~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .mask = 16'hDCFC;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X58_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux11~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux11~1 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_fifo|counter ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux11~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .mask = 16'hAAD8;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~1 .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|framing_error (
// Location: LCCOMB_X58_Y9_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|framing_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|framing_error (
	.A(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|framing_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .mask = 16'h44F4;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_read[5] (
// Location: LCCOMB_X58_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_read~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_read[5] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_read0~combout ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_read [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_read~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_read [5]));
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_read[5] .SyncLoadMux = 2'bxx;
// Location: FF_X58_Y9_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] (
// Location: LCCOMB_X58_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_regs|tx_write [1]),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_IDLE~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[1]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .mask = 16'h0ACA;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X58_Y9_N0
alta_clkenctrl clken_ctrl_X58_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X58_Y9_SIG_VCC ));
defparam clken_ctrl_X58_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y9_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X58_Y9_N0
alta_asyncctrl asyncreset_ctrl_X58_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X58_Y9_SIG ));
defparam asyncreset_ctrl_X58_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X58_Y9_N1
alta_clkenctrl clken_ctrl_X58_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X58_Y9_SIG_SIG ));
defparam clken_ctrl_X58_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X58_Y9_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X58_Y9_N0
alta_syncctrl syncreset_ctrl_X58_Y9(.Din(), .Dout(SyncReset_X58_Y9_GND));
defparam syncreset_ctrl_X58_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X58_Y9_N1
alta_syncctrl syncload_ctrl_X58_Y9(.Din(), .Dout(SyncLoad_X58_Y9_VCC));
defparam syncload_ctrl_X58_Y9.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always3~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector2~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .mask = 16'hF0E0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .mask = 16'hC0CC;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP (
// Location: LCCOMB_X59_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Selector4~4_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .mask = 16'hFC30;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~1 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] (
// Location: LCCOMB_X59_Y10_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always3~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Add4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .mask = 16'hECFD;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] (
// Location: LCCOMB_X59_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|Add4~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|always3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .mask = 16'hCDCF;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Selector4~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|Selector4~3_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .mask = 16'hEEAF;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] (
// Location: LCCOMB_X59_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always3~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout_X59_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .mask = 16'hCDCF;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .mask = 16'h0200;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always3~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always3~2 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|always3~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .mask = 16'hCC00;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always3~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY (
// Location: LCCOMB_X59_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_rx[3]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y10_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] (
// Location: LCCOMB_X59_Y10_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Add4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y10_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .mask = 16'h1032;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .mask = 16'h8A88;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .mask = 16'hF222;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|Selector4~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector4~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .mask = 16'hBBAE;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y10_N0
alta_clkenctrl clken_ctrl_X59_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y10_SIG_VCC ));
defparam clken_ctrl_X59_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y10_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X59_Y10_N0
alta_asyncctrl asyncreset_ctrl_X59_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y10_SIG ));
defparam asyncreset_ctrl_X59_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y10_N1
alta_clkenctrl clken_ctrl_X59_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout_X59_Y10_SIG_SIG ));
defparam clken_ctrl_X59_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y10_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y10_N1
alta_asyncctrl asyncreset_ctrl_X59_Y10_N1(.Din(), .Dout(AsyncReset_X59_Y10_GND));
defparam asyncreset_ctrl_X59_Y10_N1.AsyncCtrlMux = 2'b00;
// Location: LCCOMB_X59_Y11_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux4~2 (
// Location: FF_X59_Y11_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [4]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux7~2 (
// Location: FF_X59_Y11_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux7~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux3~2 (
// Location: FF_X59_Y11_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [3]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux3~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux5~2 (
// Location: FF_X59_Y11_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [5]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux5~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y11_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] (
// Location: LCCOMB_X59_Y11_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [2]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux0~2 (
// Location: FF_X59_Y11_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [0]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux0~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux6~2 (
// Location: FF_X59_Y11_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [6]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux6~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y11_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] (
// Location: LCCOMB_X59_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [6]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] (
// Location: LCCOMB_X59_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] (
// Location: LCCOMB_X59_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y11_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux2~2 (
// Location: FF_X59_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][2]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [2]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux2~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y11_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] (
// Location: LCCOMB_X59_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] (
// Location: LCCOMB_X59_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y11_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [7]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y11_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux1~2 (
// Location: FF_X59_Y11_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|fifo[1][1]~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [1]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y11_GND),
	.SyncReset(SyncReset_X59_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux1~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y11_N0
alta_clkenctrl clken_ctrl_X59_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ));
defparam clken_ctrl_X59_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y11_N0
alta_asyncctrl asyncreset_ctrl_X59_Y11_N0(.Din(), .Dout(AsyncReset_X59_Y11_GND));
defparam asyncreset_ctrl_X59_Y11_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X59_Y11_N1
alta_clkenctrl clken_ctrl_X59_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout_X59_Y11_SIG_SIG ));
defparam clken_ctrl_X59_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y11_N0
alta_syncctrl syncreset_ctrl_X59_Y11(.Din(), .Dout(SyncReset_X59_Y11_GND));
defparam syncreset_ctrl_X59_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y11_N1
alta_syncctrl syncload_ctrl_X59_Y11(.Din(), .Dout(SyncLoad_X59_Y11_VCC));
defparam syncload_ctrl_X59_Y11.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y12_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector4~2 (
// Location: FF_X59_Y12_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(SyncReset_X59_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y12_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .mask = 16'hBB00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y12_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] (
// Location: LCCOMB_X59_Y12_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector4~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|Selector3~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector4~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .mask = 16'hF8FD;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always11~1 (
// Location: FF_X59_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [0]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(SyncReset_X59_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y12_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y12_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector4~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector4~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .mask = 16'hAFBA;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP (
// Location: LCCOMB_X59_Y12_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] (
// Location: LCCOMB_X59_Y12_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always11~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always11~2 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|always11~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|always11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always11~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always11~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [5]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [4]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always11~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always11~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] (
// Location: LCCOMB_X59_Y12_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY (
// Location: LCCOMB_X59_Y12_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y12_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] (
// Location: LCCOMB_X59_Y12_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y12_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .mask = 16'h0200;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] (
// Location: LCCOMB_X59_Y12_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] (
	.A(),
	.B(),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [5]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ),
	.SyncReset(SyncReset_X59_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y12_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .mask = 16'hFFFF;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y12_N0
alta_clkenctrl clken_ctrl_X59_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[4]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|always4~2_combout_X59_Y12_SIG_SIG ));
defparam clken_ctrl_X59_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y12_N0
alta_asyncctrl asyncreset_ctrl_X59_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y12_SIG ));
defparam asyncreset_ctrl_X59_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y12_N1
alta_clkenctrl clken_ctrl_X59_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y12_SIG_VCC ));
defparam clken_ctrl_X59_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y12_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X59_Y12_N0
alta_syncctrl syncreset_ctrl_X59_Y12(.Din(), .Dout(SyncReset_X59_Y12_GND));
defparam syncreset_ctrl_X59_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y12_N1
alta_syncctrl syncload_ctrl_X59_Y12(.Din(), .Dout(SyncLoad_X59_Y12_VCC));
defparam syncload_ctrl_X59_Y12.SyncCtrlMux = 2'b01;
// Location: FF_X59_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|lcr_sps (
// Location: LCCOMB_X59_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|lcr_sps (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always5~1_combout_X59_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(SyncReset_X59_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_parity~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ));
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|lcr_sps .SyncLoadMux = 2'b01;
// Location: FF_X59_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_parity (
// Location: LCCOMB_X59_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_parity (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_parity~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_parity~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .mask = 16'h335A;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [0]),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .mask = 16'hECA0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector3~1 (
// Location: FF_X59_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|always0~0_combout ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|Selector3~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .mask = 16'hF8F0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|lcr_pen (
// Location: LCCOMB_X59_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|lcr_pen (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always5~1_combout_X59_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(SyncReset_X59_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ));
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .mask = 16'h5500;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|lcr_pen .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector5~4 (
// Location: FF_X59_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|uart_txd (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|uart_txd (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|Selector5~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|uart_txd~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .mask = 16'h0030;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|uart_txd .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|always0~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|Selector5~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .mask = 16'h1DFF;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt (
// Location: LCCOMB_X59_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .mask = 16'hFCCC;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|lcr_eps (
// Location: LCCOMB_X59_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|lcr_eps (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always5~1_combout_X59_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(SyncReset_X59_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ));
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|lcr_eps .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .mask = 16'h1320;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector4~1 (
// Location: FF_X59_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|always0~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .mask = 16'hFF20;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_parity (
// Location: LCCOMB_X59_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_parity (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_parity~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|lcr_stp2 (
// Location: LCCOMB_X59_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|lcr_stp2 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always5~1_combout_X59_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(SyncReset_X59_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ));
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .mask = 16'h00CC;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|lcr_stp2 .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector0~0 (
// Location: FF_X59_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .mask = 16'hAAFA;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y1_N0
alta_clkenctrl clken_ctrl_X59_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always5~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always5~1_combout_X59_Y1_SIG_SIG ));
defparam clken_ctrl_X59_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y1_N0
alta_asyncctrl asyncreset_ctrl_X59_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y1_SIG ));
defparam asyncreset_ctrl_X59_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y1_N1
alta_clkenctrl clken_ctrl_X59_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y1_SIG_VCC ));
defparam clken_ctrl_X59_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y1_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X59_Y1_N1
alta_asyncctrl asyncreset_ctrl_X59_Y1_N1(.Din(), .Dout(AsyncReset_X59_Y1_GND));
defparam asyncreset_ctrl_X59_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y1_N0
alta_syncctrl syncreset_ctrl_X59_Y1(.Din(), .Dout(SyncReset_X59_Y1_GND));
defparam syncreset_ctrl_X59_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y1_N1
alta_syncctrl syncload_ctrl_X59_Y1(.Din(), .Dout(SyncLoad_X59_Y1_VCC));
defparam syncload_ctrl_X59_Y1.SyncCtrlMux = 2'b01;
// Location: FF_X59_Y2_N0
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[8] (
// Location: LCCOMB_X59_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~4 (
alta_slice \macro_inst|u_ahb2apb|paddr[8] (
	.A(\macro_inst|u_uart[0]|u_rx[0]|parity_error~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_ahb2apb|haddr [8]),
	.D(\macro_inst|u_uart[0]|u_rx[1]|parity_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [8]));
defparam \macro_inst|u_ahb2apb|paddr[8] .mask = 16'hF2C2;
defparam \macro_inst|u_ahb2apb|paddr[8] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[8] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[8] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[8] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[8] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[8] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~27 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~27 (
	.A(\macro_inst|u_uart[0]|u_rx[5]|break_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|break_error_ie [5]),
	.C(\macro_inst|u_uart[0]|u_rx[5]|overrun_error~q ),
	.D(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~27_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~27 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~26 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~26 (
	.A(\macro_inst|u_uart[0]|u_regs|parity_error_ie [5]),
	.B(\macro_inst|u_uart[0]|u_rx[5]|framing_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|framing_error_ie [5]),
	.D(\macro_inst|u_uart[0]|u_rx[5]|parity_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~26_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~26 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y2_N14
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[9] (
// Location: LCCOMB_X59_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13 (
alta_slice \macro_inst|u_ahb2apb|haddr[9] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\rv32.mem_ahb_haddr[9] ),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [9]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [9]));
defparam \macro_inst|u_ahb2apb|haddr[9] .mask = 16'h2233;
defparam \macro_inst|u_ahb2apb|haddr[9] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[9] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[9] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[9] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[9] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N16
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[9] (
// Location: LCCOMB_X59_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~3 (
alta_slice \macro_inst|u_ahb2apb|paddr[9] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|parity_error~q ),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|haddr [9]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|parity_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [9]));
defparam \macro_inst|u_ahb2apb|paddr[9] .mask = 16'hCBC8;
defparam \macro_inst|u_ahb2apb|paddr[9] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[9] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[9] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[9] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[9] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[9] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N18
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[4] (
// Location: LCCOMB_X59_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~4 (
alta_slice \macro_inst|u_ahb2apb|paddr[4] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\macro_inst|u_ahb2apb|haddr [4]),
	.D(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [4]));
defparam \macro_inst|u_ahb2apb|paddr[4] .mask = 16'h8800;
defparam \macro_inst|u_ahb2apb|paddr[4] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[4] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[4] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[4] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N2
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[5] (
// Location: LCCOMB_X59_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~12 (
alta_slice \macro_inst|u_ahb2apb|paddr[5] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|haddr [5]),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~12_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [5]));
defparam \macro_inst|u_ahb2apb|paddr[5] .mask = 16'hF0FF;
defparam \macro_inst|u_ahb2apb|paddr[5] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[5] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[5] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[5] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N20
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[2] (
// Location: LCCOMB_X59_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Equal2~0 (
alta_slice \macro_inst|u_ahb2apb|haddr[2] (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\rv32.mem_ahb_haddr[2] ),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [2]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Equal2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [2]));
defparam \macro_inst|u_ahb2apb|haddr[2] .mask = 16'h0033;
defparam \macro_inst|u_ahb2apb|haddr[2] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[2] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[2] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[2] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N22
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[3] (
// Location: LCCOMB_X59_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5 (
alta_slice \macro_inst|u_ahb2apb|haddr[3] (
	.A(\macro_inst|u_ahb2apb|paddr [3]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\rv32.mem_ahb_haddr[3] ),
	.D(\macro_inst|u_ahb2apb|paddr [4]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [3]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [3]));
defparam \macro_inst|u_ahb2apb|haddr[3] .mask = 16'hFF44;
defparam \macro_inst|u_ahb2apb|haddr[3] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[3] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[3] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[3] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N24
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[6] (
// Location: LCCOMB_X59_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17 (
alta_slice \macro_inst|u_ahb2apb|haddr[6] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\rv32.mem_ahb_haddr[6] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [6]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [6]));
defparam \macro_inst|u_ahb2apb|haddr[6] .mask = 16'hCC44;
defparam \macro_inst|u_ahb2apb|haddr[6] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[6] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[6] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[6] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N26
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[8] (
// Location: LCCOMB_X59_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14 (
alta_slice \macro_inst|u_ahb2apb|haddr[8] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\rv32.mem_ahb_haddr[8] ),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [8]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [8]));
defparam \macro_inst|u_ahb2apb|haddr[8] .mask = 16'hBB88;
defparam \macro_inst|u_ahb2apb|haddr[8] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[8] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[8] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[8] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[8] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N28
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[3] (
alta_slice \macro_inst|u_ahb2apb|paddr[3] (
	.A(),
	.B(),
	.C(\macro_inst|u_ahb2apb|haddr [3]),
	.D(),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [3]));
defparam \macro_inst|u_ahb2apb|paddr[3] .mask = 16'hFFFF;
defparam \macro_inst|u_ahb2apb|paddr[3] .mode = "ripple";
defparam \macro_inst|u_ahb2apb|paddr[3] .modeMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[3] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[3] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N30
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[10] (
// Location: LCCOMB_X59_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~0 (
alta_slice \macro_inst|u_ahb2apb|haddr[10] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.C(\rv32.mem_ahb_haddr[10] ),
	.D(\macro_inst|u_uart[1]|u_regs|ibrd [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [10]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [10]));
defparam \macro_inst|u_ahb2apb|haddr[10] .mask = 16'h44EE;
defparam \macro_inst|u_ahb2apb|haddr[10] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[10] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[10] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[10] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[10] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N4
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[5] (
// Location: LCCOMB_X59_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Decoder1~1 (
alta_slice \macro_inst|u_ahb2apb|haddr[5] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\rv32.mem_ahb_haddr[5] ),
	.D(\macro_inst|u_ahb2apb|paddr [4]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [5]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Decoder1~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [5]));
defparam \macro_inst|u_ahb2apb|haddr[5] .mask = 16'h0022;
defparam \macro_inst|u_ahb2apb|haddr[5] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[5] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[5] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[5] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N6
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[10] (
// Location: LCCOMB_X59_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15 (
alta_slice \macro_inst|u_ahb2apb|paddr[10] (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_ahb2apb|haddr [10]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [10]));
defparam \macro_inst|u_ahb2apb|paddr[10] .mask = 16'h0C00;
defparam \macro_inst|u_ahb2apb|paddr[10] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[10] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[10] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[10] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[10] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[10] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y2_N8
// alta_lcell_ff \macro_inst|u_ahb2apb|haddr[4] (
// Location: LCCOMB_X59_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1 (
alta_slice \macro_inst|u_ahb2apb|haddr[4] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(vcc),
	.C(\rv32.mem_ahb_haddr[4] ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|haddr [4]),
	.Clk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ),
	.SyncReset(SyncReset_X59_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|haddr [4]));
defparam \macro_inst|u_ahb2apb|haddr[4] .mask = 16'hAA00;
defparam \macro_inst|u_ahb2apb|haddr[4] .mode = "logic";
defparam \macro_inst|u_ahb2apb|haddr[4] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|haddr[4] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|haddr[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|haddr[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|haddr[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y2_N0
alta_clkenctrl clken_ctrl_X59_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_ahb2apb|psel~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y2_SIG_SIG ));
defparam clken_ctrl_X59_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y2_N0
alta_asyncctrl asyncreset_ctrl_X59_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y2_SIG ));
defparam asyncreset_ctrl_X59_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y2_N1
alta_clkenctrl clken_ctrl_X59_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ), .ClkEn(\macro_inst|u_ahb2apb|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp__macro_inst|u_ahb2apb|always0~0_combout_X59_Y2_SIG_SIG ));
defparam clken_ctrl_X59_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y2_N0
alta_syncctrl syncreset_ctrl_X59_Y2(.Din(), .Dout(SyncReset_X59_Y2_GND));
defparam syncreset_ctrl_X59_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y2_N1
alta_syncctrl syncload_ctrl_X59_Y2(.Din(), .Dout(SyncLoad_X59_Y2_VCC));
defparam syncload_ctrl_X59_Y2.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~10_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .mask = 16'hDC8C;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|always1~0 (
// Location: FF_X59_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[6] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[6] (
	.A(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\rv32.mem_ahb_hwdata[6] ),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|always1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [6]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[6] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[15] (
// Location: LCCOMB_X59_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|always8~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[15] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[15] ),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [15]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .mask = 16'h5500;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[15] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y3_N14
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[7] (
// Location: LCCOMB_X59_Y3_N14
// alta_lcell_comb \macro_inst|u_apb_mux|always0~0 (
alta_slice \macro_inst|u_ahb2apb|paddr[7] (
	.A(\macro_inst|u_ahb2apb|psel~q ),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|haddr [7]),
	.D(\macro_inst|u_ahb2apb|penable~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_apb_mux|always0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [7]));
defparam \macro_inst|u_ahb2apb|paddr[7] .mask = 16'h00AA;
defparam \macro_inst|u_ahb2apb|paddr[7] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[7] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[7] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|always7~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|always7~0 (
	.A(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|always7~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|always7~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|always7~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|always7~0 (
	.A(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always7~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_write~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_write~0 (
	.A(\macro_inst|u_ahb2apb|psel~q ),
	.B(\macro_inst|u_ahb2apb|pwrite~q ),
	.C(\macro_inst|u_ahb2apb|paddr [12]),
	.D(\macro_inst|u_ahb2apb|penable~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_write~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y3_N20
// alta_lcell_ff \macro_inst|u_ahb2apb|pwrite (
// Location: LCCOMB_X59_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_read1 (
alta_slice \macro_inst|u_ahb2apb|pwrite (
	.A(\macro_inst|u_ahb2apb|paddr [12]),
	.B(\macro_inst|u_ahb2apb|penable~q ),
	.C(\macro_inst|u_ahb2apb|hwrite~q ),
	.D(\macro_inst|u_ahb2apb|psel~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|pwrite~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|pwrite~q ));
defparam \macro_inst|u_ahb2apb|pwrite .mask = 16'h0400;
defparam \macro_inst|u_ahb2apb|pwrite .mode = "logic";
defparam \macro_inst|u_ahb2apb|pwrite .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pwrite .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|pwrite .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|pwrite .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|pwrite .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|pwrite .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|pwrite .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|pwrite .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 (
	.A(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y3_N24
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[6] (
// Location: LCCOMB_X59_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~16 (
alta_slice \macro_inst|u_ahb2apb|paddr[6] (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_ahb2apb|haddr [6]),
	.D(\macro_inst|u_ahb2apb|paddr [7]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~16_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [6]));
defparam \macro_inst|u_ahb2apb|paddr[6] .mask = 16'h0008;
defparam \macro_inst|u_ahb2apb|paddr[6] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[6] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[6] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[6] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[6] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y3_N26
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[12] (
// Location: LCCOMB_X59_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_read1 (
alta_slice \macro_inst|u_ahb2apb|paddr[12] (
	.A(\macro_inst|u_ahb2apb|psel~q ),
	.B(\macro_inst|u_ahb2apb|pwrite~q ),
	.C(\macro_inst|u_ahb2apb|haddr [12]),
	.D(\macro_inst|u_ahb2apb|penable~q ),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_read1~combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [12]));
defparam \macro_inst|u_ahb2apb|paddr[12] .mask = 16'h2000;
defparam \macro_inst|u_ahb2apb|paddr[12] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[12] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[12] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[12] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[12] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[12] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[8] (
// Location: LCCOMB_X59_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13 (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[8] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [8]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .mask = 16'h0044;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[8] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y3_N30
// alta_lcell_ff \macro_inst|u_ahb2apb|paddr[2] (
// Location: LCCOMB_X59_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~10 (
alta_slice \macro_inst|u_ahb2apb|paddr[2] (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\macro_inst|u_ahb2apb|haddr [2]),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|paddr [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|paddr [2]));
defparam \macro_inst|u_ahb2apb|paddr[2] .mask = 16'h0800;
defparam \macro_inst|u_ahb2apb|paddr[2] .mode = "logic";
defparam \macro_inst|u_ahb2apb|paddr[2] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|paddr[2] .BypassEn = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|paddr[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|paddr[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_ahb2apb|paddr[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_write~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_write~0 (
	.A(\macro_inst|u_ahb2apb|psel~q ),
	.B(\macro_inst|u_ahb2apb|pwrite~q ),
	.C(\macro_inst|u_ahb2apb|paddr [12]),
	.D(\macro_inst|u_ahb2apb|penable~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .mask = 16'h0008;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_write~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Decoder1~0 (
// Location: FF_X59_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[11] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[11] (
	.A(\macro_inst|u_ahb2apb|paddr [7]),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ),
	.SyncReset(SyncReset_X59_Y3_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y3_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [11]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .mask = 16'h1100;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[11] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .mask = 16'hA0AA;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y3_N0
alta_clkenctrl clken_ctrl_X59_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y3_SIG_SIG ));
defparam clken_ctrl_X59_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y3_N0
alta_asyncctrl asyncreset_ctrl_X59_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y3_SIG ));
defparam asyncreset_ctrl_X59_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y3_N1
alta_clkenctrl clken_ctrl_X59_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_ahb2apb|psel~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|psel~1_combout_X59_Y3_SIG_SIG ));
defparam clken_ctrl_X59_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y3_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y3_N0
alta_syncctrl syncreset_ctrl_X59_Y3(.Din(), .Dout(SyncReset_X59_Y3_GND));
defparam syncreset_ctrl_X59_Y3.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y3_N1
alta_syncctrl syncload_ctrl_X59_Y3(.Din(), .Dout(SyncLoad_X59_Y3_VCC));
defparam syncload_ctrl_X59_Y3.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~1 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [1]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .mask = 16'hA0CF;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~5 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|rx_reg [1]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .mask = 16'hF4A4;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector9~3 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|overrun_error~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|overrun_error~q ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector9~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .mask = 16'hDDA0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~13 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~13 (
	.A(\macro_inst|u_uart[1]|u_regs|Selector11~9_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector11~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .mask = 16'hFF20;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~4 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|parity_error~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|parity_error~q ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector11~3_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .mask = 16'hCAF0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~10 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector11~10 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector11~3_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~13_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .mask = 16'hB383;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector11~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector11~13 (
// Location: FF_X59_Y4_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[14] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[14] (
	.A(\macro_inst|u_ahb2apb|paddr [3]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\rv32.mem_ahb_hwdata[14] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector11~9_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ),
	.SyncReset(SyncReset_X59_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector11~13_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [14]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .mask = 16'hDD00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[14] .SyncLoadMux = 2'b01;
// Location: FF_X59_Y4_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[14] (
// Location: LCCOMB_X59_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~12 (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[14] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector11~11_combout ),
	.C(\rv32.mem_ahb_hwdata[14] ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ),
	.SyncReset(SyncReset_X59_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~12_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [14]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .mask = 16'h8855;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[14] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~8 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~8 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [1]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .mask = 16'hDFCF;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector9~2 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|rx_reg [3]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector9~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .mask = 16'hDC98;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~6 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|parity_error~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|parity_error~q ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~5_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .mask = 16'hF588;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .mask = 16'hFFFB;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[0]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~9 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~9 (
	.A(\macro_inst|u_uart[1]|u_regs|Selector11~8_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector11~6_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~7_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .mask = 16'hEFEC;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags~10 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags~10 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .mask = 16'h0400;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~4 (
// Location: FF_X59_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[3] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector9~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ),
	.SyncReset(SyncReset_X59_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [3]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .mask = 16'hB391;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~2 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~12_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .mask = 16'hF020;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y4_N0
alta_clkenctrl clken_ctrl_X59_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y4_SIG_SIG ));
defparam clken_ctrl_X59_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y4_N0
alta_asyncctrl asyncreset_ctrl_X59_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y4_SIG ));
defparam asyncreset_ctrl_X59_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y4_N1
alta_clkenctrl clken_ctrl_X59_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y4_SIG_SIG ));
defparam clken_ctrl_X59_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y4_N0
alta_syncctrl syncreset_ctrl_X59_Y4(.Din(), .Dout(SyncReset_X59_Y4_GND));
defparam syncreset_ctrl_X59_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y4_N1
alta_syncctrl syncload_ctrl_X59_Y4(.Din(), .Dout(SyncLoad_X59_Y4_VCC));
defparam syncload_ctrl_X59_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y5_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~5 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|framing_error~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|framing_error~q ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector12~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .mask = 16'hDDA0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~4 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|rx_reg [0]),
	.C(\macro_inst|u_uart[1]|u_regs|Selector12~3_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .mask = 16'hFA44;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~9 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector5~9 (
	.A(\macro_inst|u_uart[1]|u_regs|Selector5~8_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector5~7_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .mask = 16'h3E0E;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~9 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y5_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[13] (
// Location: LCCOMB_X59_Y5_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~7 (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[13] (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [2]),
	.C(\rv32.mem_ahb_hwdata[13] ),
	.D(\macro_inst|u_uart[1]|u_regs|fbrd [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(SyncReset_X59_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [13]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .mask = 16'h2200;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[13] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y5_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~8 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector5~8 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector5~4_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector5~7_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .mask = 16'h5E0E;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~10 (
// Location: FF_X59_Y5_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[7] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[7] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector5~2_combout ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector5~9_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(SyncReset_X59_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [7]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .mask = 16'hDDA0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[7] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y5_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~4 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|framing_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_reg [0]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .mask = 16'hAAD8;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~9 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector5~9 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_reg [7]),
	.C(\macro_inst|u_ahb2apb|paddr [2]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector5~8_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .mask = 16'hA2AA;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~9 (
// Location: FF_X59_Y5_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[0] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector12~8_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector12~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(SyncReset_X59_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [0]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .mask = 16'hEC64;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y5_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~9 (
// Location: FF_X59_Y5_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[0] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[0] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector12~8_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector12~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(SyncReset_X59_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [0]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .mask = 16'hEC64;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y5_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~6 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [2]),
	.C(\macro_inst|u_uart[1]|u_regs|uart_en~q ),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .mask = 16'h0020;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~4 (
// Location: FF_X59_Y5_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[2] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector10~3_combout ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(SyncReset_X59_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [2]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .mask = 16'hA0DD;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y5_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [2]),
	.C(\macro_inst|u_ahb2apb|paddr [4]),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .mask = 16'h000D;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~2 (
// Location: FF_X59_Y5_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[13] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[13] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[13] ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ),
	.SyncReset(SyncReset_X59_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [13]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[13] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y5_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~5 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.B(\macro_inst|u_uart[0]|u_rx[5]|framing_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector12~3_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector12~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .mask = 16'hDDA0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y5_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~8 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~8 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector12~7_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector12~6_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .mask = 16'h55E4;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~8 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y5_N0
alta_clkenctrl clken_ctrl_X59_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ));
defparam clken_ctrl_X59_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y5_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y5_N0
alta_asyncctrl asyncreset_ctrl_X59_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y5_SIG ));
defparam asyncreset_ctrl_X59_Y5_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y5_N1
alta_clkenctrl clken_ctrl_X59_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X59_Y5_SIG_SIG ));
defparam clken_ctrl_X59_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y5_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y5_N0
alta_syncctrl syncreset_ctrl_X59_Y5(.Din(), .Dout(SyncReset_X59_Y5_GND));
defparam syncreset_ctrl_X59_Y5.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y5_N1
alta_syncctrl syncload_ctrl_X59_Y5(.Din(), .Dout(SyncLoad_X59_Y5_VCC));
defparam syncload_ctrl_X59_Y5.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y6_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector10~2 (
	.A(\macro_inst|u_uart[1]|u_regs|rx_reg [2]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector10~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .mask = 16'hF2C2;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|framing_error (
// Location: LCCOMB_X59_Y6_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|framing_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|framing_error (
	.A(\macro_inst|u_uart[1]|u_rx[0]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|framing_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .mask = 16'hD5C0;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|framing_error (
// Location: LCCOMB_X59_Y6_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|framing_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|framing_error (
	.A(\macro_inst|u_uart[1]|u_rx[3]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|framing_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .mask = 16'h22F2;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|framing_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector10~0 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[1]|break_error~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|break_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .mask = 16'hB9A8;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|break_error (
// Location: LCCOMB_X59_Y6_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[0]|break_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags[0]~12_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[0]|always11~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[0]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|break_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .mask = 16'hFFC0;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[0]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector10~1 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|break_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector10~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|break_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .mask = 16'hBC8C;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~1 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_idle (
// Location: LCCOMB_X59_Y6_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_idle~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_idle (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|always8~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_idle~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_idle .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|framing_error~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_rx[0]|framing_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .mask = 16'hE3E0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux2~5 (
// Location: FF_X59_Y6_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_reg[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_reg[2] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|Mux2~2_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[1]|u_regs|Mux2~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux2~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_reg [2]));
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .mask = 16'h4F40;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_reg[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|always11~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|always11~2 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always11~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[1]|Selector2~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|always11~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[1]|break_error (
// Location: LCCOMB_X59_Y6_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[1]|break_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[1]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[1]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[1]~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[1]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[1]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[1]|break_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[1]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector0~1 (
// Location: FF_X59_Y6_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [2]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X59_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(SyncReset_X59_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector0~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .mask = 16'hF588;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y6_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector12~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector12~3 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|framing_error~q ),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|framing_error~q ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector12~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector12~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .mask = 16'hBBC0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector12~3 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|framing_error (
// Location: LCCOMB_X59_Y6_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|framing_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|framing_error (
	.A(\macro_inst|u_uart[1]|u_rx[2]|Selector2~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[2]~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|framing_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .mask = 16'hF222;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y6_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|break_error (
// Location: LCCOMB_X59_Y6_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|break_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|break_error (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always11~2_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|break_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .mask = 16'hAAFA;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|break_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y6_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector10~3 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|break_error~q ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|break_error~q ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector10~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y6_N0
alta_clkenctrl clken_ctrl_X59_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y6_SIG_VCC ));
defparam clken_ctrl_X59_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y6_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X59_Y6_N0
alta_asyncctrl asyncreset_ctrl_X59_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y6_SIG ));
defparam asyncreset_ctrl_X59_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y6_N1
alta_clkenctrl clken_ctrl_X59_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X59_Y6_SIG_SIG ));
defparam clken_ctrl_X59_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y6_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y6_N1
alta_asyncctrl asyncreset_ctrl_X59_Y6_N1(.Din(), .Dout(AsyncReset_X59_Y6_GND));
defparam asyncreset_ctrl_X59_Y6_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y6_N0
alta_syncctrl syncreset_ctrl_X59_Y6(.Din(), .Dout(SyncReset_X59_Y6_GND));
defparam syncreset_ctrl_X59_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y6_N1
alta_syncctrl syncload_ctrl_X59_Y6(.Din(), .Dout(SyncLoad_X59_Y6_VCC));
defparam syncload_ctrl_X59_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~7 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector5~7 (
	.A(\macro_inst|u_uart[1]|u_regs|Selector5~3_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector5~6_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .mask = 16'h88C0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector2~0 (
// Location: FF_X59_Y7_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .mask = 16'hDC98;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~7 (
// Location: FF_X59_Y7_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|break_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|break_error_ie [1]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|overrun_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector5~6 (
	.A(\macro_inst|u_uart[1]|u_regs|status_reg [4]),
	.B(\macro_inst|u_uart[1]|u_regs|Selector5~4_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector5~5_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .mask = 16'hC0AA;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector5~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~4 (
// Location: FF_X59_Y7_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|framing_error_ie [2]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|framing_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|framing_error_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .mask = 16'hFFD8;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector3~1 (
// Location: FF_X59_Y7_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|break_error_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|break_error_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|break_error_ie [1]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|break_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|break_error_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .mask = 16'h44FA;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~2 (
	.A(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [0]),
	.B(\macro_inst|u_uart[1]|u_regs|break_error_ie [0]),
	.C(\macro_inst|u_uart[1]|u_rx[0]|break_error~q ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|overrun_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_regs|parity_error_ie [0]),
	.B(\macro_inst|u_uart[1]|u_regs|parity_error_ie [1]),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .mask = 16'hFC0A;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~5 (
// Location: FF_X59_Y7_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|framing_error_ie [3]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|framing_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|framing_error_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .mask = 16'hD8FF;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~1 (
// Location: FF_X59_Y7_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] (
	.A(\macro_inst|u_uart[1]|u_rx[0]|parity_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|framing_error_ie [0]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|framing_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|parity_error_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|parity_error_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .mask = 16'hECA0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~10 (
// Location: FF_X59_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [2]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .mask = 16'hFFD8;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~6 (
// Location: FF_X59_Y7_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] (
	.A(\macro_inst|u_uart[1]|u_regs|framing_error_ie [1]),
	.B(\macro_inst|u_uart[1]|u_rx[1]|parity_error~q ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_rx[1]|framing_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|parity_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|parity_error_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_uart[1]|u_regs|always7~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [9]),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .mask = 16'h0004;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~11 (
// Location: FF_X59_Y7_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .mask = 16'hFE76;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~3 (
// Location: FF_X59_Y7_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|break_error_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|break_error_ie[1] (
	.A(\macro_inst|u_uart[1]|u_regs|framing_error_ie [4]),
	.B(\macro_inst|u_uart[1]|u_regs|framing_error_ie [5]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|break_error_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|break_error_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~10 (
// Location: FF_X59_Y7_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X59_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ),
	.SyncReset(SyncReset_X59_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .mask = 16'hFBD9;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y7_N0
alta_clkenctrl clken_ctrl_X59_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X59_Y7_SIG_SIG ));
defparam clken_ctrl_X59_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y7_N0
alta_asyncctrl asyncreset_ctrl_X59_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y7_SIG ));
defparam asyncreset_ctrl_X59_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y7_N1
alta_clkenctrl clken_ctrl_X59_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X59_Y7_SIG_SIG ));
defparam clken_ctrl_X59_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y7_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y7_N0
alta_syncctrl syncreset_ctrl_X59_Y7(.Din(), .Dout(SyncReset_X59_Y7_GND));
defparam syncreset_ctrl_X59_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y7_N1
alta_syncctrl syncload_ctrl_X59_Y7(.Din(), .Dout(SyncLoad_X59_Y7_VCC));
defparam syncload_ctrl_X59_Y7.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|Selector2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|always3~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Selector0~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .mask = 16'hAAA8;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Selector0~4 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] (
// Location: LCCOMB_X59_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_dma_en [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(SyncReset_X59_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_dma_en [1]));
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always8~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always8~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_idle_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always8~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Selector3~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .mask = 16'hAE0C;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always10~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always10~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_in [4]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_in [3]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_parity~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always10~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .mask = 16'hD42B;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always10~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|always6~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|always6~1 (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_in [4]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_in [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .mask = 16'h3110;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|always6~1 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] (
// Location: LCCOMB_X59_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_dma_en [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(SyncReset_X59_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_dma_en [1]));
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .mask = 16'h44CC;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always3~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always3~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[4]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[5]~16 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y8_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] (
// Location: LCCOMB_X59_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_dma_en [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(SyncReset_X59_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_dma_en [0]));
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .mask = 16'h22AA;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X59_Y8_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[0]~12_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .mask = 16'hC000;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .mask = 16'hEFFF;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[4]~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 (
alta_slice \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_ahb2apb|paddr [10]),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|clear_flags[3]~11 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~10 (
// Location: FF_X59_Y8_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|tx_dma_en [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_dma_en [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4_combout_X59_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ),
	.SyncReset(SyncReset_X59_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X59_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_dma_en [0]));
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .mask = 16'hDC98;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[0] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X59_Y8_N0
alta_clkenctrl clken_ctrl_X59_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[1]~3_combout_X59_Y8_SIG_SIG ));
defparam clken_ctrl_X59_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y8_N0
alta_asyncctrl asyncreset_ctrl_X59_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y8_SIG ));
defparam asyncreset_ctrl_X59_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X59_Y8_N1
alta_clkenctrl clken_ctrl_X59_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[0]~4_combout_X59_Y8_SIG_SIG ));
defparam clken_ctrl_X59_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y8_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X59_Y8_N0
alta_syncctrl syncreset_ctrl_X59_Y8(.Din(), .Dout(SyncReset_X59_Y8_GND));
defparam syncreset_ctrl_X59_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X59_Y8_N1
alta_syncctrl syncload_ctrl_X59_Y8(.Din(), .Dout(SyncLoad_X59_Y8_VCC));
defparam syncload_ctrl_X59_Y8.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X59_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[3]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] (
// Location: LCCOMB_X59_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|always3~2_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Add4~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .mask = 16'hECEF;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] (
// Location: LCCOMB_X59_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_read [4]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .mask = 16'h5F50;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Add4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Add4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .mask = 16'h0F1E;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] (
// Location: LCCOMB_X59_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_rx[4]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|Add4~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .mask = 16'hCCDF;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always8~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always8~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_idle_en~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always8~0 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] (
// Location: LCCOMB_X59_Y9_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|Add4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X59_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .mask = 16'h0072;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|Add4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|Add4~1 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .mask = 16'h3366;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|always3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|always3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .mask = 16'hFFCC;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3 .SyncLoadMux = 2'bxx;
// Location: FF_X59_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] (
// Location: LCCOMB_X59_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|always3~2_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout_X59_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X59_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .mask = 16'hFF07;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X59_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_parity~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [0]),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector5~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X59_Y9_N0
alta_clkenctrl clken_ctrl_X59_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[4]|rx_data_cnt[0]~3_combout_X59_Y9_SIG_SIG ));
defparam clken_ctrl_X59_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X59_Y9_N0
alta_asyncctrl asyncreset_ctrl_X59_Y9_N0(.Din(), .Dout(AsyncReset_X59_Y9_GND));
defparam asyncreset_ctrl_X59_Y9_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X59_Y9_N1
alta_clkenctrl clken_ctrl_X59_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X59_Y9_SIG_VCC ));
defparam clken_ctrl_X59_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X59_Y9_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X59_Y9_N1
alta_asyncctrl asyncreset_ctrl_X59_Y9_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X59_Y9_SIG ));
defparam asyncreset_ctrl_X59_Y9_N1.AsyncCtrlMux = 2'b10;
// Location: LCCOMB_X60_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .mask = 16'h4440;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_sample~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_sample~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y10_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] (
// Location: LCCOMB_X60_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [0]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout__SyncLoad_X60_Y10_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X60_Y10_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] (
// Location: LCCOMB_X60_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout__SyncLoad_X60_Y10_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X60_Y10_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] (
// Location: LCCOMB_X60_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout__SyncLoad_X60_Y10_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X60_Y10_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] (
// Location: LCCOMB_X60_Y10_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(\~GND~combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(SyncReset_X60_Y10_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout__SyncLoad_X60_Y10_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X60_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector2~6 (
// Location: FF_X60_Y10_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Selector2~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|Selector2~3_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector2~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .mask = 16'h3320;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector0~0 (
// Location: FF_X60_Y10_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Selector2~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .mask = 16'h3033;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y10_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] (
// Location: LCCOMB_X60_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X60_Y10_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector1~0 (
// Location: FF_X60_Y10_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Selector2~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Selector2~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .mask = 16'h2232;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always2~1 (
// Location: FF_X60_Y10_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_bit (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_bit (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[3]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always2~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always2~0 (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [3]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_baud_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|Selector2~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y10_N0
alta_clkenctrl clken_ctrl_X60_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[3]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[3]|always4~2_combout_X60_Y10_SIG_SIG ));
defparam clken_ctrl_X60_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y10_N0.ClkEnMux = 2'b10;

// Location: CLKENCTRL_X60_Y10_N1
alta_clkenctrl clken_ctrl_X60_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y10_SIG_VCC ));
defparam clken_ctrl_X60_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y10_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X60_Y10_N1
alta_asyncctrl asyncreset_ctrl_X60_Y10_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y10_SIG ));
defparam asyncreset_ctrl_X60_Y10_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X60_Y10_N0
alta_syncctrl syncreset_ctrl_X60_Y10(.Din(), .Dout(SyncReset_X60_Y10_GND));
defparam syncreset_ctrl_X60_Y10.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y10_N1
alta_syncctrl syncload_ctrl_X60_Y10(.Din(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout ), .Dout(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout__SyncLoad_X60_Y10_SIG ));
defparam syncload_ctrl_X60_Y10.SyncCtrlMux = 2'b10;
// Location: FF_X60_Y11_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] (
// Location: LCCOMB_X60_Y11_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector0~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[0]|rx_in [0]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[0]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[0]|rx_in [1]));
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .mask = 16'h00BB;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[0]|rx_in[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|always4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y11_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] (
// Location: LCCOMB_X60_Y11_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Add1~0 (
// Location: FF_X60_Y11_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_in [3]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_in [4]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_in [2]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .mask = 16'h4D4D;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y11_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] (
// Location: LCCOMB_X60_Y11_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always11~0 (
// Location: FF_X60_Y11_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [5]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [6]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always11~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .mask = 16'h1000;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector4~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .mask = 16'hAD8D;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_sample~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always2~1 (
// Location: FF_X60_Y11_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y11_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always11~1 (
// Location: FF_X60_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [2]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [1]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always11~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_parity~0 (
// Location: FF_X60_Y11_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_parity~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[6] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y11_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] (
// Location: LCCOMB_X60_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_sample~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_in [1]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_sample~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_in [2]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y11_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always6~1 (
// Location: FF_X60_Y11_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_in [2]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(SyncReset_X60_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_in [3]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .mask = 16'h4054;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y11_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] (
// Location: LCCOMB_X60_Y11_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_shift_reg[1] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y11_N0
alta_clkenctrl clken_ctrl_X60_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y11_SIG_SIG ));
defparam clken_ctrl_X60_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y11_N0
alta_asyncctrl asyncreset_ctrl_X60_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y11_SIG ));
defparam asyncreset_ctrl_X60_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y11_N1
alta_clkenctrl clken_ctrl_X60_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[5]|always4~2_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|always4~2_combout_X60_Y11_SIG_SIG ));
defparam clken_ctrl_X60_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y11_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y11_N0
alta_syncctrl syncreset_ctrl_X60_Y11(.Din(), .Dout(SyncReset_X60_Y11_GND));
defparam syncreset_ctrl_X60_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y11_N1
alta_syncctrl syncload_ctrl_X60_Y11(.Din(), .Dout(SyncLoad_X60_Y11_VCC));
defparam syncload_ctrl_X60_Y11.SyncCtrlMux = 2'b01;
// Location: FF_X60_Y12_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] (
// Location: LCCOMB_X60_Y12_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] (
// Location: LCCOMB_X60_Y12_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [7]),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6]~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] (
// Location: LCCOMB_X60_Y12_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [1]),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] (
// Location: LCCOMB_X60_Y12_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][4]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [5]),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] (
// Location: LCCOMB_X60_Y12_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(SyncReset_X60_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y12_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .mask = 16'hFF88;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y12_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] (
// Location: LCCOMB_X60_Y12_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][1]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] (
// Location: LCCOMB_X60_Y12_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][2]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] (
// Location: LCCOMB_X60_Y12_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][3]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [4]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] (
// Location: LCCOMB_X60_Y12_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][7]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .mask = 16'hF3C0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X60_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y12_N0
alta_clkenctrl clken_ctrl_X60_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_shift_reg[2]~1_combout_X60_Y12_SIG_SIG ));
defparam clken_ctrl_X60_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y12_N0
alta_asyncctrl asyncreset_ctrl_X60_Y12_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y12_SIG ));
defparam asyncreset_ctrl_X60_Y12_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y12_N1
alta_clkenctrl clken_ctrl_X60_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout_X60_Y12_SIG_SIG ));
defparam clken_ctrl_X60_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y12_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y12_N1
alta_asyncctrl asyncreset_ctrl_X60_Y12_N1(.Din(), .Dout(AsyncReset_X60_Y12_GND));
defparam asyncreset_ctrl_X60_Y12_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y12_N0
alta_syncctrl syncreset_ctrl_X60_Y12(.Din(), .Dout(SyncReset_X60_Y12_GND));
defparam syncreset_ctrl_X60_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y12_N1
alta_syncctrl syncload_ctrl_X60_Y12(.Din(), .Dout(SyncLoad_X60_Y12_VCC));
defparam syncload_ctrl_X60_Y12.SyncCtrlMux = 2'b01;
// Location: FF_X60_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|fbrd[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|fbrd[2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|fbrd [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X60_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|fbrd[2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|fbrd [2]));
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|always2~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|always2~0 (
	.A(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|comb~1 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .mask = 16'h00A0;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|comb~1 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|fbrd[4] (
// Location: LCCOMB_X60_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|fbrd[4] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|fbrd [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X60_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(SyncReset_X60_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y1_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|fbrd [4]));
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .mask = 16'h4444;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|LessThan0~1 (
alta_slice \macro_inst|u_uart[0]|u_baud|LessThan0~1 (
	.A(\macro_inst|u_uart[0]|u_regs|fbrd [0]),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [5]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|u_uart[0]|u_baud|LessThan0~1_cout ),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .mask = 16'h0022;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|LessThan0~3 (
alta_slice \macro_inst|u_uart[0]|u_baud|LessThan0~3 (
	.A(\macro_inst|u_uart[0]|u_regs|fbrd [1]),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|LessThan0~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|u_uart[0]|u_baud|LessThan0~3_cout ),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .mask = 16'h004D;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~3 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_write[2] (
// Location: LCCOMB_X60_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|tx_write~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_write[2] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[2]~14_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_write [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_write~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_write [2]));
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .mask = 16'hA000;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|LessThan0~5 (
alta_slice \macro_inst|u_uart[0]|u_baud|LessThan0~5 (
	.A(\macro_inst|u_uart[0]|u_baud|f_cnt [3]),
	.B(\macro_inst|u_uart[0]|u_regs|fbrd [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|LessThan0~3_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|u_uart[0]|u_baud|LessThan0~5_cout ),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .mask = 16'h004D;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|LessThan0~7 (
// Location: FF_X60_Y1_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|fbrd[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|fbrd[3] (
	.A(\macro_inst|u_uart[0]|u_regs|fbrd [3]),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [2]),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|LessThan0~5_cout ),
	.Qin(\macro_inst|u_uart[0]|u_regs|fbrd [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X60_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(SyncReset_X60_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y1_VCC),
	.LutOut(),
	.Cout(\macro_inst|u_uart[0]|u_baud|LessThan0~7_cout ),
	.Q(\macro_inst|u_uart[0]|u_regs|fbrd [3]));
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .mask = 16'h004D;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|LessThan0~9 (
alta_slice \macro_inst|u_uart[0]|u_baud|LessThan0~9 (
	.A(\macro_inst|u_uart[0]|u_baud|f_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_regs|fbrd [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|LessThan0~7_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|u_uart[0]|u_baud|LessThan0~9_cout ),
	.Q());
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .mask = 16'h004D;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|LessThan0~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|LessThan0~10 (
// Location: FF_X60_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_del (
alta_slice \macro_inst|u_uart[0]|u_baud|f_del (
	.A(\macro_inst|u_uart[0]|u_regs|fbrd [5]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_baud|f_cnt [0]),
	.Cin(\macro_inst|u_uart[0]|u_baud|LessThan0~9_cout ),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_del~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_baud|LessThan0~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_baud|f_del~q ));
defparam \macro_inst|u_uart[0]|u_baud|f_del .mask = 16'hA0FA;
defparam \macro_inst|u_uart[0]|u_baud|f_del .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|f_del .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_del .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_del .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_del .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_del .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_del .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_del .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_baud|f_del .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] (
// Location: LCCOMB_X60_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|tx_write [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .mask = 16'h4F40;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|fbrd[5] (
// Location: LCCOMB_X60_Y1_N30
// alta_lcell_comb \macro_inst|uart_rxd[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|fbrd[5] (
	.A(vcc),
	.B(\SIM_IO[3]~input_o ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|fbrd [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X60_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(SyncReset_X60_Y1_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y1_VCC),
	.LutOut(\macro_inst|uart_rxd [3]),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|fbrd [5]));
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .mask = 16'h0033;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_stop_cnt~q ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .mask = 16'hFA8A;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|fbrd[1] (
alta_slice \macro_inst|u_uart[0]|u_regs|fbrd[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|fbrd [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X60_Y1_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|fbrd[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|fbrd [1]));
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector5~4 (
// Location: FF_X60_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|uart_txd (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|uart_txd (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_STOP~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|Selector5~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|uart_txd~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .mask = 16'h0050;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|uart_txd .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y1_N0
alta_clkenctrl clken_ctrl_X60_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always2~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X60_Y1_SIG_SIG ));
defparam clken_ctrl_X60_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y1_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y1_N0
alta_asyncctrl asyncreset_ctrl_X60_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y1_SIG ));
defparam asyncreset_ctrl_X60_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y1_N1
alta_clkenctrl clken_ctrl_X60_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y1_SIG_VCC ));
defparam clken_ctrl_X60_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y1_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X60_Y1_N0
alta_syncctrl syncreset_ctrl_X60_Y1(.Din(), .Dout(SyncReset_X60_Y1_GND));
defparam syncreset_ctrl_X60_Y1.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y1_N1
alta_syncctrl syncload_ctrl_X60_Y1(.Din(), .Dout(SyncLoad_X60_Y1_VCC));
defparam syncload_ctrl_X60_Y1.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector3~4 (
// Location: FF_X60_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[9] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[9] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|Selector3~3_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector3~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [9]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .mask = 16'h00F0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~12 (
// Location: FF_X60_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector5~6_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|framing_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(SyncReset_X60_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~12_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|framing_error_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .mask = 16'hF780;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|framing_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector0~3 (
// Location: FF_X60_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|Selector0~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(SyncReset_X60_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|tx_complete_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector0~4 (
// Location: FF_X60_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[12] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[12] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|Selector0~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector0~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [12]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[12] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector2~3 (
// Location: FF_X60_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|Selector2~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(SyncReset_X60_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector2~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|overrun_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector1~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector1~2 (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|ibrd [11]),
	.C(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [4]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector1~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .mask = 16'hAAE4;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector1~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector0~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector0~2 (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|ibrd [12]),
	.C(\macro_inst|u_uart[0]|u_regs|tx_complete_ie [4]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .mask = 16'hAAE4;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 (
	.A(\macro_inst|u_ahb2apb|paddr [9]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[0]|u_regs|always7~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector3~3 (
// Location: FF_X60_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|break_error_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|break_error_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|Selector3~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector3~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|break_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(SyncReset_X60_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector3~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|break_error_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|break_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector2~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector2~2 (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|ibrd [10]),
	.C(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [4]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .mask = 16'hAAE4;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector1~4 (
// Location: FF_X60_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[11] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[11] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|Selector1~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector1~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [11]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector1~3 (
// Location: FF_X60_Y2_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|Selector1~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector1~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(SyncReset_X60_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector1~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|rx_idle_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .mask = 16'hF388;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|rx_idle_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector2~4 (
// Location: FF_X60_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[10] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[10] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|Selector2~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector2~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [10]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~7 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector5~7 (
	.A(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector5~11_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector5~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .mask = 16'hA820;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector5~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector4~3 (
// Location: FF_X60_Y2_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] (
	.A(\macro_inst|u_uart[0]|u_regs|Selector4~2_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector4~1_combout ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|parity_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(SyncReset_X60_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector4~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|parity_error_ie [5]));
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .mask = 16'hE4AA;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|parity_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector4~4 (
// Location: FF_X60_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[8] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[8] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|Selector4~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector4~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [8]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .mask = 16'h3300;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[8] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y2_N0
alta_clkenctrl clken_ctrl_X60_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y2_SIG_SIG ));
defparam clken_ctrl_X60_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y2_N0
alta_asyncctrl asyncreset_ctrl_X60_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y2_SIG ));
defparam asyncreset_ctrl_X60_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y2_N1
alta_clkenctrl clken_ctrl_X60_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[5]~21_combout_X60_Y2_SIG_SIG ));
defparam clken_ctrl_X60_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y2_N0
alta_syncctrl syncreset_ctrl_X60_Y2(.Din(), .Dout(SyncReset_X60_Y2_GND));
defparam syncreset_ctrl_X60_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y2_N1
alta_syncctrl syncload_ctrl_X60_Y2(.Din(), .Dout(SyncLoad_X60_Y2_VCC));
defparam syncload_ctrl_X60_Y2.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|always5~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|always5~1 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|always5~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|always5~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always5~1 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N10
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[1] (
// Location: LCCOMB_X60_Y3_N10
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[1] (
alta_slice \macro_inst|u_ahb2apb|prdata[1] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [1]),
	.B(\macro_inst|u_apb_mux|pr_select [0]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata [1]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [1]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [1]));
defparam \macro_inst|u_ahb2apb|prdata[1] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[1] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[1] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[1] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector6~3 (
// Location: FF_X60_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[6] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[6] (
	.A(\macro_inst|u_uart[0]|u_regs|ibrd [6]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\macro_inst|u_uart[0]|u_regs|Selector6~2_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector6~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [6]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .mask = 16'hF800;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[6] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N14
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[13] (
// Location: LCCOMB_X60_Y3_N14
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[13] (
alta_slice \macro_inst|u_ahb2apb|prdata[13] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [13]),
	.B(\macro_inst|u_apb_mux|pr_select [0]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata [13]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [13]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [13]));
defparam \macro_inst|u_ahb2apb|prdata[13] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[13] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[13] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[13] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[13] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[13] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N16
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[0] (
// Location: LCCOMB_X60_Y3_N16
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[0] (
alta_slice \macro_inst|u_ahb2apb|prdata[0] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [0]),
	.B(\macro_inst|u_apb_mux|pr_select [1]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata [0]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [0]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [0]));
defparam \macro_inst|u_ahb2apb|prdata[0] .mask = 16'hECA0;
defparam \macro_inst|u_ahb2apb|prdata[0] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[0] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[0] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[0] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N18
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[5] (
// Location: LCCOMB_X60_Y3_N18
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[5] (
alta_slice \macro_inst|u_ahb2apb|prdata[5] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [5]),
	.B(\macro_inst|u_apb_mux|pr_select [0]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata [5]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [5]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [5]));
defparam \macro_inst|u_ahb2apb|prdata[5] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[5] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[5] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[5] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[5] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N2
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[7] (
// Location: LCCOMB_X60_Y3_N2
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[7] (
alta_slice \macro_inst|u_ahb2apb|prdata[7] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [7]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata [7]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [7]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [7]));
defparam \macro_inst|u_ahb2apb|prdata[7] .mask = 16'hECA0;
defparam \macro_inst|u_ahb2apb|prdata[7] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[7] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[7] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[7] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N20
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[15] (
// Location: LCCOMB_X60_Y3_N20
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[15] (
alta_slice \macro_inst|u_ahb2apb|prdata[15] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [15]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata [15]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [15]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [15]));
defparam \macro_inst|u_ahb2apb|prdata[15] .mask = 16'hECA0;
defparam \macro_inst|u_ahb2apb|prdata[15] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[15] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[15] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[15] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N22
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[2] (
// Location: LCCOMB_X60_Y3_N22
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[2] (
alta_slice \macro_inst|u_ahb2apb|prdata[2] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata [2]),
	.B(\macro_inst|u_apb_mux|pr_select [1]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata [2]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [2]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [2]));
defparam \macro_inst|u_ahb2apb|prdata[2] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[2] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[2] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[2] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N24
// alta_lcell_comb \macro_inst|u_ahb2apb|apb_pdone (
alta_slice \macro_inst|u_ahb2apb|apb_pdone (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|psel~q ),
	.C(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.D(\macro_inst|u_ahb2apb|penable~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_ahb2apb|apb_pdone~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_ahb2apb|apb_pdone .mask = 16'hC000;
defparam \macro_inst|u_ahb2apb|apb_pdone .mode = "logic";
defparam \macro_inst|u_ahb2apb|apb_pdone .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apb_pdone .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apb_pdone .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|apb_pdone .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|apb_pdone .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|apb_pdone .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|apb_pdone .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|apb_pdone .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[13] (
// Location: LCCOMB_X60_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata~19 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[13] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_uart[0]|u_regs|ibrd [13]),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata~19_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [13]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[13] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|always5~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|always5~0 (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|always5~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .mask = 16'h0080;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always5~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N30
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[6] (
// Location: LCCOMB_X60_Y3_N30
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[6] (
alta_slice \macro_inst|u_ahb2apb|prdata[6] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [6]),
	.B(\macro_inst|u_apb_mux|pr_select [1]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata [6]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [6]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [6]));
defparam \macro_inst|u_ahb2apb|prdata[6] .mask = 16'hECA0;
defparam \macro_inst|u_ahb2apb|prdata[6] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[6] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[6] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[6] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N4
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[14] (
// Location: LCCOMB_X60_Y3_N4
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[14] (
alta_slice \macro_inst|u_ahb2apb|prdata[14] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata [14]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata [14]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [14]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [14]));
defparam \macro_inst|u_ahb2apb|prdata[14] .mask = 16'hEAC0;
defparam \macro_inst|u_ahb2apb|prdata[14] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[14] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[14] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[14] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[14] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[15] (
// Location: LCCOMB_X60_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata~21 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[15] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_uart[0]|u_regs|ibrd [15]),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata~21_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [15]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[15] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y3_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[14] (
// Location: LCCOMB_X60_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata~20 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[14] (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_uart[0]|u_regs|ibrd [14]),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata~20_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [14]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[14] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y3_N0
alta_clkenctrl clken_ctrl_X60_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_ahb2apb|apb_pdone~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X60_Y3_SIG_SIG ));
defparam clken_ctrl_X60_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y3_N0
alta_asyncctrl asyncreset_ctrl_X60_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y3_SIG ));
defparam asyncreset_ctrl_X60_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y3_N1
alta_clkenctrl clken_ctrl_X60_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y3_SIG_SIG ));
defparam clken_ctrl_X60_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y3_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X60_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|always2~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|always2~0 (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .mask = 16'h4000;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|always2~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~16_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~14 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~14 (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\macro_inst|u_uart[1]|u_regs|Selector7~12_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector7~9_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .mask = 16'hF870;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~8 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~8 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|ibrd [5]),
	.C(\macro_inst|u_uart[1]|u_regs|Selector7~7_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .mask = 16'hD8AA;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~5 (
// Location: FF_X60_Y4_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_ahb2apb|paddr [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_dma_en [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0_combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(SyncReset_X60_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_dma_en[3]~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_dma_en [5]));
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .mask = 16'h0088;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_dma_en[5] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[15] (
// Location: LCCOMB_X60_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_prdata~8 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[15] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|ibrd [15]),
	.C(\macro_inst|u_ahb2apb|paddr [2]),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_prdata~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [15]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[15] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector9~5 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [3]),
	.C(\macro_inst|u_uart[1]|u_regs|Selector9~4_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .mask = 16'hCAF0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector9~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~13 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~13 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector7~8_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|fbrd [5]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector7~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .mask = 16'hDC98;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector9~6 (
// Location: FF_X60_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[3] (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_uart[0]|u_regs|Selector9~10_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|status_reg [0]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector9~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector9~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [3]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .mask = 16'hC480;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[14] (
// Location: LCCOMB_X60_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_prdata~7 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[14] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|ibrd [14]),
	.C(\macro_inst|u_ahb2apb|paddr [2]),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_prdata~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [14]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[14] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .mask = 16'h5575;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~15 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~15 (
// Location: FF_X60_Y4_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[1] (
	.A(\macro_inst|u_ahb2apb|paddr [7]),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~14_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~15_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [1]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .mask = 16'h1100;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~15 (
// Location: FF_X60_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[5] (
	.A(\macro_inst|u_ahb2apb|paddr [7]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [6]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector7~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~15_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [5]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .mask = 16'h0100;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 (
	.A(\macro_inst|u_ahb2apb|paddr [6]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [10]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~14 (
// Location: FF_X60_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] (
	.A(\macro_inst|u_uart[1]|u_regs|tx_dma_en [4]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~9_combout ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector11~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_dma_en [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0_combout_X60_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ),
	.SyncReset(SyncReset_X60_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y4_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~14_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_dma_en [5]));
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .mask = 16'hBBC0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_dma_en[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~12 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~12 (
	.A(\macro_inst|u_uart[1]|u_regs|Selector7~11_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|status_reg [2]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector7~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .mask = 16'hAC0C;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~12 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y4_N0
alta_clkenctrl clken_ctrl_X60_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_dma_en[5]~0_combout_X60_Y4_SIG_SIG ));
defparam clken_ctrl_X60_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y4_N0
alta_asyncctrl asyncreset_ctrl_X60_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y4_SIG ));
defparam asyncreset_ctrl_X60_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y4_N1
alta_clkenctrl clken_ctrl_X60_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y4_SIG_SIG ));
defparam clken_ctrl_X60_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y4_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y4_N0
alta_syncctrl syncreset_ctrl_X60_Y4(.Din(), .Dout(SyncReset_X60_Y4_GND));
defparam syncreset_ctrl_X60_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y4_N1
alta_syncctrl syncload_ctrl_X60_Y4(.Din(), .Dout(SyncLoad_X60_Y4_VCC));
defparam syncload_ctrl_X60_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y5_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~14 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~14 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Selector8~9_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector8~12_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .mask = 16'hF780;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector10~5 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [2]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector10~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .mask = 16'hCFA0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector10~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~8 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~8 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|Selector12~6_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector12~7_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .mask = 16'h55D8;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Equal2~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|Equal2~1 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_ahb2apb|paddr [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Equal2~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~11 (
// Location: FF_X60_Y5_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[7] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[7] (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector5~10_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [7]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .mask = 16'h0300;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~5 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector10~5 (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[0]|u_regs|fbrd [2]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector10~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .mask = 16'hCFA0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector10~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~13 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~13 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector8~8_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|fbrd [4]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector8~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~13_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .mask = 16'hDC98;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~13 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~6 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~6 (
	.A(\macro_inst|u_uart[0]|u_regs|uart_en~q ),
	.B(\macro_inst|u_ahb2apb|paddr [2]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .mask = 16'h0200;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector6~1 (
// Location: FF_X60_Y5_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[6] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[6] (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_uart[1]|u_regs|ibrd [6]),
	.C(\macro_inst|u_uart[0]|u_regs|Selector6~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [6]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .mask = 16'hF080;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector5~10 (
// Location: FF_X60_Y5_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[7] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[7] (
	.A(\macro_inst|u_uart[0]|u_regs|ibrd [7]),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector5~8_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector5~9_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector5~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [7]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .mask = 16'h08C0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector10~6 (
// Location: FF_X60_Y5_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[2] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~12_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector10~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector10~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [2]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~15 (
// Location: FF_X60_Y5_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[4] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\macro_inst|u_ahb2apb|paddr [7]),
	.D(\macro_inst|u_uart[1]|u_regs|Selector8~13_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~15_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [4]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .mask = 16'h0100;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y5_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[13] (
// Location: LCCOMB_X60_Y5_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_prdata~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[13] (
	.A(\macro_inst|u_uart[1]|u_regs|ibrd [13]),
	.B(\macro_inst|u_ahb2apb|paddr [2]),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_prdata~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [13]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[13] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~8 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~8 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|ibrd [4]),
	.C(\macro_inst|u_uart[1]|u_regs|Selector8~7_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .mask = 16'hD8AA;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector10~6 (
// Location: FF_X60_Y5_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[2] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[2] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~12_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector10~5_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector10~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [2]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y5_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector6~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector6~0 (
	.A(\macro_inst|u_ahb2apb|paddr [5]),
	.B(\macro_inst|u_ahb2apb|paddr [2]),
	.C(\macro_inst|u_uart[1]|u_regs|Equal2~1_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .mask = 16'h9010;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector6~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y5_N0
alta_clkenctrl clken_ctrl_X60_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ));
defparam clken_ctrl_X60_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y5_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y5_N0
alta_asyncctrl asyncreset_ctrl_X60_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y5_SIG ));
defparam asyncreset_ctrl_X60_Y5_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y5_N1
alta_clkenctrl clken_ctrl_X60_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X60_Y5_SIG_SIG ));
defparam clken_ctrl_X60_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y5_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X60_Y6_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector1~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector1~0 (
	.A(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [0]),
	.B(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [1]),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~28 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~28 (
	.A(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [5]),
	.B(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [5]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_idle~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_complete~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~28_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~28 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~18 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~18 (
	.A(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [3]),
	.B(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [3]),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_complete~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_idle~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~8 (
// Location: FF_X60_Y6_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_idle~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_complete~q ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector0~0 (
// Location: FF_X60_Y6_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [1]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .mask = 16'hAAD8;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~4 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_rx[0]|rx_idle~q ),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_idle~q ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .mask = 16'hFA44;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~4 (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_tx[2]|tx_complete~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_complete~q ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .mask = 16'hE4AA;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~4 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y6_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[11] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_idle_ie[1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~11 (
// Location: FF_X60_Y6_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [3]),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [1]));
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .mask = 16'hDDF5;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~6 (
	.A(\macro_inst|u_uart[1]|u_rx[4]|rx_idle~q ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_idle~q ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~3 (
// Location: FF_X60_Y6_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_complete~q ),
	.B(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [0]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[1]|u_rx[0]|rx_idle~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X60_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ),
	.SyncReset(SyncReset_X60_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [0]));
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[0] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y6_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~5 (
	.A(\macro_inst|u_uart[1]|u_rx[1]|rx_idle~q ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector8~4_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_idle~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .mask = 16'hEC2C;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~7 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~7 (
	.A(\macro_inst|u_uart[1]|u_regs|rx_reg [4]),
	.B(\macro_inst|u_uart[1]|u_regs|Selector8~5_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector8~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .mask = 16'hFC0A;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~5 (
	.A(\macro_inst|u_uart[1]|u_tx[0]|tx_complete~q ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector7~4_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|tx_complete~q ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .mask = 16'hCCE2;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~6 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~6 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~2_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_complete~q ),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_complete~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .mask = 16'hEA4A;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y6_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~7 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector7~7 (
	.A(\macro_inst|u_uart[1]|u_regs|rx_reg [5]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~1_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector7~5_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector7~6_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .mask = 16'hFC22;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector7~7 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X60_Y6_N0
alta_clkenctrl clken_ctrl_X60_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[1]~8_combout_X60_Y6_SIG_SIG ));
defparam clken_ctrl_X60_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y6_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y6_N0
alta_asyncctrl asyncreset_ctrl_X60_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y6_SIG ));
defparam asyncreset_ctrl_X60_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y6_N1
alta_clkenctrl clken_ctrl_X60_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[0]~15_combout_X60_Y6_SIG_SIG ));
defparam clken_ctrl_X60_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y6_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X60_Y6_N0
alta_syncctrl syncreset_ctrl_X60_Y6(.Din(), .Dout(SyncReset_X60_Y6_GND));
defparam syncreset_ctrl_X60_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y6_N1
alta_syncctrl syncload_ctrl_X60_Y6(.Din(), .Dout(SyncLoad_X60_Y6_VCC));
defparam syncload_ctrl_X60_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector3~2 (
// Location: FF_X60_Y7_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|break_error_ie[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|break_error_ie[3] (
	.A(\macro_inst|u_uart[1]|u_regs|break_error_ie [2]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector3~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|break_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector3~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|break_error_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .mask = 16'hBBC0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~15 (
// Location: FF_X60_Y7_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [3]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~15_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y7_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|always2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_parity~q ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .mask = 16'h0880;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y7_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] (
// Location: LCCOMB_X60_Y7_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~16 (
alta_slice \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|framing_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|parity_error_ie [3]),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[1]|u_rx[3]|parity_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|framing_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~16_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|framing_error_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .mask = 16'hECA0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|interrupts[3] (
// Location: LCCOMB_X60_Y7_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~19 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts[3] (
	.A(\macro_inst|u_uart[1]|u_regs|interrupts~15_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|interrupts~16_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|interrupts~17_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|interrupts~18_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|interrupts [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~19_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|interrupts [3]));
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[3] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y7_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|parity_error (
// Location: LCCOMB_X60_Y7_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|parity_error~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|parity_error (
	.A(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_sample~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|parity_error~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|parity_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|parity_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector0~0 (
// Location: FF_X60_Y7_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .mask = 16'hAAFA;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y7_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector1~1 (
// Location: FF_X60_Y7_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [2]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector1~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] (
// Location: LCCOMB_X60_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|tx_write [3]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .mask = 16'h00CC;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_complete (
// Location: LCCOMB_X60_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_complete~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_complete (
	.A(\macro_inst|u_uart[1]|u_regs|clear_flags[3]~11_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_complete~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .mask = 16'h00DC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_complete (
// Location: LCCOMB_X60_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_complete~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_complete (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_complete~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .mask = 16'h4454;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_complete .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y7_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector4~1 (
// Location: FF_X60_Y7_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] (
	.A(\macro_inst|u_uart[1]|u_regs|parity_error_ie [2]),
	.B(\macro_inst|u_ahb2apb|paddr [9]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|parity_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|parity_error_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y7_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_idle (
// Location: LCCOMB_X60_Y7_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_idle~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_idle (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|always8~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_idle~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~17 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~17 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|break_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [3]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|overrun_error~q ),
	.D(\macro_inst|u_uart[1]|u_regs|break_error_ie [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~17_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~17 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y7_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] (
// Location: LCCOMB_X60_Y7_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_regs|tx_write [3]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .mask = 16'h0CAC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector2~1 (
// Location: FF_X60_Y7_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] (
	.A(\macro_inst|u_uart[1]|u_regs|Selector2~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [2]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_ahb2apb|paddr [9]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ),
	.SyncReset(SyncReset_X60_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector2~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [3]));
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .mask = 16'hE4AA;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[3] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X60_Y7_N0
alta_clkenctrl clken_ctrl_X60_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[3]~10_combout_X60_Y7_SIG_SIG ));
defparam clken_ctrl_X60_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y7_N0
alta_asyncctrl asyncreset_ctrl_X60_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y7_SIG ));
defparam asyncreset_ctrl_X60_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y7_N1
alta_clkenctrl clken_ctrl_X60_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y7_SIG_VCC ));
defparam clken_ctrl_X60_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y7_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X60_Y7_N0
alta_syncctrl syncreset_ctrl_X60_Y7(.Din(), .Dout(SyncReset_X60_Y7_GND));
defparam syncreset_ctrl_X60_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y7_N1
alta_syncctrl syncload_ctrl_X60_Y7(.Din(), .Dout(SyncLoad_X60_Y7_VCC));
defparam syncload_ctrl_X60_Y7.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~22 (
// Location: FF_X60_Y8_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] (
	.A(\macro_inst|u_uart[1]|u_regs|break_error_ie [4]),
	.B(\macro_inst|u_uart[1]|u_rx[4]|overrun_error~q ),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|break_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~22_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 (
	.A(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~11_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~20 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~20 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ),
	.C(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [4]),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~20_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~20 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|overrun_error (
// Location: LCCOMB_X60_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|overrun_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|overrun_error (
	.A(\macro_inst|u_uart[1]|u_rx[4]|Selector0~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|overrun_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|overrun_error .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] (
// Location: LCCOMB_X60_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~11 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~11_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .mask = 16'h4400;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~9 (
// Location: FF_X60_Y8_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [5]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|break_error_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|break_error_ie[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[9] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|break_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|break_error_ie[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|break_error_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~23 (
// Location: FF_X60_Y8_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [4]),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_complete~q ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_idle~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~23_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[4] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|uart_en (
// Location: LCCOMB_X60_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|uart_en~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|uart_en (
	.A(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.B(\rv32.mem_ahb_hwdata[0] ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|always6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|uart_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|uart_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|uart_en~q ));
defparam \macro_inst|u_uart[1]|u_regs|uart_en .mask = 16'hD8F0;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|uart_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|uart_en .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[4]|rx_idle (
// Location: LCCOMB_X60_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[4]|rx_idle~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[4]|rx_idle (
	.A(\macro_inst|u_uart[1]|u_rx[4]|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[4]|rx_idle~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[4]|rx_idle~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[4]|rx_idle~q ));
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .mask = 16'hEAEA;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[4]|rx_idle .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector7~9 (
// Location: FF_X60_Y8_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] (
	.A(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [5]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector7~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[4] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y8_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|overrun_error (
// Location: LCCOMB_X60_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|overrun_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|overrun_error (
	.A(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|overrun_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|overrun_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|overrun_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|overrun_error .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|framing_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|framing_error_ie[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|framing_error_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_complete (
// Location: LCCOMB_X60_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_complete~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_complete (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_regs|clear_flags[4]~15_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_complete~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_complete~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_complete~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .mask = 16'h5540;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_complete .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y8_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|interrupts[4] (
// Location: LCCOMB_X60_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~24 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts[4] (
	.A(\macro_inst|u_uart[1]|u_regs|interrupts~20_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|interrupts~23_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|interrupts~21_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|interrupts~22_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|interrupts [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~24_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|interrupts [4]));
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~21 (
// Location: FF_X60_Y8_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] (
	.A(\macro_inst|u_uart[1]|u_rx[4]|framing_error~q ),
	.B(\macro_inst|u_uart[1]|u_regs|framing_error_ie [4]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_rx[4]|parity_error~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|parity_error_ie [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ),
	.SyncReset(SyncReset_X60_Y8_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y8_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~21_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|parity_error_ie [4]));
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X60_Y8_N0
alta_clkenctrl clken_ctrl_X60_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[4]~12_combout_X60_Y8_SIG_SIG ));
defparam clken_ctrl_X60_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y8_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y8_N0
alta_asyncctrl asyncreset_ctrl_X60_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y8_SIG ));
defparam asyncreset_ctrl_X60_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y8_N1
alta_clkenctrl clken_ctrl_X60_Y8_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y8_SIG_VCC ));
defparam clken_ctrl_X60_Y8_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y8_N1.ClkEnMux = 2'b01;

// Location: SYNCCTRL_X60_Y8_N0
alta_syncctrl syncreset_ctrl_X60_Y8(.Din(), .Dout(SyncReset_X60_Y8_GND));
defparam syncreset_ctrl_X60_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y8_N1
alta_syncctrl syncload_ctrl_X60_Y8(.Din(), .Dout(SyncLoad_X60_Y8_VCC));
defparam syncload_ctrl_X60_Y8.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X60_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|Add1~0 (
// Location: FF_X60_Y9_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] (
	.A(\macro_inst|u_uart[1]|u_rx[2]|rx_in [4]),
	.B(\macro_inst|u_uart[1]|u_rx[2]|rx_in [2]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(SyncReset_X60_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_in [3]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .mask = 16'h22BB;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X60_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|always6~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|always6~1 (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_in [3]),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_in [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .mask = 16'h4054;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector5~4 (
// Location: FF_X60_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|uart_txd (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|uart_txd (
	.A(\macro_inst|u_uart[1]|u_tx[3]|Selector5~2_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|uart_txd~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .mask = 16'h0404;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|uart_txd .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_parity (
// Location: LCCOMB_X60_Y9_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_parity (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X60_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_parity~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] (
// Location: LCCOMB_X60_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|rx_read [5]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .mask = 16'h3F30;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|break_error (
// Location: LCCOMB_X60_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|break_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|break_error (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|always11~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|break_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|break_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|break_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|break_error .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] (
// Location: LCCOMB_X60_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_in [4]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|framing_error (
// Location: LCCOMB_X60_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|framing_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|framing_error (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|framing_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|framing_error~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|framing_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .mask = 16'h44F4;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|framing_error .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_parity (
// Location: LCCOMB_X60_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_parity (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_parity~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X60_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_parity~q ));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .mask = 16'h553C;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X60_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always11~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|always11~2 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|always11~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always11~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector2~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always11~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always11~2 .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] (
// Location: LCCOMB_X60_Y9_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_in[2]~feeder (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[3]|rx_in [1]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_in[2]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_in [2]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .mask = 16'hF0F0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[2] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] (
// Location: LCCOMB_X60_Y9_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[3]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[3]|rx_in [4]));
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[3]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] (
// Location: LCCOMB_X60_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[2]|rx_in[4]~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[2]|rx_in [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_in [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[2]|rx_in[4]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_in [4]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[4] .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_parity (
// Location: LCCOMB_X60_Y9_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_parity (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ),
	.AsyncReset(AsyncReset_X60_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_parity~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .mask = 16'h4774;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X60_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] (
// Location: LCCOMB_X60_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|Add1~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_in [2]),
	.B(\macro_inst|u_uart[1]|u_rx[3]|rx_in [3]),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_in [2]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_in [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_in [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(SyncReset_X60_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|Add1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_in [3]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .mask = 16'h7711;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[3] .SyncLoadMux = 2'b01;
// Location: FF_X60_Y9_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] (
// Location: LCCOMB_X60_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] (
	.A(\macro_inst|u_uart[1]|u_rx[3]|rx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[2]|rx_in [1]),
	.D(\macro_inst|u_uart[1]|u_rx[3]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[2]|rx_in [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ),
	.SyncReset(SyncReset_X60_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X60_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[3]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[2]|rx_in [2]));
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .mask = 16'hFFAA;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[2]|rx_in[2] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X60_Y9_N0
alta_clkenctrl clken_ctrl_X60_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_baud|baud16~q_X60_Y9_SIG_SIG ));
defparam clken_ctrl_X60_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X60_Y9_N0
alta_asyncctrl asyncreset_ctrl_X60_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X60_Y9_SIG ));
defparam asyncreset_ctrl_X60_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X60_Y9_N1
alta_clkenctrl clken_ctrl_X60_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X60_Y9_SIG_VCC ));
defparam clken_ctrl_X60_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X60_Y9_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X60_Y9_N1
alta_asyncctrl asyncreset_ctrl_X60_Y9_N1(.Din(), .Dout(AsyncReset_X60_Y9_GND));
defparam asyncreset_ctrl_X60_Y9_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y9_N0
alta_syncctrl syncreset_ctrl_X60_Y9(.Din(), .Dout(SyncReset_X60_Y9_GND));
defparam syncreset_ctrl_X60_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X60_Y9_N1
alta_syncctrl syncload_ctrl_X60_Y9(.Din(), .Dout(SyncLoad_X60_Y9_VCC));
defparam syncload_ctrl_X60_Y9.SyncCtrlMux = 2'b01;
// Location: FF_X61_Y10_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_parity (
// Location: LCCOMB_X61_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_parity (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_parity~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(AsyncReset_X61_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_parity~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .mask = 16'h14BE;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_parity .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt (
// Location: LCCOMB_X61_Y10_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(AsyncReset_X61_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .mask = 16'hEAEA;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] (
// Location: LCCOMB_X61_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|tx_write [4]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .mask = 16'h2F20;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START (
// Location: LCCOMB_X61_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .mask = 16'hCCEC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_stop (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|always6~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|always6~0 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] (
// Location: LCCOMB_X61_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout__SyncReset_X61_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X61_Y10_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|always6~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|always6~1 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_tx[5]|always6~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|always6~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|always6~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|tx_write [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|comb~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|comb~1 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .mask = 16'h5000;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|comb~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector0~0 (
// Location: FF_X61_Y10_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .mask = 16'hFF30;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|fifo_rden (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|fifo_rden (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|comb~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .mask = 16'hF050;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y10_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .mask = 16'h1320;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y10_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] (
// Location: LCCOMB_X61_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout__SyncReset_X61_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y10_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] (
// Location: LCCOMB_X61_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout__SyncReset_X61_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y10_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] (
// Location: LCCOMB_X61_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout__SyncReset_X61_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .mask = 16'h3C3C;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X61_Y10_N0
alta_clkenctrl clken_ctrl_X61_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y10_SIG_VCC ));
defparam clken_ctrl_X61_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y10_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y10_N0
alta_asyncctrl asyncreset_ctrl_X61_Y10_N0(.Din(), .Dout(AsyncReset_X61_Y10_GND));
defparam asyncreset_ctrl_X61_Y10_N0.AsyncCtrlMux = 2'b00;

// Location: ASYNCCTRL_X61_Y10_N1
alta_asyncctrl asyncreset_ctrl_X61_Y10_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y10_SIG ));
defparam asyncreset_ctrl_X61_Y10_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X61_Y10_N0
alta_syncctrl syncreset_ctrl_X61_Y10(.Din(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout ), .Dout(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout__SyncReset_X61_Y10_SIG ));
defparam syncreset_ctrl_X61_Y10.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X61_Y10_N1
alta_syncctrl syncload_ctrl_X61_Y10(.Din(), .Dout(SyncLoad_X61_Y10_GND));
defparam syncload_ctrl_X61_Y10.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X61_Y11_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|parity_error~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .mask = 16'h2080;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector1~0 (
// Location: FF_X61_Y11_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Selector2~4_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector1~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .mask = 16'h00DC;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y11_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY (
// Location: LCCOMB_X61_Y11_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector3~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector2~6 (
// Location: FF_X61_Y11_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Selector2~5_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector2~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Selector2~3_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector2~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .mask = 16'h3222;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Selector4~3_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector3~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Selector3~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector4~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector4~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .mask = 16'hFEFC;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always8~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|always8~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always8~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always8~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y11_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP (
// Location: LCCOMB_X61_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Selector3~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector4~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .mask = 16'hEEF0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector4~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .mask = 16'hAA00;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .mask = 16'h44CC;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector4~1 (
// Location: FF_X61_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_bit (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always2~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ),
	.SyncReset(SyncReset_X61_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .mask = 16'h3000;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_bit .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|Add1~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Selector2~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector2~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .mask = 16'h00C8;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~5 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector3~0 (
// Location: FF_X61_Y11_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Selector0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ),
	.SyncReset(SyncReset_X61_Y11_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y11_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .mask = 16'hCC00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_IDLE .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y11_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|always3~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Selector2~3_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector2~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .mask = 16'hFE00;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector2~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y11_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_PARITY~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~3 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y11_N0
alta_clkenctrl clken_ctrl_X61_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y11_SIG_VCC ));
defparam clken_ctrl_X61_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y11_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y11_N0
alta_asyncctrl asyncreset_ctrl_X61_Y11_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y11_SIG ));
defparam asyncreset_ctrl_X61_Y11_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X61_Y11_N0
alta_syncctrl syncreset_ctrl_X61_Y11(.Din(), .Dout(SyncReset_X61_Y11_GND));
defparam syncreset_ctrl_X61_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y11_N1
alta_syncctrl syncload_ctrl_X61_Y11(.Din(), .Dout(SyncLoad_X61_Y11_VCC));
defparam syncload_ctrl_X61_Y11.SyncCtrlMux = 2'b01;
// Location: FF_X61_Y12_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] (
// Location: LCCOMB_X61_Y12_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [6]),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5]~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] (
// Location: LCCOMB_X61_Y12_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(SyncReset_X61_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y12_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] (
// Location: LCCOMB_X61_Y12_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [1]),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] (
// Location: LCCOMB_X61_Y12_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] (
// Location: LCCOMB_X61_Y12_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][3]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] (
// Location: LCCOMB_X61_Y12_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][7]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] (
// Location: LCCOMB_X61_Y12_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][2]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] (
// Location: LCCOMB_X61_Y12_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][6]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] (
// Location: LCCOMB_X61_Y12_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [5]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|fifo[1][4]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y12_N0
alta_clkenctrl clken_ctrl_X61_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout_X61_Y12_SIG_SIG ));
defparam clken_ctrl_X61_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y12_N0
alta_asyncctrl asyncreset_ctrl_X61_Y12_N0(.Din(), .Dout(AsyncReset_X61_Y12_GND));
defparam asyncreset_ctrl_X61_Y12_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X61_Y12_N1
alta_clkenctrl clken_ctrl_X61_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg[3]~1_combout_X61_Y12_SIG_SIG ));
defparam clken_ctrl_X61_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y12_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y12_N1
alta_asyncctrl asyncreset_ctrl_X61_Y12_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y12_SIG ));
defparam asyncreset_ctrl_X61_Y12_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X61_Y12_N0
alta_syncctrl syncreset_ctrl_X61_Y12(.Din(), .Dout(SyncReset_X61_Y12_GND));
defparam syncreset_ctrl_X61_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y12_N1
alta_syncctrl syncload_ctrl_X61_Y12(.Din(), .Dout(SyncLoad_X61_Y12_VCC));
defparam syncload_ctrl_X61_Y12.SyncCtrlMux = 2'b01;
// Location: FF_X61_Y1_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_cnt[0] (
// Location: LCCOMB_X61_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|f_cnt[0]~6 (
alta_slice \macro_inst|u_uart[0]|u_baud|f_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_baud|f_cnt[0]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|f_cnt[0]~7 ),
	.Q(\macro_inst|u_uart[0]|u_baud|f_cnt [0]));
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_cnt[5] (
// Location: LCCOMB_X61_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|f_cnt[5]~16 (
alta_slice \macro_inst|u_uart[0]|u_baud|f_cnt[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [5]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|f_cnt[4]~15 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_baud|f_cnt[5]~16_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_baud|f_cnt [5]));
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .mask = 16'h3C3C;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[5] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X61_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|always6~1 (
// Location: FF_X61_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_bit (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [3]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|always6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt (
// Location: LCCOMB_X61_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(AsyncReset_X61_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .mask = 16'hFCF0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_write[1] (
// Location: LCCOMB_X61_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|tx_write~1 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_write[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[1]~13_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_write [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_write~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_write [1]));
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .mask = 16'hC000;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|Selector0~0 (
// Location: FF_X61_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .mask = 16'hCCFC;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y1_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_cnt[1] (
// Location: LCCOMB_X61_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|f_cnt[1]~8 (
alta_slice \macro_inst|u_uart[0]|u_baud|f_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|f_cnt[0]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_baud|f_cnt[1]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|f_cnt[1]~9 ),
	.Q(\macro_inst|u_uart[0]|u_baud|f_cnt [1]));
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] (
// Location: LCCOMB_X61_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_regs|tx_write [1]),
	.B(\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .mask = 16'h3A0A;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|fifo_rden (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|fifo_rden (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_IDLE~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .mask = 16'hF030;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y1_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START (
// Location: LCCOMB_X61_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .mask = 16'hBAAA;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .mask = 16'h1230;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|comb~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|comb~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_stop_cnt~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|comb~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .mask = 16'h3000;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|comb~1 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y1_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req (
// Location: LCCOMB_X61_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req (
	.A(\rv32.ext_dma_DMACCLR[3] ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|tx_dma_en [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_dma_req~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .mask = 16'h5100;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_dma_req .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_cnt[2] (
// Location: LCCOMB_X61_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|f_cnt[2]~10 (
alta_slice \macro_inst|u_uart[0]|u_baud|f_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|f_cnt[1]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_baud|f_cnt[2]~10_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|f_cnt[2]~11 ),
	.Q(\macro_inst|u_uart[0]|u_baud|f_cnt [2]));
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_cnt[3] (
// Location: LCCOMB_X61_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|f_cnt[3]~12 (
alta_slice \macro_inst|u_uart[0]|u_baud|f_cnt[3] (
	.A(\macro_inst|u_uart[0]|u_baud|f_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|f_cnt[2]~11 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_baud|f_cnt[3]~12_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|f_cnt[3]~13 ),
	.Q(\macro_inst|u_uart[0]|u_baud|f_cnt [3]));
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y1_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_baud|f_cnt[4] (
// Location: LCCOMB_X61_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_baud|f_cnt[4]~14 (
alta_slice \macro_inst|u_uart[0]|u_baud|f_cnt[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_baud|f_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_baud|f_cnt[3]~13 ),
	.Qin(\macro_inst|u_uart[0]|u_baud|f_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_baud|f_cnt[4]~14_combout ),
	.Cout(\macro_inst|u_uart[0]|u_baud|f_cnt[4]~15 ),
	.Q(\macro_inst|u_uart[0]|u_baud|f_cnt [4]));
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[0]|u_baud|f_cnt[4] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X61_Y1_N0
alta_clkenctrl clken_ctrl_X61_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y1_SIG_VCC ));
defparam clken_ctrl_X61_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y1_N0
alta_asyncctrl asyncreset_ctrl_X61_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y1_SIG ));
defparam asyncreset_ctrl_X61_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: ASYNCCTRL_X61_Y1_N1
alta_asyncctrl asyncreset_ctrl_X61_Y1_N1(.Din(), .Dout(AsyncReset_X61_Y1_GND));
defparam asyncreset_ctrl_X61_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y1_N0
alta_syncctrl syncreset_ctrl_X61_Y1(.Din(\macro_inst|u_uart[0]|u_regs|uart_en~q ), .Dout(\macro_inst|u_uart[0]|u_regs|uart_en~q__SyncReset_X61_Y1_INV ));
defparam syncreset_ctrl_X61_Y1.SyncCtrlMux = 2'b11;

// Location: SYNCCTRL_X61_Y1_N1
alta_syncctrl syncload_ctrl_X61_Y1(.Din(), .Dout(SyncLoad_X61_Y1_GND));
defparam syncload_ctrl_X61_Y1.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X61_Y2_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~9 (
// Location: FF_X61_Y2_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[3] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[3] (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_uart[0]|u_regs|Selector9~10_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|status_reg [0]),
	.D(\macro_inst|u_uart[0]|u_regs|Selector9~8_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~9_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [3]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .mask = 16'hC480;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~11 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~11 (
	.A(\macro_inst|u_uart[0]|u_regs|ibrd [4]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector8~6_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector8~10_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~11_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .mask = 16'hF838;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~11 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[5] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|ibrd[5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [5]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~12 (
// Location: FF_X61_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|apb_prdata[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[4] (
	.A(\macro_inst|u_ahb2apb|paddr [7]),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|Selector8~11_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|apb_prdata [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~12_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|apb_prdata [4]));
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .mask = 16'h0100;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~10 (
// Location: FF_X61_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[4] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[4] (
	.A(\macro_inst|u_uart[0]|u_regs|Selector9~2_combout ),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_ahb2apb|paddr [7]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(SyncReset_X61_Y2_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y2_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [4]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .mask = 16'h0022;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[4] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y2_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~8 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector9~8 (
	.A(\macro_inst|u_ahb2apb|paddr [3]),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_stp2~q ),
	.C(\macro_inst|u_uart[0]|u_regs|Selector9~7_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|fbrd [3]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~8_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .mask = 16'hF858;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~8 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~17 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~17 (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|paddr [6]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [7]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~17_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .mask = 16'h0003;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~17 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector4~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector4~2 (
	.A(\macro_inst|u_uart[0]|u_regs|ibrd [8]),
	.B(\macro_inst|u_uart[0]|u_regs|parity_error_ie [4]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .mask = 16'hF0CA;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector4~2 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[9] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[9] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[9] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|ibrd[9]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [9]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|interrupts~22 (
alta_slice \macro_inst|u_uart[0]|u_regs|interrupts~22 (
	.A(\macro_inst|u_uart[0]|u_rx[4]|break_error~q ),
	.B(\macro_inst|u_uart[0]|u_rx[4]|overrun_error~q ),
	.C(\macro_inst|u_uart[0]|u_regs|overrun_error_ie [4]),
	.D(\macro_inst|u_uart[0]|u_regs|break_error_ie [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|interrupts~22_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|interrupts~22 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[7] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|ibrd[7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [7]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[7] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector3~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector3~2 (
	.A(\macro_inst|u_uart[0]|u_regs|break_error_ie [4]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|ibrd [9]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .mask = 16'hCCB8;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector8~6 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector8~6 (
	.A(\macro_inst|u_uart[0]|u_regs|Selector8~5_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~5_combout ),
	.C(\macro_inst|u_uart[0]|u_regs|fbrd [4]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector8~6_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .mask = 16'h22FC;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector8~6 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector7~18 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector7~18 (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_uart[0]|u_regs|fbrd [5]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_uart[0]|u_regs|ibrd [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector7~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .mask = 16'hCDC8;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector7~18 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_regs|tx_write [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .mask = 16'h0F00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|ibrd[12] (
alta_slice \macro_inst|u_uart[0]|u_regs|ibrd[12] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[12] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|ibrd [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X61_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|ibrd[12]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|ibrd [12]));
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|ibrd[12] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y2_N0
alta_clkenctrl clken_ctrl_X61_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|apb_read1~combout_X61_Y2_SIG_SIG ));
defparam clken_ctrl_X61_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y2_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y2_N0
alta_asyncctrl asyncreset_ctrl_X61_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y2_SIG ));
defparam asyncreset_ctrl_X61_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y2_N1
alta_clkenctrl clken_ctrl_X61_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always1~0_combout_X61_Y2_SIG_SIG ));
defparam clken_ctrl_X61_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X61_Y2_N0
alta_syncctrl syncreset_ctrl_X61_Y2(.Din(), .Dout(SyncReset_X61_Y2_GND));
defparam syncreset_ctrl_X61_Y2.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y2_N1
alta_syncctrl syncload_ctrl_X61_Y2(.Din(), .Dout(SyncLoad_X61_Y2_VCC));
defparam syncload_ctrl_X61_Y2.SyncCtrlMux = 2'b01;
// Location: FF_X61_Y3_N0
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[12] (
// Location: LCCOMB_X61_Y3_N0
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[12] (
alta_slice \macro_inst|u_ahb2apb|prdata[12] (
	.A(\macro_inst|u_apb_mux|pr_select [1]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata [12]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata [12]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [12]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [12]));
defparam \macro_inst|u_ahb2apb|prdata[12] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[12] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[12] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[12] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[12] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_ahb2apb|paddr [4]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .mask = 16'hBFF7;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N12
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[9] (
// Location: LCCOMB_X61_Y3_N12
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[9] (
alta_slice \macro_inst|u_ahb2apb|prdata[9] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [9]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata [9]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [9]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [9]));
defparam \macro_inst|u_ahb2apb|prdata[9] .mask = 16'hECA0;
defparam \macro_inst|u_ahb2apb|prdata[9] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[9] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[9] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[9] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N14
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[8] (
// Location: LCCOMB_X61_Y3_N14
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[8] (
alta_slice \macro_inst|u_ahb2apb|prdata[8] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [8]),
	.B(\macro_inst|u_apb_mux|pr_select [1]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata [8]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [8]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [8]));
defparam \macro_inst|u_ahb2apb|prdata[8] .mask = 16'hECA0;
defparam \macro_inst|u_ahb2apb|prdata[8] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[8] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[8] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[8] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N16
// alta_lcell_ff \macro_inst|u_apb_mux|pr_select[1] (
// Location: LCCOMB_X61_Y3_N16
// alta_lcell_comb \macro_inst|u_apb_mux|pr_select[1]~feeder (
alta_slice \macro_inst|u_apb_mux|pr_select[1] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [12]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_apb_mux|pr_select [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_apb_mux|always0~0_combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|pr_select[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_apb_mux|pr_select [1]));
defparam \macro_inst|u_apb_mux|pr_select[1] .mask = 16'hF0F0;
defparam \macro_inst|u_apb_mux|pr_select[1] .mode = "logic";
defparam \macro_inst|u_apb_mux|pr_select[1] .modeMux = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[1] .BypassEn = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_apb_mux|pr_select[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_apb_mux|pr_select[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_apb_mux|pr_select[1] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N18
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[11] (
// Location: LCCOMB_X61_Y3_N18
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[11] (
alta_slice \macro_inst|u_ahb2apb|prdata[11] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [11]),
	.B(\macro_inst|u_apb_mux|pr_select [0]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata [11]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [11]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [11]));
defparam \macro_inst|u_ahb2apb|prdata[11] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[11] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[11] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[11] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[11] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[11] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[11] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N20
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_pready~0 (
alta_slice \macro_inst|u_apb_mux|apb_in_pready~0 (
	.A(\macro_inst|u_uart[0]|u_regs|apb_pready~q ),
	.B(\macro_inst|u_apb_mux|pr_select [1]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[1]|u_regs|apb_pready~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_pready~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .mask = 16'h135F;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .mode = "logic";
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .modeMux = 1'b0;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .BypassEn = 1'b0;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_apb_mux|apb_in_pready~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector9~2 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector9~2 (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector9~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .mask = 16'h3343;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector9~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .mask = 16'h0F00;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N26
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[10] (
// Location: LCCOMB_X61_Y3_N26
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[10] (
alta_slice \macro_inst|u_ahb2apb|prdata[10] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata [10]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata [10]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [10]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [10]));
defparam \macro_inst|u_ahb2apb|prdata[10] .mask = 16'hEAC0;
defparam \macro_inst|u_ahb2apb|prdata[10] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[10] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[10] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[10] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N28
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[3] (
// Location: LCCOMB_X61_Y3_N28
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[3] (
alta_slice \macro_inst|u_ahb2apb|prdata[3] (
	.A(\macro_inst|u_apb_mux|pr_select [1]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata [3]),
	.C(\macro_inst|u_apb_mux|pr_select [0]),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata [3]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [3]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [3]));
defparam \macro_inst|u_ahb2apb|prdata[3] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[3] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[3] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[3] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 (
alta_slice \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 (
	.A(\macro_inst|u_ahb2apb|paddr [2]),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_ahb2apb|paddr [3]),
	.D(\macro_inst|u_ahb2apb|paddr [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .mask = 16'hADBC;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|apb_prdata[4]~18 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N4
// alta_lcell_ff \macro_inst|u_ahb2apb|prdata[4] (
// Location: LCCOMB_X61_Y3_N4
// alta_lcell_comb \macro_inst|u_apb_mux|apb_in_prdata[4] (
alta_slice \macro_inst|u_ahb2apb|prdata[4] (
	.A(\macro_inst|u_uart[0]|u_regs|apb_prdata [4]),
	.B(\macro_inst|u_apb_mux|pr_select [0]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata [4]),
	.D(\macro_inst|u_apb_mux|pr_select [1]),
	.Cin(),
	.Qin(\macro_inst|u_ahb2apb|prdata [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|apb_in_prdata [4]),
	.Cout(),
	.Q(\macro_inst|u_ahb2apb|prdata [4]));
defparam \macro_inst|u_ahb2apb|prdata[4] .mask = 16'hF888;
defparam \macro_inst|u_ahb2apb|prdata[4] .mode = "logic";
defparam \macro_inst|u_ahb2apb|prdata[4] .modeMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[4] .BypassEn = 1'b0;
defparam \macro_inst|u_ahb2apb|prdata[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_ahb2apb|prdata[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_ahb2apb|prdata[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_ahb2apb|prdata[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_stop .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y3_N8
// alta_lcell_ff \macro_inst|u_apb_mux|pr_select[0] (
// Location: LCCOMB_X61_Y3_N8
// alta_lcell_comb \macro_inst|u_apb_mux|pr_select[0]~0 (
alta_slice \macro_inst|u_apb_mux|pr_select[0] (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_ahb2apb|paddr [12]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_apb_mux|pr_select [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_apb_mux|always0~0_combout_X61_Y3_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_apb_mux|pr_select[0]~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_apb_mux|pr_select [0]));
defparam \macro_inst|u_apb_mux|pr_select[0] .mask = 16'h0F0F;
defparam \macro_inst|u_apb_mux|pr_select[0] .mode = "logic";
defparam \macro_inst|u_apb_mux|pr_select[0] .modeMux = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[0] .BypassEn = 1'b0;
defparam \macro_inst|u_apb_mux|pr_select[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_apb_mux|pr_select[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_apb_mux|pr_select[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_apb_mux|pr_select[0] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y3_N0
alta_clkenctrl clken_ctrl_X61_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_ahb2apb|apb_pdone~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_ahb2apb|apb_pdone~combout_X61_Y3_SIG_SIG ));
defparam clken_ctrl_X61_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y3_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y3_N0
alta_asyncctrl asyncreset_ctrl_X61_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y3_SIG ));
defparam asyncreset_ctrl_X61_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y3_N1
alta_clkenctrl clken_ctrl_X61_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_apb_mux|always0~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_apb_mux|always0~0_combout_X61_Y3_SIG_SIG ));
defparam clken_ctrl_X61_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y3_N1.ClkEnMux = 2'b10;
// Location: LCCOMB_X61_Y4_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|LessThan0~1 (
alta_slice \macro_inst|u_uart[1]|u_baud|LessThan0~1 (
	.A(\macro_inst|u_uart[1]|u_baud|f_cnt [5]),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|u_uart[1]|u_baud|LessThan0~1_cout ),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .mask = 16'h0044;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|LessThan0~10 (
// Location: FF_X61_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_del (
alta_slice \macro_inst|u_uart[1]|u_baud|f_del (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [5]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_baud|f_cnt [0]),
	.Cin(\macro_inst|u_uart[1]|u_baud|LessThan0~9_cout ),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_del~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|LessThan0~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_baud|f_del~q ));
defparam \macro_inst|u_uart[1]|u_baud|f_del .mask = 16'hC0FC;
defparam \macro_inst|u_uart[1]|u_baud|f_del .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|f_del .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_del .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_del .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_del .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_del .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_del .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_del .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|f_del .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector5~4 (
// Location: FF_X61_Y4_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|uart_txd (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|uart_txd (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|Selector5~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|uart_txd~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .mask = 16'h000A;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|uart_txd .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|fbrd[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|fbrd[5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|fbrd [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X61_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|fbrd[5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|fbrd [5]));
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux11~3 (
// Location: FF_X61_Y4_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|status_reg[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|status_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_ahb2apb|paddr [10]),
	.C(\macro_inst|u_uart[1]|u_regs|Mux11~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Mux11~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|status_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X61_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux11~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|status_reg [1]));
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .mask = 16'h0C0F;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|status_reg[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0 (
// Location: FF_X61_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|fbrd[1] (
alta_slice \macro_inst|u_uart[1]|u_regs|fbrd[1] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[0]|u_regs|tx_write [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|fbrd [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X61_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(SyncReset_X61_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|fbrd [1]));
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[1] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y4_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|LessThan0~3 (
alta_slice \macro_inst|u_uart[1]|u_baud|LessThan0~3 (
	.A(\macro_inst|u_uart[1]|u_baud|f_cnt [4]),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|LessThan0~1_cout ),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(),
	.Cout(\macro_inst|u_uart[1]|u_baud|LessThan0~3_cout ),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .mask = 16'h002B;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|LessThan0~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_sps~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .mask = 16'h2000;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] (
// Location: LCCOMB_X61_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_IDLE~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|tx_write [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .mask = 16'h4F40;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_parity~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .mask = 16'hF888;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N26
// alta_lcell_comb \macro_inst|uart_rxd[10] (
alta_slice \macro_inst|uart_rxd[10] (
	.A(vcc),
	.B(vcc),
	.C(\SIM_IO[10]~input_o ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [10]),
	.Cout(),
	.Q());
defparam \macro_inst|uart_rxd[10] .mask = 16'h000F;
defparam \macro_inst|uart_rxd[10] .mode = "logic";
defparam \macro_inst|uart_rxd[10] .modeMux = 1'b0;
defparam \macro_inst|uart_rxd[10] .FeedbackMux = 1'b0;
defparam \macro_inst|uart_rxd[10] .ShiftMux = 1'b0;
defparam \macro_inst|uart_rxd[10] .BypassEn = 1'b0;
defparam \macro_inst|uart_rxd[10] .CarryEnb = 1'b1;
defparam \macro_inst|uart_rxd[10] .AsyncResetMux = 2'bxx;
defparam \macro_inst|uart_rxd[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|uart_rxd[10] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y4_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_write[3] (
// Location: LCCOMB_X61_Y4_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|tx_write~3 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_write[3] (
	.A(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_write [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_write~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_write [3]));
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .mask = 16'h8800;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[3] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_parity (
// Location: LCCOMB_X61_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_parity~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_parity (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_eps~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_parity~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ),
	.AsyncReset(AsyncReset_X61_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_parity~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .mask = 16'h2772;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_parity .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|LessThan0~5 (
// Location: FF_X61_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|fbrd[2] (
alta_slice \macro_inst|u_uart[1]|u_regs|fbrd[2] (
	.A(\macro_inst|u_uart[1]|u_baud|f_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [2]),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|LessThan0~3_cout ),
	.Qin(\macro_inst|u_uart[1]|u_regs|fbrd [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X61_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(SyncReset_X61_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|u_uart[1]|u_baud|LessThan0~5_cout ),
	.Q(\macro_inst|u_uart[1]|u_regs|fbrd [2]));
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .mask = 16'h004D;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[2] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|LessThan0~7 (
// Location: FF_X61_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|fbrd[3] (
alta_slice \macro_inst|u_uart[1]|u_regs|fbrd[3] (
	.A(\macro_inst|u_uart[1]|u_regs|fbrd [3]),
	.B(\macro_inst|u_uart[1]|u_baud|f_cnt [2]),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|LessThan0~5_cout ),
	.Qin(\macro_inst|u_uart[1]|u_regs|fbrd [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X61_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(SyncReset_X61_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|u_uart[1]|u_baud|LessThan0~7_cout ),
	.Q(\macro_inst|u_uart[1]|u_regs|fbrd [3]));
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .mask = 16'h004D;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[3] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|LessThan0~9 (
// Location: FF_X61_Y4_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|fbrd[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|fbrd[4] (
	.A(\macro_inst|u_uart[1]|u_baud|f_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_regs|fbrd [4]),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|LessThan0~7_cout ),
	.Qin(\macro_inst|u_uart[1]|u_regs|fbrd [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X61_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ),
	.SyncReset(SyncReset_X61_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y4_VCC),
	.LutOut(),
	.Cout(\macro_inst|u_uart[1]|u_baud|LessThan0~9_cout ),
	.Q(\macro_inst|u_uart[1]|u_regs|fbrd [4]));
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .mask = 16'h004D;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|fbrd[4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X61_Y4_N0
alta_clkenctrl clken_ctrl_X61_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y4_SIG_VCC ));
defparam clken_ctrl_X61_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y4_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y4_N0
alta_asyncctrl asyncreset_ctrl_X61_Y4_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y4_SIG ));
defparam asyncreset_ctrl_X61_Y4_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y4_N1
alta_clkenctrl clken_ctrl_X61_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always2~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always2~0_combout_X61_Y4_SIG_SIG ));
defparam clken_ctrl_X61_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y4_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y4_N1
alta_asyncctrl asyncreset_ctrl_X61_Y4_N1(.Din(), .Dout(AsyncReset_X61_Y4_GND));
defparam asyncreset_ctrl_X61_Y4_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y4_N0
alta_syncctrl syncreset_ctrl_X61_Y4(.Din(), .Dout(SyncReset_X61_Y4_GND));
defparam syncreset_ctrl_X61_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y4_N1
alta_syncctrl syncload_ctrl_X61_Y4(.Din(), .Dout(SyncLoad_X61_Y4_VCC));
defparam syncload_ctrl_X61_Y4.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X61_Y5_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector1~2 (
// Location: FF_X61_Y5_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[11] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[11] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector1~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(SyncReset_X61_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector1~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [11]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .mask = 16'hDC98;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[11] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y5_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector4~2 (
// Location: FF_X61_Y5_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[8] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[8] (
	.A(\macro_inst|u_uart[1]|u_regs|Selector4~1_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(SyncReset_X61_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector4~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [8]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .mask = 16'hCCB8;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[8] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y5_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[10] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[10] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[10] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ibrd[10]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [10]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[10] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y5_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|fbrd[0] (
// Location: LCCOMB_X61_Y5_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|fbrd[0] (
	.A(\macro_inst|u_uart[0]|u_regs|tx_write [1]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[0] ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|fbrd [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(SyncReset_X61_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y5_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|fbrd [0]));
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .mask = 16'h00AA;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_regs|fbrd[0] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y5_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[6] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ibrd[6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [6]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector8~12 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector8~12 (
	.A(\macro_inst|u_uart[1]|u_regs|status_reg [1]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~17_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector8~10_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector8~11_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector8~12_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .mask = 16'hE222;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector8~12 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .mask = 16'h0080;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y5_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[4] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ibrd[4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [4]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_regs|always6~0 (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .mask = 16'h0020;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|always6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[4]~16_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .mask = 16'h8AAA;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector6~1 (
// Location: FF_X61_Y5_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[12] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[12] (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(SyncReset_X61_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y5_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [12]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .mask = 16'h2211;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[12] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y5_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector5~8 (
// Location: FF_X61_Y5_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[9] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[9] (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.B(\macro_inst|u_ahb2apb|paddr [5]),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_ahb2apb|paddr [2]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(SyncReset_X61_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y5_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector5~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [9]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[9] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y5_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|Selector12~7 (
alta_slice \macro_inst|u_uart[0]|u_regs|Selector12~7 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_regs|fbrd [0]),
	.C(\macro_inst|u_ahb2apb|paddr [5]),
	.D(\macro_inst|u_ahb2apb|paddr [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|Selector12~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .mask = 16'h00C0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|Selector12~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector6~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector6~0 (
	.A(\macro_inst|u_uart[1]|u_regs|status_reg [1]),
	.B(\macro_inst|u_ahb2apb|paddr [4]),
	.C(\macro_inst|u_uart[0]|u_regs|Selector6~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_reg [6]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .mask = 16'h7040;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y5_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4 (
// Location: FF_X61_Y5_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[15] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[15] (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[15] ),
	.D(\macro_inst|u_ahb2apb|paddr [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(SyncReset_X61_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y5_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_regs|apb_prdata[0]~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [15]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .mask = 16'h0055;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[15] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y5_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|ibrd[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|ibrd[5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|ibrd [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ibrd[5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|ibrd [5]));
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|ibrd[5] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y5_N0
alta_clkenctrl clken_ctrl_X61_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always1~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always1~0_combout_X61_Y5_SIG_SIG ));
defparam clken_ctrl_X61_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y5_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y5_N0
alta_asyncctrl asyncreset_ctrl_X61_Y5_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y5_SIG ));
defparam asyncreset_ctrl_X61_Y5_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y5_N1
alta_clkenctrl clken_ctrl_X61_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_regs|always2~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_regs|always2~0_combout_X61_Y5_SIG_SIG ));
defparam clken_ctrl_X61_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y5_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X61_Y5_N0
alta_syncctrl syncreset_ctrl_X61_Y5(.Din(), .Dout(SyncReset_X61_Y5_GND));
defparam syncreset_ctrl_X61_Y5.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y5_N1
alta_syncctrl syncload_ctrl_X61_Y5(.Din(), .Dout(SyncLoad_X61_Y5_VCC));
defparam syncload_ctrl_X61_Y5.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X61_Y6_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 (
	.A(\macro_inst|u_uart[1]|u_regs|always8~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~13_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector2~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector2~3 (
	.A(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [5]),
	.B(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [4]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector2~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector2~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .mask = 16'hAFC0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector3~3 (
// Location: FF_X61_Y6_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|break_error_ie[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|break_error_ie[5] (
	.A(\macro_inst|u_uart[1]|u_regs|ibrd [9]),
	.B(\macro_inst|u_uart[1]|u_regs|Selector3~2_combout ),
	.C(\rv32.mem_ahb_hwdata[9] ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|break_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector3~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|break_error_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|break_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y6_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector2~4 (
// Location: FF_X61_Y6_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[10] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[10] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|Selector2~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector2~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [10]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[10] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~27 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~27 (
	.A(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [5]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|break_error~q ),
	.C(\macro_inst|u_uart[1]|u_regs|break_error_ie [5]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|overrun_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~27_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~27 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector3~0 (
// Location: FF_X61_Y6_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] (
	.A(\macro_inst|u_uart[1]|u_regs|break_error_ie [4]),
	.B(\macro_inst|u_uart[1]|u_regs|break_error_ie [5]),
	.C(\rv32.mem_ahb_hwdata[8] ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|parity_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|parity_error_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|parity_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y6_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector4~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector4~3 (
	.A(\macro_inst|u_uart[1]|u_regs|parity_error_ie [4]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector4~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|parity_error_ie [5]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector4~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .mask = 16'hF838;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector4~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector2~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector2~2 (
	.A(\macro_inst|u_uart[1]|u_regs|ibrd [10]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Selector2~1_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector2~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .mask = 16'hFC22;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector2~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector0~4 (
// Location: FF_X61_Y6_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[12] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[12] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|Selector0~3_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector0~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [12]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .mask = 16'h5050;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[12] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector1~3 (
// Location: FF_X61_Y6_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] (
	.A(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [4]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.C(\rv32.mem_ahb_hwdata[11] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector1~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector1~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_idle_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_idle_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y6_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector4~4 (
// Location: FF_X61_Y6_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[8] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[8] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|Selector4~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector4~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [8]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[8] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector0~2 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector0~2 (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~4_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|ibrd [12]),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector0~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector0~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .mask = 16'hAEA4;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector0~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector0~3 (
// Location: FF_X61_Y6_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] (
	.A(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [4]),
	.B(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.C(\rv32.mem_ahb_hwdata[12] ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector0~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector0~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_complete_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .mask = 16'hF388;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_complete_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y6_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector3~4 (
// Location: FF_X61_Y6_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[9] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[9] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Selector3~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~9_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Selector3~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector3~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [9]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .mask = 16'h4540;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[9] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y6_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector1~4 (
// Location: FF_X61_Y6_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|apb_prdata[11] (
alta_slice \macro_inst|u_uart[1]|u_regs|apb_prdata[11] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_prdata[11]~5_combout ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|Selector1~3_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|apb_prdata [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector1~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|apb_prdata [11]));
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .mask = 16'h5500;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|apb_prdata[11] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y6_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] (
// Location: LCCOMB_X61_Y6_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~13 (
alta_slice \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] (
	.A(\macro_inst|u_ahb2apb|paddr [4]),
	.B(\macro_inst|u_ahb2apb|paddr [8]),
	.C(\rv32.mem_ahb_hwdata[10] ),
	.D(\macro_inst|u_uart[0]|u_regs|Decoder1~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ),
	.SyncReset(SyncReset_X61_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~13_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|overrun_error_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|overrun_error_ie[5] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X61_Y6_N0
alta_clkenctrl clken_ctrl_X61_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y6_SIG_SIG ));
defparam clken_ctrl_X61_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y6_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y6_N0
alta_asyncctrl asyncreset_ctrl_X61_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y6_SIG ));
defparam asyncreset_ctrl_X61_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y6_N1
alta_clkenctrl clken_ctrl_X61_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|apb_read1~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|apb_read1~combout_X61_Y6_SIG_SIG ));
defparam clken_ctrl_X61_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y6_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X61_Y6_N0
alta_syncctrl syncreset_ctrl_X61_Y6(.Din(), .Dout(SyncReset_X61_Y6_GND));
defparam syncreset_ctrl_X61_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y6_N1
alta_syncctrl syncload_ctrl_X61_Y6(.Din(), .Dout(SyncLoad_X61_Y6_VCC));
defparam syncload_ctrl_X61_Y6.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X61_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_stop (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_stop .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_write[3] (
// Location: LCCOMB_X61_Y7_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|tx_write~3 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_write[3] (
	.A(\macro_inst|u_uart[0]|u_regs|rx_not_empty_ie[3]~15_combout ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_write [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_write~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_write [3]));
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .mask = 16'hA000;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[3] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START (
// Location: LCCOMB_X61_Y7_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .mask = 16'hCCEC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] (
// Location: LCCOMB_X61_Y7_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|status_reg[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(SyncReset_X61_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|status_reg[2]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y7_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector3~1 (
// Location: FF_X61_Y7_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[1]|Selector3~0_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[1]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .mask = 16'hECCC;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] (
// Location: LCCOMB_X61_Y7_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[1]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[1]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[7] ),
	.D(\macro_inst|u_uart[1]|u_tx[1]|tx_state.UART_PARITY~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|framing_error_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(SyncReset_X61_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[1]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|framing_error_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .mask = 16'h3300;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|framing_error_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .mask = 16'h00F0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~25 (
// Location: FF_X61_Y7_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie [5]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(SyncReset_X61_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~25_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_not_full_ie [5]));
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .mask = 16'hBA30;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|tx_not_full_ie[5] .SyncLoadMux = 2'b01;
// Location: LCCOMB_X61_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|fifo_rden (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|fifo_rden (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .mask = 16'hCC44;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|tx_write [5]),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .mask = 16'h00F0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|Selector0~0 (
// Location: FF_X61_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] (
// Location: LCCOMB_X61_Y7_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_regs|tx_write [5]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .mask = 16'h0CAC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|interrupts[5] (
// Location: LCCOMB_X61_Y7_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~29 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts[5] (
	.A(\macro_inst|u_uart[1]|u_regs|interrupts~28_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|interrupts~25_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|interrupts~26_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|interrupts~27_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|interrupts [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~29_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|interrupts [5]));
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .mask = 16'hFFFE;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts[5] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|interrupts~26 (
alta_slice \macro_inst|u_uart[1]|u_regs|interrupts~26 (
	.A(\macro_inst|u_uart[1]|u_regs|framing_error_ie [5]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|framing_error~q ),
	.C(\macro_inst|u_uart[1]|u_regs|parity_error_ie [5]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|parity_error~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|interrupts~26_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .mask = 16'hF888;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|interrupts~26 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y7_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|always0~0_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|Selector5~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .mask = 16'h35FF;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y7_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|tx_write[5] (
// Location: LCCOMB_X61_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|tx_write~5 (
alta_slice \macro_inst|u_uart[1]|u_regs|tx_write[5] (
	.A(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.D(\macro_inst|u_ahb2apb|paddr [8]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|tx_write [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|tx_write~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|tx_write [5]));
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|tx_write[5] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y7_N0
alta_clkenctrl clken_ctrl_X61_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y7_SIG_VCC ));
defparam clken_ctrl_X61_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y7_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y7_N0
alta_asyncctrl asyncreset_ctrl_X61_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y7_SIG ));
defparam asyncreset_ctrl_X61_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y7_N1
alta_clkenctrl clken_ctrl_X61_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|rx_not_empty_ie[5]~14_combout_X61_Y7_SIG_SIG ));
defparam clken_ctrl_X61_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y7_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X61_Y7_N0
alta_syncctrl syncreset_ctrl_X61_Y7(.Din(), .Dout(SyncReset_X61_Y7_GND));
defparam syncreset_ctrl_X61_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y7_N1
alta_syncctrl syncload_ctrl_X61_Y7(.Din(), .Dout(SyncLoad_X61_Y7_VCC));
defparam syncload_ctrl_X61_Y7.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X61_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|Equal1~2 (
alta_slice \macro_inst|u_uart[1]|u_baud|Equal1~2 (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [10]),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [11]),
	.C(\macro_inst|u_uart[1]|u_baud|i_cnt [9]),
	.D(\macro_inst|u_uart[1]|u_baud|i_cnt [12]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|Equal1~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~2 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_cnt[1] (
// Location: LCCOMB_X61_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|f_cnt[1]~8 (
alta_slice \macro_inst|u_uart[1]|u_baud|f_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_baud|f_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|f_cnt[0]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_baud|f_cnt[1]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|f_cnt[1]~9 ),
	.Q(\macro_inst|u_uart[1]|u_baud|f_cnt [1]));
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y8_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_cnt[2] (
// Location: LCCOMB_X61_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|f_cnt[2]~10 (
alta_slice \macro_inst|u_uart[1]|u_baud|f_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_baud|f_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|f_cnt[1]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_baud|f_cnt[2]~10_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|f_cnt[2]~11 ),
	.Q(\macro_inst|u_uart[1]|u_baud|f_cnt [2]));
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y8_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_cnt[3] (
// Location: LCCOMB_X61_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|f_cnt[3]~12 (
alta_slice \macro_inst|u_uart[1]|u_baud|f_cnt[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|f_cnt [3]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|f_cnt[2]~11 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_baud|f_cnt[3]~12_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|f_cnt[3]~13 ),
	.Q(\macro_inst|u_uart[1]|u_baud|f_cnt [3]));
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y8_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_cnt[4] (
// Location: LCCOMB_X61_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|f_cnt[4]~14 (
alta_slice \macro_inst|u_uart[1]|u_baud|f_cnt[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|f_cnt [4]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|f_cnt[3]~13 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_baud|f_cnt[4]~14_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|f_cnt[4]~15 ),
	.Q(\macro_inst|u_uart[1]|u_baud|f_cnt [4]));
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[4] .SyncLoadMux = 2'b00;
// Location: FF_X61_Y8_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_cnt[5] (
// Location: LCCOMB_X61_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|f_cnt[5]~16 (
alta_slice \macro_inst|u_uart[1]|u_baud|f_cnt[5] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_baud|f_cnt [5]),
	.Cin(\macro_inst|u_uart[1]|u_baud|f_cnt[4]~15 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_baud|f_cnt[5]~16_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_baud|f_cnt [5]));
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[5] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X61_Y8_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_baud|always0~0 (
	.A(\macro_inst|u_uart[1]|u_baud|f_del~q ),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_baud|Equal1~4_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|uart_en~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .mask = 16'hD0FF;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|always0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|parity_error (
// Location: LCCOMB_X61_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|parity_error~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|parity_error (
	.A(\macro_inst|u_uart[1]|u_rx[5]|parity_error~0_combout ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_sample~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|parity_error~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|parity_error~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|parity_error~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .mask = 16'h88F8;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|parity_error .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|Equal1~3 (
alta_slice \macro_inst|u_uart[1]|u_baud|Equal1~3 (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [13]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_baud|i_cnt [15]),
	.D(\macro_inst|u_uart[1]|u_baud|i_cnt [14]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|Equal1~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .mask = 16'h0005;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Mux11~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|Mux11~0 (
	.A(\macro_inst|u_ahb2apb|paddr [10]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ),
	.C(\macro_inst|u_ahb2apb|paddr [8]),
	.D(\macro_inst|u_uart[1]|u_rx[4]|rx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Mux11~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .mask = 16'h8A80;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Mux11~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|Equal1~0 (
alta_slice \macro_inst|u_uart[1]|u_baud|Equal1~0 (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [4]),
	.C(\macro_inst|u_uart[1]|u_baud|i_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_baud|i_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|Equal1~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|Equal1~1 (
alta_slice \macro_inst|u_uart[1]|u_baud|Equal1~1 (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [7]),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [5]),
	.C(\macro_inst|u_uart[1]|u_baud|i_cnt [6]),
	.D(\macro_inst|u_uart[1]|u_baud|i_cnt [8]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|Equal1~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|always2~0 (
// Location: FF_X61_Y8_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|baud16 (
alta_slice \macro_inst|u_uart[1]|u_baud|baud16 (
	.A(\macro_inst|u_uart[1]|u_baud|f_del~q ),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_baud|Equal1~4_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|uart_en~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|always2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_baud|baud16~q ));
defparam \macro_inst|u_uart[1]|u_baud|baud16 .mask = 16'hD000;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|baud16 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|baud16 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X61_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|Equal1~4 (
alta_slice \macro_inst|u_uart[1]|u_baud|Equal1~4 (
	.A(\macro_inst|u_uart[1]|u_baud|Equal1~3_combout ),
	.B(\macro_inst|u_uart[1]|u_baud|Equal1~1_combout ),
	.C(\macro_inst|u_uart[1]|u_baud|Equal1~0_combout ),
	.D(\macro_inst|u_uart[1]|u_baud|Equal1~2_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_baud|Equal1~4_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_baud|Equal1~4 .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en (
// Location: LCCOMB_X61_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|clear_flags[5]~16_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_idle_en~q ));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .mask = 16'hCCFC;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_idle_en .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y8_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|f_cnt[0] (
// Location: LCCOMB_X61_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|f_cnt[0]~6 (
alta_slice \macro_inst|u_uart[1]|u_baud|f_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_baud|f_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_baud|f_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y8_GND),
	.LutOut(\macro_inst|u_uart[1]|u_baud|f_cnt[0]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|f_cnt[0]~7 ),
	.Q(\macro_inst|u_uart[1]|u_baud|f_cnt [0]));
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .SyncResetMux = 2'b11;
defparam \macro_inst|u_uart[1]|u_baud|f_cnt[0] .SyncLoadMux = 2'b00;

// Location: CLKENCTRL_X61_Y8_N0
alta_clkenctrl clken_ctrl_X61_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X61_Y8_SIG_VCC ));
defparam clken_ctrl_X61_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y8_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X61_Y8_N0
alta_asyncctrl asyncreset_ctrl_X61_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y8_SIG ));
defparam asyncreset_ctrl_X61_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X61_Y8_N0
alta_syncctrl syncreset_ctrl_X61_Y8(.Din(\macro_inst|u_uart[1]|u_regs|uart_en~q ), .Dout(\macro_inst|u_uart[1]|u_regs|uart_en~q__SyncReset_X61_Y8_INV ));
defparam syncreset_ctrl_X61_Y8.SyncCtrlMux = 2'b11;

// Location: SYNCCTRL_X61_Y8_N1
alta_syncctrl syncload_ctrl_X61_Y8(.Din(), .Dout(SyncLoad_X61_Y8_GND));
defparam syncload_ctrl_X61_Y8.SyncCtrlMux = 2'b00;
// Location: FF_X61_Y9_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] (
// Location: LCCOMB_X61_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1]~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .mask = 16'hAACC;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] (
// Location: LCCOMB_X61_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(SyncReset_X61_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y9_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] (
// Location: LCCOMB_X61_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [5]),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] (
// Location: LCCOMB_X61_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY~q ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(SyncReset_X61_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .mask = 16'h00AA;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y9_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] (
// Location: LCCOMB_X61_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [1]),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] (
// Location: LCCOMB_X61_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][2]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] (
// Location: LCCOMB_X61_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [0]),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7]~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .mask = 16'hCCAA;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] (
// Location: LCCOMB_X61_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [4]),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] (
// Location: LCCOMB_X61_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][5]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] (
// Location: LCCOMB_X61_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector5~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(SyncReset_X61_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector5~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .mask = 16'h4444;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y9_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X61_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] (
// Location: LCCOMB_X61_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_IDLE~q ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_fifo|counter ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X61_Y9_GND),
	.SyncReset(SyncReset_X61_Y9_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X61_Y9_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .mask = 16'h0033;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: FF_X61_Y9_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] (
// Location: LCCOMB_X61_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [7]),
	.C(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|fifo[1][6]~q ),
	.D(\macro_inst|u_uart[0]|u_tx[1]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X61_Y9_N0
alta_clkenctrl clken_ctrl_X61_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_shift_reg[7]~1_combout_X61_Y9_SIG_SIG ));
defparam clken_ctrl_X61_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y9_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y9_N0
alta_asyncctrl asyncreset_ctrl_X61_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X61_Y9_SIG ));
defparam asyncreset_ctrl_X61_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X61_Y9_N1
alta_clkenctrl clken_ctrl_X61_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[1]|tx_fifo|wrreq~0_combout_X61_Y9_SIG_SIG ));
defparam clken_ctrl_X61_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X61_Y9_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X61_Y9_N1
alta_asyncctrl asyncreset_ctrl_X61_Y9_N1(.Din(), .Dout(AsyncReset_X61_Y9_GND));
defparam asyncreset_ctrl_X61_Y9_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y9_N0
alta_syncctrl syncreset_ctrl_X61_Y9(.Din(), .Dout(SyncReset_X61_Y9_GND));
defparam syncreset_ctrl_X61_Y9.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X61_Y9_N1
alta_syncctrl syncload_ctrl_X61_Y9(.Din(), .Dout(SyncLoad_X61_Y9_VCC));
defparam syncload_ctrl_X61_Y9.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X62_Y10_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|fifo_rden (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|fifo_rden (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|counter ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .mask = 16'h2A0A;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y10_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector5~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .mask = 16'h00F0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y10_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|Selector5~3_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .mask = 16'h57DF;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y10_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] (
// Location: LCCOMB_X62_Y10_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout_X62_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .mask = 16'hFCED;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y10_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] (
// Location: LCCOMB_X62_Y10_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout_X62_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .mask = 16'hEDED;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y10_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .mask = 16'hECEC;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y10_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|fifo_rden~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y10_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] (
// Location: LCCOMB_X62_Y10_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] (
// Location: LCCOMB_X62_Y10_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] (
// Location: LCCOMB_X62_Y10_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y10_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] (
// Location: LCCOMB_X62_Y10_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [3]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y10_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y10_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .mask = 16'h5A5A;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y10_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|always0~0 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [2]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .mask = 16'h0002;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y10_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|always6~1 (
// Location: FF_X62_Y10_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_bit (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|always6~0_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [3]),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .mask = 16'hC0C0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y10_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START (
// Location: LCCOMB_X62_Y10_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .mask = 16'hCCEC;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y10_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] (
// Location: LCCOMB_X62_Y10_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout_X62_Y10_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y10_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .mask = 16'hCFCF;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y10_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|always6~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|always6~0 (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|always6~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y10_N0
alta_clkenctrl clken_ctrl_X62_Y10_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y10_SIG_VCC ));
defparam clken_ctrl_X62_Y10_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y10_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y10_N0
alta_asyncctrl asyncreset_ctrl_X62_Y10_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y10_SIG ));
defparam asyncreset_ctrl_X62_Y10_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y10_N1
alta_clkenctrl clken_ctrl_X62_Y10_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_data_cnt[2]~1_combout_X62_Y10_SIG_SIG ));
defparam clken_ctrl_X62_Y10_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y10_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y10_N1
alta_asyncctrl asyncreset_ctrl_X62_Y10_N1(.Din(), .Dout(AsyncReset_X62_Y10_GND));
defparam asyncreset_ctrl_X62_Y10_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y10_N0
alta_syncctrl syncreset_ctrl_X62_Y10(.Din(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout ), .Dout(\macro_inst|u_uart[1]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y10_SIG ));
defparam syncreset_ctrl_X62_Y10.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y10_N1
alta_syncctrl syncload_ctrl_X62_Y10(.Din(), .Dout(SyncLoad_X62_Y10_GND));
defparam syncload_ctrl_X62_Y10.SyncCtrlMux = 2'b00;
// Location: FF_X62_Y11_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] (
// Location: LCCOMB_X62_Y11_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add4~1_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout_X62_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .mask = 16'hABBB;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always2~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|always2~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always2~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .mask = 16'h8800;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always2~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y11_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] (
// Location: LCCOMB_X62_Y11_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add4~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y11_SIG_VCC ),
	.AsyncReset(AsyncReset_X62_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .mask = 16'h0072;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[3] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|always3~1 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~1 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|always3~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|always3~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[5]|always3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|always3~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|always3~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [3]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .mask = 16'h0001;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y11_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] (
// Location: LCCOMB_X62_Y11_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|always3~2_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_rx[5]|Add3~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout_X62_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .mask = 16'hABAF;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Add4~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Add4~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Add4~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .mask = 16'h03FC;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~1 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y11_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] (
// Location: LCCOMB_X62_Y11_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~5 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_rx[5]|Add4~2_combout ),
	.C(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|always3~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout_X62_Y11_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y11_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .mask = 16'hFABB;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y11_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] (
// Location: LCCOMB_X62_Y11_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [0]),
	.B(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y11_SIG ),
	.SyncReset(SyncReset_X62_Y11_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout__SyncLoad_X62_Y11_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y11_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] (
// Location: LCCOMB_X62_Y11_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y11_SIG ),
	.SyncReset(SyncReset_X62_Y11_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout__SyncLoad_X62_Y11_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y11_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] (
// Location: LCCOMB_X62_Y11_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y11_SIG ),
	.SyncReset(SyncReset_X62_Y11_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout__SyncLoad_X62_Y11_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y11_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] (
// Location: LCCOMB_X62_Y11_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [3]),
	.B(vcc),
	.C(\~GND~combout ),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y11_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y11_SIG ),
	.SyncReset(SyncReset_X62_Y11_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout__SyncLoad_X62_Y11_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .mask = 16'h5A5A;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_baud_cnt[3] .SyncLoadMux = 2'b10;
// Location: LCCOMB_X62_Y11_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Add4~0 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Add4~0 (
	.A(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [3]),
	.B(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Add4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .mask = 16'h5556;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .mask = 16'hFFF0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y11_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Add4~2 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Add4~2 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [1]),
	.D(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Add4~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add4~2 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y11_N0
alta_clkenctrl clken_ctrl_X62_Y11_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_rx[5]|rx_data_cnt[0]~3_combout_X62_Y11_SIG_SIG ));
defparam clken_ctrl_X62_Y11_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y11_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y11_N0
alta_asyncctrl asyncreset_ctrl_X62_Y11_N0(.Din(), .Dout(AsyncReset_X62_Y11_GND));
defparam asyncreset_ctrl_X62_Y11_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X62_Y11_N1
alta_clkenctrl clken_ctrl_X62_Y11_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y11_SIG_VCC ));
defparam clken_ctrl_X62_Y11_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y11_N1.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y11_N1
alta_asyncctrl asyncreset_ctrl_X62_Y11_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y11_SIG ));
defparam asyncreset_ctrl_X62_Y11_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y11_N0
alta_syncctrl syncreset_ctrl_X62_Y11(.Din(), .Dout(SyncReset_X62_Y11_GND));
defparam syncreset_ctrl_X62_Y11.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y11_N1
alta_syncctrl syncload_ctrl_X62_Y11(.Din(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout ), .Dout(\macro_inst|u_uart[1]|u_rx[5]|always6~1_combout__SyncLoad_X62_Y11_SIG ));
defparam syncload_ctrl_X62_Y11.SyncCtrlMux = 2'b10;
// Location: FF_X62_Y12_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] (
// Location: LCCOMB_X62_Y12_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [5]),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][4]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .mask = 16'hEE22;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] (
// Location: LCCOMB_X62_Y12_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .mask = 16'hFC30;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] (
// Location: LCCOMB_X62_Y12_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(SyncReset_X62_Y12_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y12_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .mask = 16'hFF88;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'b01;
// Location: FF_X62_Y12_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] (
// Location: LCCOMB_X62_Y12_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][2]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] (
// Location: LCCOMB_X62_Y12_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][7]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .mask = 16'hBB88;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y12_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] (
// Location: LCCOMB_X62_Y12_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][6]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .mask = 16'hFC30;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] (
// Location: LCCOMB_X62_Y12_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [4]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][3]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .mask = 16'hFC30;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] (
// Location: LCCOMB_X62_Y12_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][5]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .mask = 16'hFC30;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y12_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] (
// Location: LCCOMB_X62_Y12_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|fifo[1][1]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[1]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y12_N0
alta_clkenctrl clken_ctrl_X62_Y12_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y12_SIG_SIG ));
defparam clken_ctrl_X62_Y12_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y12_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y12_N0
alta_asyncctrl asyncreset_ctrl_X62_Y12_N0(.Din(), .Dout(AsyncReset_X62_Y12_GND));
defparam asyncreset_ctrl_X62_Y12_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X62_Y12_N1
alta_clkenctrl clken_ctrl_X62_Y12_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg[4]~1_combout_X62_Y12_SIG_SIG ));
defparam clken_ctrl_X62_Y12_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y12_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y12_N1
alta_asyncctrl asyncreset_ctrl_X62_Y12_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y12_SIG ));
defparam asyncreset_ctrl_X62_Y12_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y12_N0
alta_syncctrl syncreset_ctrl_X62_Y12(.Din(), .Dout(SyncReset_X62_Y12_GND));
defparam syncreset_ctrl_X62_Y12.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y12_N1
alta_syncctrl syncload_ctrl_X62_Y12(.Din(), .Dout(SyncLoad_X62_Y12_VCC));
defparam syncload_ctrl_X62_Y12.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X62_Y1_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|Selector5~3_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|always0~0_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .mask = 16'h1FDF;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector0~0 (
// Location: FF_X62_Y1_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .mask = 16'hAAFA;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y1_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] (
// Location: LCCOMB_X62_Y1_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [0]),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout_X62_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .mask = 16'hFFA5;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y1_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] (
// Location: LCCOMB_X62_Y1_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout__SyncReset_X62_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y1_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] (
// Location: LCCOMB_X62_Y1_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout__SyncReset_X62_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y1_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] (
// Location: LCCOMB_X62_Y1_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout__SyncReset_X62_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y1_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|always0~0 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .mask = 16'h0004;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|always0~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y1_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] (
// Location: LCCOMB_X62_Y1_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout__SyncReset_X62_Y1_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y1_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y1_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|fifo_rden (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|fifo_rden (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .mask = 16'hA0AA;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|always6~0 (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [1]),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [0]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_baud_cnt [2]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|always6~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y1_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] (
// Location: LCCOMB_X62_Y1_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout_X62_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .mask = 16'hFCED;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y1_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START (
// Location: LCCOMB_X62_Y1_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|comb~1_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .mask = 16'hBAAA;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|counter ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_IDLE~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_stop .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|Selector2~0 (
// Location: FF_X62_Y1_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .mask = 16'h88F8;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y1_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] (
// Location: LCCOMB_X62_Y1_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout_X62_Y1_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y1_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y1_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .mask = 16'hFFA0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y1_N0
alta_clkenctrl clken_ctrl_X62_Y1_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y1_SIG_VCC ));
defparam clken_ctrl_X62_Y1_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y1_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y1_N0
alta_asyncctrl asyncreset_ctrl_X62_Y1_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y1_SIG ));
defparam asyncreset_ctrl_X62_Y1_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y1_N1
alta_clkenctrl clken_ctrl_X62_Y1_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_data_cnt[0]~1_combout_X62_Y1_SIG_SIG ));
defparam clken_ctrl_X62_Y1_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y1_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y1_N1
alta_asyncctrl asyncreset_ctrl_X62_Y1_N1(.Din(), .Dout(AsyncReset_X62_Y1_GND));
defparam asyncreset_ctrl_X62_Y1_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y1_N0
alta_syncctrl syncreset_ctrl_X62_Y1(.Din(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout ), .Dout(\macro_inst|u_uart[0]|u_tx[2]|tx_stop~combout__SyncReset_X62_Y1_SIG ));
defparam syncreset_ctrl_X62_Y1.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y1_N1
alta_syncctrl syncload_ctrl_X62_Y1(.Din(), .Dout(SyncLoad_X62_Y1_GND));
defparam syncload_ctrl_X62_Y1.SyncCtrlMux = 2'b00;
// Location: FF_X62_Y2_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] (
// Location: LCCOMB_X62_Y2_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y2_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y2_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y2_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] (
// Location: LCCOMB_X62_Y2_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [1]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y2_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y2_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .mask = 16'h5A5F;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y2_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] (
// Location: LCCOMB_X62_Y2_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y2_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y2_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y2_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] (
// Location: LCCOMB_X62_Y2_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y2_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y2_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y2_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] (
// Location: LCCOMB_X62_Y2_N18
// alta_lcell_comb \macro_inst|uart_rxd[4] (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.B(vcc),
	.C(vcc),
	.D(\SIM_IO[4]~input_o ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_in [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X62_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|uart_rxd [4]),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_in [0]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .mask = 16'h0055;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|fifo_rden (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|fifo_rden (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .mask = 16'hCC44;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|fifo_rden .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|always6~1 (
// Location: FF_X62_Y2_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_bit (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_bit (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [3]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|always6~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .mask = 16'hCC00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_bit .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y2_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] (
// Location: LCCOMB_X62_Y2_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_rx[4]|rx_in[1]~feeder (
alta_slice \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_rx[4]|rx_in [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_rx[4]|rx_in [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X62_Y2_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_rx[4]|rx_in[1]~feeder_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_rx[4]|rx_in [1]));
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_rx[4]|rx_in[1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y2_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] (
// Location: LCCOMB_X62_Y2_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[0]|u_regs|tx_write [4]),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .mask = 16'h0CAC;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y2_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_regs|tx_write[4] (
// Location: LCCOMB_X62_Y2_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_regs|tx_write~4 (
alta_slice \macro_inst|u_uart[0]|u_regs|tx_write[4] (
	.A(\macro_inst|u_ahb2apb|paddr [8]),
	.B(\macro_inst|u_uart[0]|u_regs|apb_write~0_combout ),
	.C(\macro_inst|u_uart[1]|u_regs|Equal2~2_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|ShiftLeft0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_regs|tx_write [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_regs|tx_write~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_regs|tx_write [4]));
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .mask = 16'h4000;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_regs|tx_write[4] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_regs|tx_write [4]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .mask = 16'h00F0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|Selector0~0 (
// Location: FF_X62_Y2_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[4]|comb~1_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|Selector0~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .mask = 16'hCCFC;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_stop (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_stop (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_IDLE~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|counter ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .mask = 16'h000F;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_stop .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|always6~0 (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [2]),
	.C(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|tx_baud_cnt [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|always6~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y2_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector4~1 (
// Location: FF_X62_Y2_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|always0~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|Selector4~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .mask = 16'hFF40;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y2_N0
alta_clkenctrl clken_ctrl_X62_Y2_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y2_SIG_VCC ));
defparam clken_ctrl_X62_Y2_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y2_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y2_N0
alta_asyncctrl asyncreset_ctrl_X62_Y2_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y2_SIG ));
defparam asyncreset_ctrl_X62_Y2_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y2_N1
alta_clkenctrl clken_ctrl_X62_Y2_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_baud|baud16~q ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_baud|baud16~q_X62_Y2_SIG_SIG ));
defparam clken_ctrl_X62_Y2_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y2_N1.ClkEnMux = 2'b10;

// Location: SYNCCTRL_X62_Y2_N0
alta_syncctrl syncreset_ctrl_X62_Y2(.Din(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout ), .Dout(\macro_inst|u_uart[0]|u_tx[4]|tx_stop~combout__SyncReset_X62_Y2_SIG ));
defparam syncreset_ctrl_X62_Y2.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y2_N1
alta_syncctrl syncload_ctrl_X62_Y2(.Din(), .Dout(SyncLoad_X62_Y2_GND));
defparam syncload_ctrl_X62_Y2.SyncCtrlMux = 2'b00;
// Location: LCCOMB_X62_Y3_N0
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|always0~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|Selector5~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .mask = 16'h47FF;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector3~1 (
// Location: FF_X62_Y3_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[0]|u_tx[3]|Selector3~0_combout ),
	.B(\macro_inst|u_uart[0]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|always0~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .mask = 16'hEAAA;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y3_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] (
// Location: LCCOMB_X62_Y3_N12
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [1]),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout_X62_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .mask = 16'hFCED;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|always6~1 (
// Location: FF_X62_Y3_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_bit (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_bit (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[3]|always6~0_combout ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .mask = 16'hF000;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector2~0 (
// Location: FF_X62_Y3_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[0]|u_tx[3]|always0~0_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .mask = 16'hDC50;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y3_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] (
// Location: LCCOMB_X62_Y3_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y3_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y3_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START (
// Location: LCCOMB_X62_Y3_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START (
	.A(\macro_inst|u_uart[0]|u_tx[3]|comb~1_combout ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .mask = 16'hFF40;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y3_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] (
// Location: LCCOMB_X62_Y3_N20
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y3_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y3_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] (
// Location: LCCOMB_X62_Y3_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [2]),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y3_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .mask = 16'hA50A;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y3_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] (
// Location: LCCOMB_X62_Y3_N24
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ),
	.SyncReset(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y3_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y3_GND),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y3_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_PARITY~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|Selector3~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .mask = 16'h0C0C;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|Selector3~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y3_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] (
// Location: LCCOMB_X62_Y3_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout_X62_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .mask = 16'hFF0F;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|always0~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|always0~0 (
	.A(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .mask = 16'h0010;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|always6~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|always6~0 (
	.A(\macro_inst|u_uart[0]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [0]),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [2]),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|always6~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y3_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] (
// Location: LCCOMB_X62_Y3_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout_X62_Y3_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y3_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .mask = 16'hFCCF;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y3_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_START~q ),
	.C(\macro_inst|u_uart[0]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[0]|u_tx[3]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .mask = 16'hFCCC;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y3_N0
alta_clkenctrl clken_ctrl_X62_Y3_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y3_SIG_VCC ));
defparam clken_ctrl_X62_Y3_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y3_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y3_N0
alta_asyncctrl asyncreset_ctrl_X62_Y3_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y3_SIG ));
defparam asyncreset_ctrl_X62_Y3_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y3_N1
alta_clkenctrl clken_ctrl_X62_Y3_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[3]|tx_data_cnt[0]~1_combout_X62_Y3_SIG_SIG ));
defparam clken_ctrl_X62_Y3_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y3_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y3_N1
alta_asyncctrl asyncreset_ctrl_X62_Y3_N1(.Din(), .Dout(AsyncReset_X62_Y3_GND));
defparam asyncreset_ctrl_X62_Y3_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y3_N0
alta_syncctrl syncreset_ctrl_X62_Y3(.Din(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout ), .Dout(\macro_inst|u_uart[0]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y3_SIG ));
defparam syncreset_ctrl_X62_Y3.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y3_N1
alta_syncctrl syncload_ctrl_X62_Y3(.Din(), .Dout(SyncLoad_X62_Y3_GND));
defparam syncload_ctrl_X62_Y3.SyncCtrlMux = 2'b00;
// Location: FF_X62_Y4_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[2] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] (
// Location: LCCOMB_X62_Y4_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [0]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] (
// Location: LCCOMB_X62_Y4_N16
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] (
// Location: LCCOMB_X62_Y4_N18
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] (
// Location: LCCOMB_X62_Y4_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][4]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [5]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] (
// Location: LCCOMB_X62_Y4_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][3]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] (
// Location: LCCOMB_X62_Y4_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] (
// Location: LCCOMB_X62_Y4_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][2]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y4_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] (
// Location: LCCOMB_X62_Y4_N6
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] (
	.A(\macro_inst|u_uart[0]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\rv32.mem_ahb_hwdata[5] ),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y4_GND),
	.SyncReset(SyncReset_X62_Y4_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y4_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'b01;
// Location: FF_X62_Y4_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] (
// Location: LCCOMB_X62_Y4_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|fifo[1][6]~q ),
	.C(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_tx[4]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y4_N0
alta_clkenctrl clken_ctrl_X62_Y4_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_fifo|wrreq~0_combout_X62_Y4_SIG_SIG ));
defparam clken_ctrl_X62_Y4_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y4_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y4_N0
alta_asyncctrl asyncreset_ctrl_X62_Y4_N0(.Din(), .Dout(AsyncReset_X62_Y4_GND));
defparam asyncreset_ctrl_X62_Y4_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X62_Y4_N1
alta_clkenctrl clken_ctrl_X62_Y4_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[4]|tx_shift_reg[3]~1_combout_X62_Y4_SIG_SIG ));
defparam clken_ctrl_X62_Y4_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y4_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y4_N1
alta_asyncctrl asyncreset_ctrl_X62_Y4_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y4_SIG ));
defparam asyncreset_ctrl_X62_Y4_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y4_N0
alta_syncctrl syncreset_ctrl_X62_Y4(.Din(), .Dout(SyncReset_X62_Y4_GND));
defparam syncreset_ctrl_X62_Y4.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y4_N1
alta_syncctrl syncload_ctrl_X62_Y4(.Din(), .Dout(SyncLoad_X62_Y4_VCC));
defparam syncload_ctrl_X62_Y4.SyncCtrlMux = 2'b01;
// Location: FF_X62_Y5_N0
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N10
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] (
// Location: LCCOMB_X62_Y5_N10
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][5]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .mask = 16'hFC30;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N12
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N14
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] (
// Location: LCCOMB_X62_Y5_N14
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [5]),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .mask = 16'hEE22;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N16
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[4] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N18
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N2
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] (
// Location: LCCOMB_X62_Y5_N2
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|tx_bit~q ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(SyncReset_X62_Y5_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y5_VCC),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .mask = 16'hFF88;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: FF_X62_Y5_N20
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N22
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] (
// Location: LCCOMB_X62_Y5_N22
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][7]~q ),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .mask = 16'hBB88;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N24
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N26
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] (
// Location: LCCOMB_X62_Y5_N26
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [4]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][3]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .mask = 16'hFC30;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N28
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] (
// Location: LCCOMB_X62_Y5_N28
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [1]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][0]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .mask = 16'hFC30;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N30
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] (
// Location: LCCOMB_X62_Y5_N30
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] (
	.A(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][2]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N4
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] (
// Location: LCCOMB_X62_Y5_N4
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .mask = 16'hFC30;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N6
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y5_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y5_N8
// alta_lcell_ff \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] (
// Location: LCCOMB_X62_Y5_N8
// alta_lcell_comb \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[0]|u_tx[2]|fifo_rden~combout ),
	.C(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [2]),
	.D(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|fifo[1][1]~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .mask = 16'hFC30;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y5_N0
alta_clkenctrl clken_ctrl_X62_Y5_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_fifo|wrreq~0_combout_X62_Y5_SIG_SIG ));
defparam clken_ctrl_X62_Y5_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y5_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y5_N0
alta_asyncctrl asyncreset_ctrl_X62_Y5_N0(.Din(), .Dout(AsyncReset_X62_Y5_GND));
defparam asyncreset_ctrl_X62_Y5_N0.AsyncCtrlMux = 2'b00;

// Location: CLKENCTRL_X62_Y5_N1
alta_clkenctrl clken_ctrl_X62_Y5_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[0]|u_tx[2]|tx_shift_reg[5]~1_combout_X62_Y5_SIG_SIG ));
defparam clken_ctrl_X62_Y5_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y5_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y5_N1
alta_asyncctrl asyncreset_ctrl_X62_Y5_N1(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y5_SIG ));
defparam asyncreset_ctrl_X62_Y5_N1.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y5_N0
alta_syncctrl syncreset_ctrl_X62_Y5(.Din(), .Dout(SyncReset_X62_Y5_GND));
defparam syncreset_ctrl_X62_Y5.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y5_N1
alta_syncctrl syncload_ctrl_X62_Y5(.Din(), .Dout(SyncLoad_X62_Y5_VCC));
defparam syncload_ctrl_X62_Y5.SyncCtrlMux = 2'b01;
// Location: LCCOMB_X62_Y6_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector2~0 (
// Location: FF_X62_Y6_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_tx[4]|always0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y6_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt (
// Location: LCCOMB_X62_Y6_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ),
	.AsyncReset(AsyncReset_X62_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .mask = 16'hFF88;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .mask = 16'h1540;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|Selector11~7 (
alta_slice \macro_inst|u_uart[1]|u_regs|Selector11~7 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_ahb2apb|paddr [3]),
	.C(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~13_combout ),
	.D(\macro_inst|u_uart[0]|u_regs|apb_prdata[1]~14_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|Selector11~7_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .mask = 16'h888F;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|Selector11~7 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [0]),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_parity~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector5~2_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .mask = 16'hEAC0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector5~2 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_shift_reg [0]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_parity~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .mask = 16'h0800;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector4~1 (
// Location: FF_X62_Y6_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_tx[4]|always0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|Selector4~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .mask = 16'hF2F0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y6_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|lcr_sps (
alta_slice \macro_inst|u_uart[1]|u_regs|lcr_sps (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always5~0_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_regs|lcr_sps__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|lcr_sps~q ));
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_regs|lcr_sps .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector5~4 (
// Location: FF_X62_Y6_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|uart_txd (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|uart_txd (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_IDLE~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[4]|Selector5~2_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|uart_txd~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector5~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|uart_txd~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .mask = 16'h0022;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|uart_txd .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y6_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|lcr_stp2 (
// Location: LCCOMB_X62_Y6_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|comb~1 (
alta_slice \macro_inst|u_uart[1]|u_regs|lcr_stp2 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.C(\rv32.mem_ahb_hwdata[3] ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always5~0_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(SyncReset_X62_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|comb~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ));
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .mask = 16'h0088;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|lcr_stp2 .SyncLoadMux = 2'b01;
// Location: LCCOMB_X62_Y6_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector3~1 (
// Location: FF_X62_Y6_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_DATA~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|Selector3~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|always0~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .mask = 16'hF8F0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y6_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|always5~0 (
// Location: FF_X62_Y6_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|lcr_eps (
alta_slice \macro_inst|u_uart[1]|u_regs|lcr_eps (
	.A(\macro_inst|u_uart[1]|u_regs|apb_write~0_combout ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[0]|u_regs|always5~0_combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always5~0_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(SyncReset_X62_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|always5~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ));
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .mask = 16'hAA00;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|lcr_eps .SyncLoadMux = 2'b01;
// Location: LCCOMB_X62_Y6_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_stop_cnt~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY~q ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_STOP~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .mask = 16'hFBC0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y6_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_regs|lcr_pen (
// Location: LCCOMB_X62_Y6_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|Selector3~0 (
alta_slice \macro_inst|u_uart[1]|u_regs|lcr_pen (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_PARITY~q ),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[1] ),
	.D(\macro_inst|u_uart[1]|u_tx[4]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always5~0_combout_X62_Y6_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ),
	.SyncReset(SyncReset_X62_Y6_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y6_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|Selector3~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ));
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .mask = 16'h00AA;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .mode = "logic";
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_regs|lcr_pen .SyncLoadMux = 2'b01;
// Location: LCCOMB_X62_Y6_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_rx[5]|Add3~1 (
alta_slice \macro_inst|u_uart[1]|u_rx[5]|Add3~1 (
	.A(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_stp2~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_rx[5]|Add3~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .mask = 16'hFFAA;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_rx[5]|Add3~1 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y6_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[4]|tx_parity (
// Location: LCCOMB_X62_Y6_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[4]|tx_parity~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[4]|tx_parity (
	.A(\macro_inst|u_uart[1]|u_tx[4]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_tx[4]|tx_parity~0_combout ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_eps~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[4]|tx_parity~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ),
	.AsyncReset(AsyncReset_X62_Y6_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[4]|tx_parity~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[4]|tx_parity~q ));
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .mask = 16'h14BE;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[4]|tx_parity .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y6_N0
alta_clkenctrl clken_ctrl_X62_Y6_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y6_SIG_VCC ));
defparam clken_ctrl_X62_Y6_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y6_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y6_N0
alta_asyncctrl asyncreset_ctrl_X62_Y6_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y6_SIG ));
defparam asyncreset_ctrl_X62_Y6_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y6_N1
alta_clkenctrl clken_ctrl_X62_Y6_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_regs|always5~0_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_regs|always5~0_combout_X62_Y6_SIG_SIG ));
defparam clken_ctrl_X62_Y6_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y6_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y6_N1
alta_asyncctrl asyncreset_ctrl_X62_Y6_N1(.Din(), .Dout(AsyncReset_X62_Y6_GND));
defparam asyncreset_ctrl_X62_Y6_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y6_N0
alta_syncctrl syncreset_ctrl_X62_Y6(.Din(), .Dout(SyncReset_X62_Y6_GND));
defparam syncreset_ctrl_X62_Y6.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y6_N1
alta_syncctrl syncload_ctrl_X62_Y6(.Din(), .Dout(SyncLoad_X62_Y6_VCC));
defparam syncload_ctrl_X62_Y6.SyncCtrlMux = 2'b01;
// Location: FF_X62_Y7_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] (
// Location: LCCOMB_X62_Y7_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [1]),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [0]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] (
// Location: LCCOMB_X62_Y7_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5]~q ),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [6]),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~6_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [5]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .mask = 16'hCCF0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[7] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[1] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[0] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[5] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][5] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] (
// Location: LCCOMB_X62_Y7_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [3]),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [2]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[2] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] (
// Location: LCCOMB_X62_Y7_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.C(\rv32.mem_ahb_hwdata[2] ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|tx_bit~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(SyncReset_X62_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .mask = 16'hEECC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][2] .SyncLoadMux = 2'b01;
// Location: FF_X62_Y7_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] (
// Location: LCCOMB_X62_Y7_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~7 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6]~q ),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [7]),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~7_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [6]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .mask = 16'hAAF0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[6] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] (
// Location: LCCOMB_X62_Y7_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~5 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [5]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~5_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [4]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .mask = 16'hF0AA;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[4] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] (
// Location: LCCOMB_X62_Y7_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [4]),
	.C(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3]~q ),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~4_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [3]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .mask = 16'hF0CC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[3] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][3] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] (
// Location: LCCOMB_X62_Y7_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][1]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [2]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [1]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] (
// Location: LCCOMB_X62_Y7_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] (
	.A(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][7]~q ),
	.B(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[5]|fifo_rden~combout ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg~8_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg [7]));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .mask = 16'hAACC;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[7] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y7_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] (
	.A(),
	.B(),
	.C(vcc),
	.D(\rv32.mem_ahb_hwdata[6] ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6]__feeder__LutOut ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .mask = 16'hFF00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][6] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y7_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_regs|ibrd[0]~_wirecell (
// Location: FF_X62_Y7_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] (
alta_slice \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] (
	.A(vcc),
	.B(vcc),
	.C(\rv32.mem_ahb_hwdata[4] ),
	.D(\macro_inst|u_uart[1]|u_regs|ibrd [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4]~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y7_GND),
	.SyncReset(SyncReset_X62_Y7_GND),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y7_VCC),
	.LutOut(\macro_inst|u_uart[1]|u_regs|ibrd[0]~_wirecell_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4]~q ));
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .mask = 16'h00FF;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[5]|tx_fifo|fifo[1][4] .SyncLoadMux = 2'b01;

// Location: CLKENCTRL_X62_Y7_N0
alta_clkenctrl clken_ctrl_X62_Y7_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_shift_reg[3]~1_combout_X62_Y7_SIG_SIG ));
defparam clken_ctrl_X62_Y7_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y7_N0.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y7_N0
alta_asyncctrl asyncreset_ctrl_X62_Y7_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y7_SIG ));
defparam asyncreset_ctrl_X62_Y7_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y7_N1
alta_clkenctrl clken_ctrl_X62_Y7_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[5]|tx_fifo|wrreq~combout_X62_Y7_SIG_SIG ));
defparam clken_ctrl_X62_Y7_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y7_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y7_N1
alta_asyncctrl asyncreset_ctrl_X62_Y7_N1(.Din(), .Dout(AsyncReset_X62_Y7_GND));
defparam asyncreset_ctrl_X62_Y7_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y7_N0
alta_syncctrl syncreset_ctrl_X62_Y7(.Din(), .Dout(SyncReset_X62_Y7_GND));
defparam syncreset_ctrl_X62_Y7.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y7_N1
alta_syncctrl syncload_ctrl_X62_Y7(.Din(), .Dout(SyncLoad_X62_Y7_VCC));
defparam syncload_ctrl_X62_Y7.SyncCtrlMux = 2'b01;
// Location: FF_X62_Y8_N0
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[0] (
// Location: LCCOMB_X62_Y8_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[0]~16 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[0] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd[0]~_wirecell_combout ),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[0]~16_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[0]~17 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [0]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .mask = 16'h3333;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[0] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[5] (
// Location: LCCOMB_X62_Y8_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[5]~26 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[5] (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [5]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [5]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[4]~25 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [5]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[5]~26_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[5]~27 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [5]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .mask = 16'hA505;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[5] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[6] (
// Location: LCCOMB_X62_Y8_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[6]~28 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[6] (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [6]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [6]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[5]~27 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [6]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[6]~28_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[6]~29 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [6]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .mask = 16'h5AAF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[6] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[7] (
// Location: LCCOMB_X62_Y8_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[7]~30 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[7] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [7]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [7]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[6]~29 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [7]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[7]~30_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[7]~31 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [7]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .mask = 16'hC303;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[7] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[8] (
// Location: LCCOMB_X62_Y8_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[8]~32 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[8] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [8]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [8]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[7]~31 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [8]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[8]~32_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[8]~33 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [8]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[8] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[9] (
// Location: LCCOMB_X62_Y8_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[9]~34 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[9] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [9]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [9]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[8]~33 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [9]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[9]~34_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[9]~35 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [9]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .mask = 16'hC303;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[9] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N2
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[1] (
// Location: LCCOMB_X62_Y8_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[1]~18 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [1]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [1]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[0]~17 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[1]~18_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[1]~19 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [1]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .mask = 16'hC303;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[1] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[10] (
// Location: LCCOMB_X62_Y8_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[10]~36 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[10] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [10]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [10]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[9]~35 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [10]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[10]~36_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[10]~37 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [10]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[10] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[11] (
// Location: LCCOMB_X62_Y8_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[11]~38 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[11] (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [11]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [11]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[10]~37 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [11]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[11]~38_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[11]~39 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [11]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .mask = 16'hA505;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[11] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[12] (
// Location: LCCOMB_X62_Y8_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[12]~40 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[12] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [12]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [12]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[11]~39 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [12]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[12]~40_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[12]~41 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [12]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[12] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[13] (
// Location: LCCOMB_X62_Y8_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[13]~42 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[13] (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [13]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [13]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[12]~41 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [13]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[13]~42_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[13]~43 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [13]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .mask = 16'hA505;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[13] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N28
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[14] (
// Location: LCCOMB_X62_Y8_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[14]~44 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[14] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [14]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [14]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[13]~43 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [14]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[14]~44_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[14]~45 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [14]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[14] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N30
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[15] (
// Location: LCCOMB_X62_Y8_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[15]~46 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[15] (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [15]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [15]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[14]~45 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [15]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[15]~46_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [15]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .mask = 16'hA5A5;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[15] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[2] (
// Location: LCCOMB_X62_Y8_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[2]~20 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [2]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[1]~19 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[2]~20_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[2]~21 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [2]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[2] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[3] (
// Location: LCCOMB_X62_Y8_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[3]~22 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[3] (
	.A(\macro_inst|u_uart[1]|u_baud|i_cnt [3]),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [3]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[2]~21 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[3]~22_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[3]~23 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [3]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .mask = 16'hA505;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[3] .SyncLoadMux = 2'b10;
// Location: FF_X62_Y8_N8
// alta_lcell_ff \macro_inst|u_uart[1]|u_baud|i_cnt[4] (
// Location: LCCOMB_X62_Y8_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_baud|i_cnt[4]~24 (
alta_slice \macro_inst|u_uart[1]|u_baud|i_cnt[4] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_baud|i_cnt [4]),
	.C(\macro_inst|u_uart[1]|u_regs|ibrd [4]),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_baud|i_cnt[3]~23 ),
	.Qin(\macro_inst|u_uart[1]|u_baud|i_cnt [4]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ),
	.SyncReset(SyncReset_X62_Y8_GND),
	.ShiftData(),
	.SyncLoad(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ),
	.LutOut(\macro_inst|u_uart[1]|u_baud|i_cnt[4]~24_combout ),
	.Cout(\macro_inst|u_uart[1]|u_baud|i_cnt[4]~25 ),
	.Q(\macro_inst|u_uart[1]|u_baud|i_cnt [4]));
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .mask = 16'h3CCF;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .SyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_baud|i_cnt[4] .SyncLoadMux = 2'b10;

// Location: CLKENCTRL_X62_Y8_N0
alta_clkenctrl clken_ctrl_X62_Y8_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y8_SIG_VCC ));
defparam clken_ctrl_X62_Y8_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y8_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y8_N0
alta_asyncctrl asyncreset_ctrl_X62_Y8_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y8_SIG ));
defparam asyncreset_ctrl_X62_Y8_N0.AsyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y8_N0
alta_syncctrl syncreset_ctrl_X62_Y8(.Din(), .Dout(SyncReset_X62_Y8_GND));
defparam syncreset_ctrl_X62_Y8.SyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y8_N1
alta_syncctrl syncload_ctrl_X62_Y8(.Din(\macro_inst|u_uart[1]|u_baud|always0~0_combout ), .Dout(\macro_inst|u_uart[1]|u_baud|always0~0_combout__SyncLoad_X62_Y8_SIG ));
defparam syncload_ctrl_X62_Y8.SyncCtrlMux = 2'b10;
// Location: LCCOMB_X62_Y9_N0
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|Selector5~3_combout ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .mask = 16'h1BFF;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N10
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector4~1 (
// Location: FF_X62_Y9_N10
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|Selector4~0_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector4~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .mask = 16'hCCEC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N12
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] (
// Location: LCCOMB_X62_Y9_N12
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [0]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout_X62_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .mask = 16'hFAAF;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[1] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N14
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] (
// Location: LCCOMB_X62_Y9_N14
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0]~4 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [0]),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0]~4_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0]~5 ),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .mask = 16'h6688;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y9_N16
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] (
// Location: LCCOMB_X62_Y9_N16
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1]~6 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [1]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[0]~5 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [1]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1]~6_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1]~7 ),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [1]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .mask = 16'h3C3F;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1] .SyncLoadMux = 2'b00;
// Location: FF_X62_Y9_N18
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] (
// Location: LCCOMB_X62_Y9_N18
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2]~8 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] (
	.A(vcc),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [2]),
	.C(vcc),
	.D(vcc),
	.Cin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[1]~7 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2]~8_combout ),
	.Cout(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2]~9 ),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .mask = 16'hC30C;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .CarryEnb = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y9_N2
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.D(vcc),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .mask = 16'hF8F8;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1 .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N20
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] (
// Location: LCCOMB_X62_Y9_N20
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3]~10 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] (
	.A(vcc),
	.B(vcc),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [3]),
	.Cin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[2]~9 ),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [3]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y9_SIG ),
	.ShiftData(),
	.SyncLoad(SyncLoad_X62_Y9_GND),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3]~10_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [3]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .mask = 16'h0FF0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .mode = "ripple";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .modeMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .BypassEn = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .SyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt[3] .SyncLoadMux = 2'b00;
// Location: LCCOMB_X62_Y9_N22
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector3~1 (
// Location: FF_X62_Y9_N22
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|Selector3~0_combout ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|always0~0_combout ),
	.D(\macro_inst|u_uart[1]|u_regs|lcr_pen~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector3~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .mask = 16'hECCC;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N24
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] (
// Location: LCCOMB_X62_Y9_N24
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~2 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.B(vcc),
	.C(vcc),
	.D(vcc),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [0]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout_X62_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~2_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [0]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .mask = 16'hAFAF;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[0] .SyncLoadMux = 2'bxx;
// Location: FF_X62_Y9_N26
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] (
// Location: LCCOMB_X62_Y9_N26
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~3 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [0]),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [1]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [2]),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout_X62_Y9_SIG_SIG ),
	.AsyncReset(AsyncReset_X62_Y9_GND),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt~3_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [2]));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .mask = 16'hFAEB;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .AsyncResetMux = 2'b00;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2] .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N28
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_PARITY~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_STOP~q ),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_stop_cnt~q ),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector4~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .mask = 16'hECAC;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|Selector4~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N30
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|always0~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|always0~0 (
	.A(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [2]),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [0]),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|always0~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .mask = 16'h0010;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|always0~0 .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N4
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|always6~1 (
// Location: FF_X62_Y9_N4
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_bit (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_bit (
	.A(vcc),
	.B(vcc),
	.C(\macro_inst|u_uart[1]|u_tx[3]|always6~0_combout ),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [3]),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|always6~1_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .mask = 16'hF000;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_bit .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N6
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|Selector2~0 (
// Location: FF_X62_Y9_N6
// alta_lcell_ff \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA (
	.A(\macro_inst|u_uart[1]|u_tx[3]|always0~0_combout ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_bit~q ),
	.C(vcc),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_START~q ),
	.Cin(),
	.Qin(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ),
	.Clk(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ),
	.AsyncReset(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|Selector2~0_combout ),
	.Cout(),
	.Q(\macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA~q ));
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .mask = 16'hDC50;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .FeedbackMux = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .AsyncResetMux = 2'b10;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|tx_state.UART_DATA .SyncLoadMux = 2'bxx;
// Location: LCCOMB_X62_Y9_N8
// alta_lcell_comb \macro_inst|u_uart[1]|u_tx[3]|always6~0 (
alta_slice \macro_inst|u_uart[1]|u_tx[3]|always6~0 (
	.A(\macro_inst|u_uart[1]|u_baud|baud16~q ),
	.B(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [2]),
	.C(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [0]),
	.D(\macro_inst|u_uart[1]|u_tx[3]|tx_baud_cnt [1]),
	.Cin(),
	.Qin(),
	.Clk(),
	.AsyncReset(),
	.SyncReset(),
	.ShiftData(),
	.SyncLoad(),
	.LutOut(\macro_inst|u_uart[1]|u_tx[3]|always6~0_combout ),
	.Cout(),
	.Q());
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .mask = 16'h8000;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .mode = "logic";
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .modeMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .FeedbackMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .ShiftMux = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .BypassEn = 1'b0;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .CarryEnb = 1'b1;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .AsyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .SyncResetMux = 2'bxx;
defparam \macro_inst|u_uart[1]|u_tx[3]|always6~0 .SyncLoadMux = 2'bxx;

// Location: CLKENCTRL_X62_Y9_N0
alta_clkenctrl clken_ctrl_X62_Y9_N0(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp_X62_Y9_SIG_VCC ));
defparam clken_ctrl_X62_Y9_N0.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y9_N0.ClkEnMux = 2'b01;

// Location: ASYNCCTRL_X62_Y9_N0
alta_asyncctrl asyncreset_ctrl_X62_Y9_N0(.Din(\sys_resetn~clkctrl_outclk ), .Dout(\sys_resetn~clkctrl_outclk__AsyncReset_X62_Y9_SIG ));
defparam asyncreset_ctrl_X62_Y9_N0.AsyncCtrlMux = 2'b10;

// Location: CLKENCTRL_X62_Y9_N1
alta_clkenctrl clken_ctrl_X62_Y9_N1(.ClkIn(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp ), .ClkEn(\macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout ), .ClkOut(\auto_generated_inst.hbo_22_717df45ba12dbb20_bp__macro_inst|u_uart[1]|u_tx[3]|tx_data_cnt[2]~1_combout_X62_Y9_SIG_SIG ));
defparam clken_ctrl_X62_Y9_N1.ClkMux = 2'b10;
defparam clken_ctrl_X62_Y9_N1.ClkEnMux = 2'b10;

// Location: ASYNCCTRL_X62_Y9_N1
alta_asyncctrl asyncreset_ctrl_X62_Y9_N1(.Din(), .Dout(AsyncReset_X62_Y9_GND));
defparam asyncreset_ctrl_X62_Y9_N1.AsyncCtrlMux = 2'b00;

// Location: SYNCCTRL_X62_Y9_N0
alta_syncctrl syncreset_ctrl_X62_Y9(.Din(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout ), .Dout(\macro_inst|u_uart[1]|u_tx[3]|tx_stop~combout__SyncReset_X62_Y9_SIG ));
defparam syncreset_ctrl_X62_Y9.SyncCtrlMux = 2'b10;

// Location: SYNCCTRL_X62_Y9_N1
alta_syncctrl syncload_ctrl_X62_Y9(.Din(), .Dout(SyncLoad_X62_Y9_GND));
defparam syncload_ctrl_X62_Y9.SyncCtrlMux = 2'b00;
endmodule