startup_gd32f10x_hd.s 17 KB

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  1. ;/*!
  2. ; \file startup_gd32f10x_hd.s
  3. ; \brief start up file
  4. ;
  5. ; \version 2014-12-26, V1.0.0, firmware for GD32F10x
  6. ; \version 2017-06-20, V2.0.0, firmware for GD32F10x
  7. ; \version 2018-07-31, V2.1.0, firmware for GD32F10x
  8. ;*/
  9. ;
  10. ;/*
  11. ; Copyright (c) 2018, GigaDevice Semiconductor Inc.
  12. ;
  13. ; All rights reserved.
  14. ;
  15. ; Redistribution and use in source and binary forms, with or without modification,
  16. ;are permitted provided that the following conditions are met:
  17. ;
  18. ; 1. Redistributions of source code must retain the above copyright notice, this
  19. ; list of conditions and the following disclaimer.
  20. ; 2. Redistributions in binary form must reproduce the above copyright notice,
  21. ; this list of conditions and the following disclaimer in the documentation
  22. ; and/or other materials provided with the distribution.
  23. ; 3. Neither the name of the copyright holder nor the names of its contributors
  24. ; may be used to endorse or promote products derived from this software without
  25. ; specific prior written permission.
  26. ;
  27. ; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  28. ;AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  29. ;WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
  30. ;IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
  31. ;INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
  32. ;NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  33. ;PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  34. ;WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  35. ;ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
  36. ;OF SUCH DAMAGE.
  37. ;*/
  38. ; <h> Stack Configuration
  39. ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
  40. ; </h>
  41. Stack_Size EQU 0x00002000
  42. AREA STACK, NOINIT, READWRITE, ALIGN = 3
  43. Stack_Mem SPACE Stack_Size
  44. __initial_sp
  45. ; <h> Heap Configuration
  46. ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
  47. ; </h>
  48. Heap_Size EQU 0x00001000
  49. AREA HEAP, NOINIT, READWRITE, ALIGN = 3
  50. __heap_base
  51. Heap_Mem SPACE Heap_Size
  52. __heap_limit
  53. PRESERVE8
  54. THUMB
  55. ; /* reset Vector Mapped to at Address 0 */
  56. AREA RESET, DATA, READONLY
  57. EXPORT __Vectors
  58. EXPORT __Vectors_End
  59. EXPORT __Vectors_Size
  60. __Vectors DCD __initial_sp ; Top of Stack
  61. DCD Reset_Handler ; Reset Handler
  62. DCD NMI_Handler ; NMI Handler
  63. DCD HardFault_Handler ; Hard Fault Handler
  64. DCD MemManage_Handler ; MPU Fault Handler
  65. DCD BusFault_Handler ; Bus Fault Handler
  66. DCD UsageFault_Handler ; Usage Fault Handler
  67. DCD 0 ; Reserved
  68. DCD 0 ; Reserved
  69. DCD 0 ; Reserved
  70. DCD 0 ; Reserved
  71. DCD SVC_Handler ; SVCall Handler
  72. DCD DebugMon_Handler ; Debug Monitor Handler
  73. DCD 0 ; Reserved
  74. DCD PendSV_Handler ; PendSV Handler
  75. ; DCD OS_CPU_PendSVHandler ; PendSV Handler
  76. DCD SysTick_Handler ; SysTick Handler
  77. ; /* external interrupts handler */
  78. DCD WWDGT_IRQHandler ; 16:Window Watchdog Timer
  79. DCD LVD_IRQHandler ; 17:LVD through EXTI Line detect
  80. DCD TAMPER_IRQHandler ; 18:Tamper Interrupt
  81. DCD RTC_IRQHandler ; 19:RTC through EXTI Line
  82. DCD FMC_IRQHandler ; 20:FMC
  83. DCD RCU_IRQHandler ; 21:RCU
  84. DCD EXTI0_IRQHandler ; 22:EXTI Line 0
  85. DCD EXTI1_IRQHandler ; 23:EXTI Line 1
  86. DCD EXTI2_IRQHandler ; 24:EXTI Line 2
  87. DCD EXTI3_IRQHandler ; 25:EXTI Line 3
  88. DCD EXTI4_IRQHandler ; 26:EXTI Line 4
  89. DCD DMA0_Channel0_IRQHandler ; 27:DMA0 Channel 0
  90. DCD DMA0_Channel1_IRQHandler ; 28:DMA0 Channel 1
  91. DCD DMA0_Channel2_IRQHandler ; 29:DMA0 Channel 2
  92. DCD DMA0_Channel3_IRQHandler ; 30:DMA0 Channel 3
  93. DCD DMA0_Channel4_IRQHandler ; 31:DMA0 Channel 4
  94. DCD DMA0_Channel5_IRQHandler ; 32:DMA0 Channel 5
  95. DCD DMA0_Channel6_IRQHandler ; 33:DMA0 Channel 6
  96. DCD ADC0_1_IRQHandler ; 34:ADC0 and ADC1
  97. DCD USBD_HP_CAN0_TX_IRQHandler ; 35:USBD and CAN0 TX
  98. DCD USBD_LP_CAN0_RX0_IRQHandler ; 36:USBD and CAN0 RX0
  99. DCD CAN0_RX1_IRQHandler ; 37:CAN0 RX1
  100. DCD CAN0_EWMC_IRQHandler ; 38:CAN0 EWMC
  101. DCD EXTI5_9_IRQHandler ; 39:EXTI Line 5 to EXTI Line 9
  102. DCD TIMER0_BRK_IRQHandler ; 40:TIMER0 Break
  103. DCD TIMER0_UP_IRQHandler ; 41:TIMER0 Update
  104. DCD TIMER0_TRG_CMT_IRQHandler ; 42:TIMER0 Trigger and Commutation
  105. DCD TIMER0_Channel_IRQHandler ; 43:TIMER0 Channel Capture Compare
  106. DCD TIMER1_IRQHandler ; 44:TIMER1
  107. DCD TIMER2_IRQHandler ; 45:TIMER2
  108. DCD TIMER3_IRQHandler ; 46:TIMER3
  109. DCD I2C0_EV_IRQHandler ; 47:I2C0 Event
  110. DCD I2C0_ER_IRQHandler ; 48:I2C0 Error
  111. DCD I2C1_EV_IRQHandler ; 49:I2C1 Event
  112. DCD I2C1_ER_IRQHandler ; 50:I2C1 Error
  113. DCD SPI0_IRQHandler ; 51:SPI0
  114. DCD SPI1_IRQHandler ; 52:SPI1
  115. DCD USART0_IRQHandler ; 53:USART0
  116. DCD USART1_IRQHandler ; 54:USART1
  117. DCD USART2_IRQHandler ; 55:USART2
  118. DCD EXTI10_15_IRQHandler ; 56:EXTI Line 10 to EXTI Line 15
  119. DCD RTC_Alarm_IRQHandler ; 57:RTC Alarm through EXTI Line
  120. DCD USBD_WKUP_IRQHandler ; 58:USBD WakeUp from suspend through EXTI Line
  121. DCD TIMER7_BRK_IRQHandler ; 59:TIMER7 Break Interrupt
  122. DCD TIMER7_UP_IRQHandler ; 60:TIMER7 Update Interrupt
  123. DCD TIMER7_TRG_CMT_IRQHandler ; 61:TIMER7 Trigger and Commutation Interrupt
  124. DCD TIMER7_Channel_IRQHandler ; 62:TIMER7 Channel Capture Compare
  125. DCD ADC2_IRQHandler ; 63:ADC2
  126. DCD EXMC_IRQHandler ; 64:EXMC
  127. DCD SDIO_IRQHandler ; 65:SDIO
  128. DCD TIMER4_IRQHandler ; 66:TIMER4
  129. DCD SPI2_IRQHandler ; 67:SPI2
  130. DCD UART3_IRQHandler ; 68:UART3
  131. DCD UART4_IRQHandler ; 69:UART4
  132. DCD TIMER5_IRQHandler ; 70:TIMER5
  133. DCD TIMER6_IRQHandler ; 71:TIMER6
  134. DCD DMA1_Channel0_IRQHandler ; 72:DMA1 Channel0
  135. DCD DMA1_Channel1_IRQHandler ; 73:DMA1 Channel1
  136. DCD DMA1_Channel2_IRQHandler ; 74:DMA1 Channel2
  137. DCD DMA1_Channel3_4_IRQHandler ; 75:DMA1 Channel3 and Channel4
  138. __Vectors_End
  139. __Vectors_Size EQU __Vectors_End - __Vectors
  140. AREA |.text|, CODE, READONLY
  141. ;/* reset Handler */
  142. Reset_Handler PROC
  143. EXPORT Reset_Handler [WEAK]
  144. IMPORT __main
  145. IMPORT SystemInit
  146. LDR R0, =SystemInit
  147. BLX R0
  148. LDR R0, =__main
  149. BX R0
  150. ENDP
  151. ;/* dummy Exception Handlers */
  152. NMI_Handler PROC
  153. EXPORT NMI_Handler [WEAK]
  154. B .
  155. ENDP
  156. HardFault_Handler PROC
  157. EXPORT HardFault_Handler [WEAK]
  158. B .
  159. ENDP
  160. MemManage_Handler PROC
  161. EXPORT MemManage_Handler [WEAK]
  162. B .
  163. ENDP
  164. BusFault_Handler PROC
  165. EXPORT BusFault_Handler [WEAK]
  166. B .
  167. ENDP
  168. UsageFault_Handler PROC
  169. EXPORT UsageFault_Handler [WEAK]
  170. B .
  171. ENDP
  172. SVC_Handler PROC
  173. EXPORT SVC_Handler [WEAK]
  174. B .
  175. ENDP
  176. DebugMon_Handler PROC
  177. EXPORT DebugMon_Handler [WEAK]
  178. B .
  179. ENDP
  180. PendSV_Handler PROC
  181. EXPORT PendSV_Handler [WEAK]
  182. B .
  183. ENDP
  184. ;OS_CPU_PendSVHandler PROC
  185. ; EXPORT OS_CPU_PendSVHandler [WEAK]
  186. ; B .
  187. ; ENDP
  188. SysTick_Handler PROC
  189. EXPORT SysTick_Handler [WEAK]
  190. B .
  191. ENDP
  192. Default_Handler PROC
  193. ; /* external interrupts handler */
  194. EXPORT WWDGT_IRQHandler [WEAK]
  195. EXPORT LVD_IRQHandler [WEAK]
  196. EXPORT TAMPER_IRQHandler [WEAK]
  197. EXPORT RTC_IRQHandler [WEAK]
  198. EXPORT FMC_IRQHandler [WEAK]
  199. EXPORT RCU_IRQHandler [WEAK]
  200. EXPORT EXTI0_IRQHandler [WEAK]
  201. EXPORT EXTI1_IRQHandler [WEAK]
  202. EXPORT EXTI2_IRQHandler [WEAK]
  203. EXPORT EXTI3_IRQHandler [WEAK]
  204. EXPORT EXTI4_IRQHandler [WEAK]
  205. EXPORT DMA0_Channel0_IRQHandler [WEAK]
  206. EXPORT DMA0_Channel1_IRQHandler [WEAK]
  207. EXPORT DMA0_Channel2_IRQHandler [WEAK]
  208. EXPORT DMA0_Channel3_IRQHandler [WEAK]
  209. EXPORT DMA0_Channel4_IRQHandler [WEAK]
  210. EXPORT DMA0_Channel5_IRQHandler [WEAK]
  211. EXPORT DMA0_Channel6_IRQHandler [WEAK]
  212. EXPORT ADC0_1_IRQHandler [WEAK]
  213. EXPORT USBD_HP_CAN0_TX_IRQHandler [WEAK]
  214. EXPORT USBD_LP_CAN0_RX0_IRQHandler [WEAK]
  215. EXPORT CAN0_RX1_IRQHandler [WEAK]
  216. EXPORT CAN0_EWMC_IRQHandler [WEAK]
  217. EXPORT EXTI5_9_IRQHandler [WEAK]
  218. EXPORT TIMER0_BRK_IRQHandler [WEAK]
  219. EXPORT TIMER0_UP_IRQHandler [WEAK]
  220. EXPORT TIMER0_TRG_CMT_IRQHandler [WEAK]
  221. EXPORT TIMER0_Channel_IRQHandler [WEAK]
  222. EXPORT TIMER1_IRQHandler [WEAK]
  223. EXPORT TIMER2_IRQHandler [WEAK]
  224. EXPORT TIMER3_IRQHandler [WEAK]
  225. EXPORT I2C0_EV_IRQHandler [WEAK]
  226. EXPORT I2C0_ER_IRQHandler [WEAK]
  227. EXPORT I2C1_EV_IRQHandler [WEAK]
  228. EXPORT I2C1_ER_IRQHandler [WEAK]
  229. EXPORT SPI0_IRQHandler [WEAK]
  230. EXPORT SPI1_IRQHandler [WEAK]
  231. EXPORT USART0_IRQHandler [WEAK]
  232. EXPORT USART1_IRQHandler [WEAK]
  233. EXPORT USART2_IRQHandler [WEAK]
  234. EXPORT EXTI10_15_IRQHandler [WEAK]
  235. EXPORT RTC_Alarm_IRQHandler [WEAK]
  236. EXPORT USBD_WKUP_IRQHandler [WEAK]
  237. EXPORT TIMER7_BRK_IRQHandler [WEAK]
  238. EXPORT TIMER7_UP_IRQHandler [WEAK]
  239. EXPORT TIMER7_TRG_CMT_IRQHandler [WEAK]
  240. EXPORT TIMER7_Channel_IRQHandler [WEAK]
  241. EXPORT ADC2_IRQHandler [WEAK]
  242. EXPORT EXMC_IRQHandler [WEAK]
  243. EXPORT SDIO_IRQHandler [WEAK]
  244. EXPORT TIMER4_IRQHandler [WEAK]
  245. EXPORT SPI2_IRQHandler [WEAK]
  246. EXPORT UART3_IRQHandler [WEAK]
  247. EXPORT UART4_IRQHandler [WEAK]
  248. EXPORT TIMER5_IRQHandler [WEAK]
  249. EXPORT TIMER6_IRQHandler [WEAK]
  250. EXPORT DMA1_Channel0_IRQHandler [WEAK]
  251. EXPORT DMA1_Channel1_IRQHandler [WEAK]
  252. EXPORT DMA1_Channel2_IRQHandler [WEAK]
  253. EXPORT DMA1_Channel3_4_IRQHandler [WEAK]
  254. ;/* external interrupts handler */
  255. WWDGT_IRQHandler
  256. LVD_IRQHandler
  257. TAMPER_IRQHandler
  258. RTC_IRQHandler
  259. FMC_IRQHandler
  260. RCU_IRQHandler
  261. EXTI0_IRQHandler
  262. EXTI1_IRQHandler
  263. EXTI2_IRQHandler
  264. EXTI3_IRQHandler
  265. EXTI4_IRQHandler
  266. DMA0_Channel0_IRQHandler
  267. DMA0_Channel1_IRQHandler
  268. DMA0_Channel2_IRQHandler
  269. DMA0_Channel3_IRQHandler
  270. DMA0_Channel4_IRQHandler
  271. DMA0_Channel5_IRQHandler
  272. DMA0_Channel6_IRQHandler
  273. ADC0_1_IRQHandler
  274. USBD_HP_CAN0_TX_IRQHandler
  275. USBD_LP_CAN0_RX0_IRQHandler
  276. CAN0_RX1_IRQHandler
  277. CAN0_EWMC_IRQHandler
  278. EXTI5_9_IRQHandler
  279. TIMER0_BRK_IRQHandler
  280. TIMER0_UP_IRQHandler
  281. TIMER0_TRG_CMT_IRQHandler
  282. TIMER0_Channel_IRQHandler
  283. TIMER1_IRQHandler
  284. TIMER2_IRQHandler
  285. TIMER3_IRQHandler
  286. I2C0_EV_IRQHandler
  287. I2C0_ER_IRQHandler
  288. I2C1_EV_IRQHandler
  289. I2C1_ER_IRQHandler
  290. SPI0_IRQHandler
  291. SPI1_IRQHandler
  292. USART0_IRQHandler
  293. USART1_IRQHandler
  294. USART2_IRQHandler
  295. EXTI10_15_IRQHandler
  296. RTC_Alarm_IRQHandler
  297. USBD_WKUP_IRQHandler
  298. TIMER7_BRK_IRQHandler
  299. TIMER7_UP_IRQHandler
  300. TIMER7_TRG_CMT_IRQHandler
  301. TIMER7_Channel_IRQHandler
  302. ADC2_IRQHandler
  303. EXMC_IRQHandler
  304. SDIO_IRQHandler
  305. TIMER4_IRQHandler
  306. SPI2_IRQHandler
  307. UART3_IRQHandler
  308. UART4_IRQHandler
  309. TIMER5_IRQHandler
  310. TIMER6_IRQHandler
  311. DMA1_Channel0_IRQHandler
  312. DMA1_Channel1_IRQHandler
  313. DMA1_Channel2_IRQHandler
  314. DMA1_Channel3_4_IRQHandler
  315. B .
  316. ENDP
  317. ALIGN
  318. ; user Initial Stack & Heap
  319. IF :DEF:__MICROLIB
  320. EXPORT __initial_sp
  321. EXPORT __heap_base
  322. EXPORT __heap_limit
  323. ELSE
  324. IMPORT __use_two_region_memory
  325. EXPORT __user_initial_stackheap
  326. __user_initial_stackheap PROC
  327. LDR R0, = Heap_Mem
  328. LDR R1, =(Stack_Mem + Stack_Size)
  329. LDR R2, = (Heap_Mem + Heap_Size)
  330. LDR R3, = Stack_Mem
  331. BX LR
  332. ENDP
  333. ALIGN
  334. ENDIF
  335. END