01042002

.gitignore

@@ -0,0 +1,12 @@
+.pio
+.vscode/.browse.c_cpp.db*
+.vscode/c_cpp_properties.json
+.vscode/launch.json
+.vscode/ipch
+*.json
+logic/alta_db
+logic/alta_logs
+logic/db
+logic/incremental_db
+logic/quartus_logs
+logic/simulation

PT_0104.ve

@@ -0,0 +1,50 @@
+SYSCLK 120
+
+HSECLK 8
+
+
+#串口初始化
+UART0_UARTRXD PIN_69    #DEGUG口
+UART0_UARTTXD PIN_68
+
+#4G口
+UART1_UARTRXD PIN_83    #4G串口 AT_NET2MCU
+UART1_UARTTXD PIN_80    #AT_MCU2NET
+
+#485口
+UART2_UARTRXD PIN_26    #RS485_BUS2MCU
+UART2_UARTTXD PIN_25    #RS485_MCU2BUS
+GPIO1_2 PIN_24          #RS485_CTL
+
+
+#LED_RUN  LED_MOD 初始化
+GPIO1_0 PIN_3 # LED_RUN
+GPIO1_1 PIN_2 # LED_MOD
+GPIO1_3 PIN_4 #LED_PWR
+
+
+#按键
+GPIO1_4 PIN_92 #MCU_KEY1
+GPIO1_5 PIN_91 #MCU_KEY2
+GPIO1_6 PIN_88 #MCU_KEY3
+
+
+#硬件id
+GPIO0_4 PIN_15
+GPIO0_5 PIN_16
+GPIO0_6 PIN_17
+GPIO0_7 PIN_18
+
+#4G模块
+GPIO5_0         PIN_23 # +VDD_EXT 检测4G模块的电压，判断4G模块是否上电
+GPIO5_1         PIN_93 #MCU_NET_PWR
+GPIO5_2         PIN_98 #MCU_NET_RST
+GPIO5_3         PIN_7  #NET_DETECH 检测4G是否焊接
+
+#i2c eeprom
+GPIO2_0         PIN_97 #I2C_WP
+GPIO2_1         PIN_95 #I2C_SCL
+GPIO2_2         PIN_96 #I2C_SDA
+
+
+

logic/PT_0104.asf

@@ -0,0 +1,13 @@
+# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
+if { [info exists BOARD_PLL_CLKIN] } {
+  if { $BOARD_PLL_CLKIN == "PIN_OSC" } {
+    set_config -loc 18 0 0 CFG_RCOSC_EN 1'b1
+  }
+}
+if { [info exists USB0_MODE] } {
+  alta::tcl_info "USB0_MODE = $USB0_MODE"
+  set_config -loc 0 1 3 CFG_PULLUP_ENB 1'b0
+  set_config -loc 0 1 3 CFG_PULLDN_ENB 1'b0
+}
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIN_26
+# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<

logic/PT_0104.hx

@@ -0,0 +1,24 @@
+#ifndef _AGM_BOARD_INFO
+#define _AGM_BOARD_INFO
+
+#ifndef BOARD_HSI_FREQUENCY
+#define BOARD_HSI_FREQUENCY 10000000
+#endif
+
+#ifndef BOARD_HSE_FREQUENCY
+#define BOARD_HSE_FREQUENCY 8000000
+#endif
+
+#ifndef BOARD_PLL_FREQUENCY
+#define BOARD_PLL_FREQUENCY 120000000
+#endif
+
+#ifndef BOARD_BUS_FREQUENCY
+#define BOARD_BUS_FREQUENCY 120000000
+#endif
+
+#ifndef BOARD_PLL_CLKIN
+#define BOARD_PLL_CLKIN PIN_HSE
+#endif
+
+#endif

logic/PT_0104.inc

@@ -0,0 +1,282 @@
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logic/PT_0104.post.asf

@@ -0,0 +1,2 @@
+# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
+# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<

logic/PT_0104.pre.asf

@@ -0,0 +1,6 @@
+# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>
+set BOARD_PLL_CLKIN PIN_HSE
+set db_io_name_priority true
+set ip_pll_vco_lowpower true
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION "ON"
+# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<

logic/PT_0104.proj

@@ -0,0 +1,40 @@
+[GuiMigrateSetupPage]
+design=PT_0104
+device=AGRV2KL100
+
+[GuiMigrateRunPage]
+fitting=1
+fitter=5
+effort=2
+skew=2
+isMC=false
+count=
+jobs=
+seed=
+retry=0
+holdx=0
+skope=0
+preset=0
+adjust=0
+target=0
+tuning=0
+corner=0
+flow=0
+orgPlace=false
+quartusSdc=true
+probeForce=false
+probeState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\x2\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x2i\0\0\0\x2\0\x1\x1\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\0\0\0K\0\0\0\x4\0\0\0\0\0\0\0\x2\0\0\x1\xc2\0\0\0\x1\0\0\0\0\0\0\0\xa7\0\0\0\x1\0\0\0\0)
+probeCount=5
+probe0From=
+probe0Pad=
+probe1From=
+probe1Pad=
+probe2From=
+probe2Pad=
+probe3From=
+probe3Pad=
+probe4From=
+probe4Pad=
+
+[MainWindow]
+recentFile.0=

logic/PT_0104.qpf

@@ -0,0 +1,3 @@
+#QUARTUS_VERSION = "11.1"
+PROJECT_REVISION = "PT_0104"
+

logic/PT_0104.qsf

@@ -0,0 +1,141 @@
+# Design name Assignments, replace __design_name__ with actual design name
+# ========================
+set_global_assignment -name FAMILY "Cyclone IV E"
+set_global_assignment -name DEVICE EP4CE75F29C8
+
+set_global_assignment -name TOP_LEVEL_ENTITY "top"
+
+set_global_assignment -name VERILOG_FILE PT_0104.v
+set_global_assignment -name VERILOG_FILE PT_0104_fpga.v
+set_global_assignment -name VERILOG_FILE "C:\\Users\\61552\\.platformio\\packages\\tool-agrv_logic\\etc\\arch\\rodinia\\alta_sim.v"
+
+set_global_assignment -name SDC_FILE .\\PT_0104.sdc
+
+
+#set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE "atom_netlists/__design_name__.vqm"
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:37:04  JANUARY 04, 2013"
+set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./quartus_logs
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
+#set_global_assignment -name SMART_RECOMPILE ON
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+#set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
+#set_global_assignment -name AUTO_ROM_RECOGNITION OFF
+#set_global_assignment -name AUTO_RAM_RECOGNITION OFF
+#set_global_assignment -name MAX_RAM_BLOCKS_M4K 0
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF
+# set_instance_assignment -name PRESERVE_REGISTER ON -to *
+#set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER ON -to *
+#set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 0 -to *
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
+set_global_assignment -name ECO_OPTIMIZE_TIMING ON
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
+set_global_assignment -name SEED 1
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 6
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+#set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
+
+# LogicLock Region Assignments
+# ============================
+set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# start EDA_TOOL_SETTINGS(eda_simulation)
+# ---------------------------------------
+
+# EDA Netlist Writer Assignments
+# ==============================
+set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
+set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
+
+# end EDA_TOOL_SETTINGS(eda_simulation)
+# -------------------------------------
+
+# start DESIGN_PARTITION(Top)
+# ---------------------------
+
+# Incremental Compilation Assignments
+# ===================================
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
+
+# end DESIGN_PARTITION(Top)
+# -------------------------
+
+set_global_assignment -name LL_ENABLED ON -section_id core_logic
+set_global_assignment -name LL_AUTO_SIZE OFF -section_id core_logic
+set_global_assignment -name LL_STATE LOCKED -section_id core_logic
+set_global_assignment -name LL_RESERVED OFF -section_id core_logic
+set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id core_logic
+set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id core_logic
+set_global_assignment -name LL_PR_REGION OFF -section_id core_logic
+set_global_assignment -name LL_WIDTH 20 -section_id core_logic
+set_global_assignment -name LL_HEIGHT 12 -section_id core_logic
+set_global_assignment -name LL_ORIGIN X43_Y1 -section_id core_logic
+set_global_assignment -name LL_MEMBER_OF core_logic -section_id core_logic
+
+set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_WIDTH 13 -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_HEIGHT 8 -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_ORIGIN X43_Y5 -section_id LOGIC_RESERVE_0
+
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
+set_global_assignment -name MAX_RAM_BLOCKS_M4K 4
+
+
+set_global_assignment -name PARTITION_COLOR 52377 -section_id rv32 -tag alta_auto
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id rv32 -tag alta_auto
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id rv32 -tag alta_auto
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
+set_instance_assignment -name PARTITION_HIERARCHY rv32 -to "alta_rv32:rv32" -section_id rv32
+set_global_assignment -name LL_CORE_ONLY OFF -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id LOGIC_RESERVE_0
+set_global_assignment -name LL_CORE_ONLY OFF -section_id core_logic
+set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id core_logic

logic/PT_0104.sdc

@@ -0,0 +1,13 @@
+# pio_begin
+if { ! [info exists ::HSI_PERIOD] } {
+  set ::HSI_PERIOD 100.0
+}
+create_clock -name PIN_HSI -period $::HSI_PERIOD [get_ports PIN_HSI]
+set_clock_groups -asynchronous -group PIN_HSI
+if { ! [info exists ::HSE_PERIOD] } {
+  set ::HSE_PERIOD 125.0
+}
+create_clock -name PIN_HSE -period $::HSE_PERIOD [get_ports PIN_HSE]
+set_clock_groups -asynchronous -group PIN_HSE
+derive_pll_clocks -create_base_clocks
+# pio_end

logic/PT_0104.v

@@ -0,0 +1,480 @@
+`timescale 1 ps/ 1 ps
+
+module top (
+  PIN_15,
+  PIN_16,
+  PIN_17,
+  PIN_18,
+  PIN_2,
+  PIN_23,
+  PIN_24,
+  PIN_25,
+  PIN_26,
+  PIN_3,
+  PIN_4,
+  PIN_68,
+  PIN_69,
+  PIN_7,
+  PIN_80,
+  PIN_83,
+  PIN_88,
+  PIN_91,
+  PIN_92,
+  PIN_93,
+  PIN_95,
+  PIN_96,
+  PIN_97,
+  PIN_98,
+  PIN_HSE,
+  PIN_HSI,
+  PIN_OSC
+);
+inout PIN_15;
+inout PIN_16;
+inout PIN_17;
+inout PIN_18;
+inout PIN_2;
+inout PIN_23;
+inout PIN_24;
+output PIN_25;
+input PIN_26;
+inout PIN_3;
+inout PIN_4;
+output PIN_68;
+input PIN_69;
+inout PIN_7;
+output PIN_80;
+input PIN_83;
+inout PIN_88;
+inout PIN_91;
+inout PIN_92;
+inout PIN_93;
+inout PIN_95;
+inout PIN_96;
+inout PIN_97;
+inout PIN_98;
+input PIN_HSE;
+input PIN_HSI;
+input PIN_OSC;
+
+// GPIO0_4, GPIO0_4
+assign PIN_15_in = PIN_15;
+wire PIN_15_out_en;
+wire PIN_15_out_data;
+assign PIN_15 = PIN_15_out_en ? PIN_15_out_data : 1'bz;
+
+// GPIO0_5, GPIO0_5
+assign PIN_16_in = PIN_16;
+wire PIN_16_out_en;
+wire PIN_16_out_data;
+assign PIN_16 = PIN_16_out_en ? PIN_16_out_data : 1'bz;
+
+// GPIO0_6, GPIO0_6
+assign PIN_17_in = PIN_17;
+wire PIN_17_out_en;
+wire PIN_17_out_data;
+assign PIN_17 = PIN_17_out_en ? PIN_17_out_data : 1'bz;
+
+// GPIO0_7, GPIO0_7
+assign PIN_18_in = PIN_18;
+wire PIN_18_out_en;
+wire PIN_18_out_data;
+assign PIN_18 = PIN_18_out_en ? PIN_18_out_data : 1'bz;
+
+// GPIO1_1, GPIO1_1
+assign PIN_2_in = PIN_2;
+wire PIN_2_out_en;
+wire PIN_2_out_data;
+assign PIN_2 = PIN_2_out_en ? PIN_2_out_data : 1'bz;
+
+// GPIO5_0, GPIO5_0
+assign PIN_23_in = PIN_23;
+wire PIN_23_out_en;
+wire PIN_23_out_data;
+assign PIN_23 = PIN_23_out_en ? PIN_23_out_data : 1'bz;
+
+// GPIO1_2, GPIO1_2
+assign PIN_24_in = PIN_24;
+wire PIN_24_out_en;
+wire PIN_24_out_data;
+assign PIN_24 = PIN_24_out_en ? PIN_24_out_data : 1'bz;
+
+// UART2_UARTTXD, GPIO8_2
+wire PIN_25_out_en;
+wire PIN_25_out_data;
+assign PIN_25 = PIN_25_out_en ? PIN_25_out_data : 1'bz;
+
+// UART2_UARTRXD, GPIO6_5
+assign PIN_26_in = PIN_26;
+
+// GPIO1_0, GPIO1_0
+assign PIN_3_in = PIN_3;
+wire PIN_3_out_en;
+wire PIN_3_out_data;
+assign PIN_3 = PIN_3_out_en ? PIN_3_out_data : 1'bz;
+
+// GPIO1_3, GPIO1_3
+assign PIN_4_in = PIN_4;
+wire PIN_4_out_en;
+wire PIN_4_out_data;
+assign PIN_4 = PIN_4_out_en ? PIN_4_out_data : 1'bz;
+
+// UART0_UARTTXD, GPIO7_6
+wire PIN_68_out_en;
+wire PIN_68_out_data;
+assign PIN_68 = PIN_68_out_en ? PIN_68_out_data : 1'bz;
+
+// UART0_UARTRXD, GPIO6_1
+assign PIN_69_in = PIN_69;
+
+// GPIO5_3, GPIO5_3
+assign PIN_7_in = PIN_7;
+wire PIN_7_out_en;
+wire PIN_7_out_data;
+assign PIN_7 = PIN_7_out_en ? PIN_7_out_data : 1'bz;
+
+// UART1_UARTTXD, GPIO8_0
+wire PIN_80_out_en;
+wire PIN_80_out_data;
+assign PIN_80 = PIN_80_out_en ? PIN_80_out_data : 1'bz;
+
+// UART1_UARTRXD, GPIO6_3
+assign PIN_83_in = PIN_83;
+
+// GPIO1_6, GPIO1_6
+assign PIN_88_in = PIN_88;
+wire PIN_88_out_en;
+wire PIN_88_out_data;
+assign PIN_88 = PIN_88_out_en ? PIN_88_out_data : 1'bz;
+
+// GPIO1_5, GPIO1_5
+assign PIN_91_in = PIN_91;
+wire PIN_91_out_en;
+wire PIN_91_out_data;
+assign PIN_91 = PIN_91_out_en ? PIN_91_out_data : 1'bz;
+
+// GPIO1_4, GPIO1_4
+assign PIN_92_in = PIN_92;
+wire PIN_92_out_en;
+wire PIN_92_out_data;
+assign PIN_92 = PIN_92_out_en ? PIN_92_out_data : 1'bz;
+
+// GPIO5_1, GPIO5_1
+assign PIN_93_in = PIN_93;
+wire PIN_93_out_en;
+wire PIN_93_out_data;
+assign PIN_93 = PIN_93_out_en ? PIN_93_out_data : 1'bz;
+
+// GPIO2_1, GPIO2_1
+assign PIN_95_in = PIN_95;
+wire PIN_95_out_en;
+wire PIN_95_out_data;
+assign PIN_95 = PIN_95_out_en ? PIN_95_out_data : 1'bz;
+
+// GPIO2_2, GPIO2_2
+assign PIN_96_in = PIN_96;
+wire PIN_96_out_en;
+wire PIN_96_out_data;
+assign PIN_96 = PIN_96_out_en ? PIN_96_out_data : 1'bz;
+
+// GPIO2_0, GPIO2_0
+assign PIN_97_in = PIN_97;
+wire PIN_97_out_en;
+wire PIN_97_out_data;
+assign PIN_97 = PIN_97_out_en ? PIN_97_out_data : 1'bz;
+
+// GPIO5_2, GPIO5_2
+assign PIN_98_in = PIN_98;
+wire PIN_98_out_en;
+wire PIN_98_out_data;
+assign PIN_98 = PIN_98_out_en ? PIN_98_out_data : 1'bz;
+
+// HSE clock
+assign PIN_HSE_in = PIN_HSE;
+
+// HSI clock
+assign PIN_HSI_in = PIN_HSI;
+
+// OSC clock
+assign PIN_OSC_in = PIN_OSC;
+
+wire [4:0] PLL_CLKOUT;
+(* keep = 1 *) wire       sys_resetn;
+(* keep = 1 *) wire       sys_ctrl_stop;
+(* keep = 1 *) wire [1:0] sys_ctrl_clkSource;
+(* keep = 1 *) wire       PLL_ENABLE;
+(* keep = 1 *) wire       PLL_LOCK;
+
+altpll pll_inst (
+  .areset(!PLL_ENABLE),
+  .inclk (PIN_HSE_in),
+  .clk   (PLL_CLKOUT),
+  .locked(PLL_LOCK));
+defparam pll_inst.bandwidth_type          = "AUTO";
+defparam pll_inst.clk0_divide_by          = 6;
+defparam pll_inst.clk0_multiply_by        = 90;
+defparam pll_inst.clk0_phase_shift        = "0";
+defparam pll_inst.clk1_divide_by          = 6;
+defparam pll_inst.clk1_multiply_by        = 90;
+defparam pll_inst.clk1_phase_shift        = "0";
+defparam pll_inst.clk2_divide_by          = 6;
+defparam pll_inst.clk2_multiply_by        = 90;
+defparam pll_inst.clk2_phase_shift        = "0";
+defparam pll_inst.clk3_divide_by          = 6;
+defparam pll_inst.clk3_multiply_by        = 90;
+defparam pll_inst.clk3_phase_shift        = "0";
+defparam pll_inst.clk4_divide_by          = 6;
+defparam pll_inst.clk4_multiply_by        = 90;
+defparam pll_inst.clk4_phase_shift        = "0";
+defparam pll_inst.compensate_clock        = "CLK0";
+defparam pll_inst.inclk0_input_frequency  = 125000;
+defparam pll_inst.lpm_type                = "altpll";
+defparam pll_inst.operation_mode          = "NORMAL";
+defparam pll_inst.pll_type                = "AUTO";
+defparam pll_inst.port_areset             = "PORT_USED";
+defparam pll_inst.port_inclk0             = "PORT_USED";
+defparam pll_inst.port_locked             = "PORT_USED";
+defparam pll_inst.port_clk0               = "PORT_USED";
+defparam pll_inst.port_clk1               = "PORT_UNUSED";
+defparam pll_inst.port_clk2               = "PORT_UNUSED";
+defparam pll_inst.port_clk3               = "PORT_UNUSED";
+defparam pll_inst.port_clk4               = "PORT_UNUSED";
+defparam pll_inst.width_clock             = 5;
+
+wire sys_gck;
+assign bus_clk = sys_gck;
+
+// Location: BBOX_X22_Y4_N0 FIXED_COORD
+alta_gclksw gclksw_inst (
+    .resetn(sys_resetn),
+    .ena   (1'b1),
+    .clkin0(PIN_HSI_in),
+    .clkin1(PIN_HSE_in),
+    .clkin2(PLL_CLKOUT[0]),
+    .clkin3(),
+    .select(sys_ctrl_clkSource),
+    .clkout(sys_clk));
+assign sys_gck = sys_clk;
+
+(* keep = 1 *) wire [1:0]  mem_ahb_htrans;
+(* keep = 1 *) wire        mem_ahb_hready;
+(* keep = 1 *) wire        mem_ahb_hwrite;
+(* keep = 1 *) wire [31:0] mem_ahb_haddr;
+(* keep = 1 *) wire [2:0]  mem_ahb_hsize;
+(* keep = 1 *) wire [2:0]  mem_ahb_hburst;
+(* keep = 1 *) wire [31:0] mem_ahb_hwdata;
+(* keep = 1 *) wire        mem_ahb_hreadyout;
+(* keep = 1 *) wire        mem_ahb_hresp;
+(* keep = 1 *) wire [31:0] mem_ahb_hrdata;
+
+(* keep = 1 *) wire        slave_ahb_hsel;
+(* keep = 1 *) wire        slave_ahb_hready;
+(* keep = 1 *) wire        slave_ahb_hreadyout;
+(* keep = 1 *) wire [1:0]  slave_ahb_htrans;
+(* keep = 1 *) wire [2:0]  slave_ahb_hsize;
+(* keep = 1 *) wire [2:0]  slave_ahb_hburst;
+(* keep = 1 *) wire        slave_ahb_hwrite;
+(* keep = 1 *) wire [31:0] slave_ahb_haddr;
+(* keep = 1 *) wire [31:0] slave_ahb_hwdata;
+(* keep = 1 *) wire        slave_ahb_hresp;
+(* keep = 1 *) wire [31:0] slave_ahb_hrdata;
+
+(* keep = 1 *) wire [3:0]  ext_dma_DMACBREQ;
+(* keep = 1 *) wire [3:0]  ext_dma_DMACLBREQ;
+(* keep = 1 *) wire [3:0]  ext_dma_DMACSREQ;
+(* keep = 1 *) wire [3:0]  ext_dma_DMACLSREQ;
+(* keep = 1 *) wire [3:0]  ext_dma_DMACCLR;
+(* keep = 1 *) wire [3:0]  ext_dma_DMACTC;
+(* keep = 1 *) wire [3:0]  local_int;
+
+PT_0104_fpga macro_inst(
+  .sys_clock          (sys_gck            ),
+  .bus_clock          (bus_clk            ),
+  .resetn             (sys_resetn         ),
+  .stop               (sys_ctrl_stop      ),
+  .mem_ahb_htrans     (mem_ahb_htrans     ),
+  .mem_ahb_hready     (mem_ahb_hready     ),
+  .mem_ahb_hwrite     (mem_ahb_hwrite     ),
+  .mem_ahb_haddr      (mem_ahb_haddr      ),
+  .mem_ahb_hsize      (mem_ahb_hsize      ),
+  .mem_ahb_hburst     (mem_ahb_hburst     ),
+  .mem_ahb_hwdata     (mem_ahb_hwdata     ),
+  .mem_ahb_hreadyout  (mem_ahb_hreadyout  ),
+  .mem_ahb_hresp      (mem_ahb_hresp      ),
+  .mem_ahb_hrdata     (mem_ahb_hrdata     ),
+  .slave_ahb_hsel     (slave_ahb_hsel     ),
+  .slave_ahb_hready   (slave_ahb_hready   ),
+  .slave_ahb_hreadyout(slave_ahb_hreadyout),
+  .slave_ahb_htrans   (slave_ahb_htrans   ),
+  .slave_ahb_hsize    (slave_ahb_hsize    ),
+  .slave_ahb_hburst   (slave_ahb_hburst   ),
+  .slave_ahb_hwrite   (slave_ahb_hwrite   ),
+  .slave_ahb_haddr    (slave_ahb_haddr    ),
+  .slave_ahb_hwdata   (slave_ahb_hwdata   ),
+  .slave_ahb_hresp    (slave_ahb_hresp    ),
+  .slave_ahb_hrdata   (slave_ahb_hrdata   ),
+  .ext_dma_DMACBREQ   (ext_dma_DMACBREQ   ),
+  .ext_dma_DMACLBREQ  (ext_dma_DMACLBREQ  ),
+  .ext_dma_DMACSREQ   (ext_dma_DMACSREQ   ),
+  .ext_dma_DMACLSREQ  (ext_dma_DMACLSREQ  ),
+  .ext_dma_DMACCLR    (ext_dma_DMACCLR    ),
+  .ext_dma_DMACTC     (ext_dma_DMACTC     ),
+  .local_int          (local_int          )
+);
+
+(* keep = 1 *) wire [7:0] gpio0_io_out_data;
+(* keep = 1 *) wire [7:0] gpio0_io_out_en;
+assign PIN_15_out_data = gpio0_io_out_data[4];
+assign PIN_15_out_en = gpio0_io_out_en[4];
+assign PIN_16_out_data = gpio0_io_out_data[5];
+assign PIN_16_out_en = gpio0_io_out_en[5];
+assign PIN_17_out_data = gpio0_io_out_data[6];
+assign PIN_17_out_en = gpio0_io_out_en[6];
+assign PIN_18_out_data = gpio0_io_out_data[7];
+assign PIN_18_out_en = gpio0_io_out_en[7];
+(* keep = 1 *) wire [7:0] gpio0_io_in = {PIN_18_in, PIN_17_in, PIN_16_in, PIN_15_in, 1'b0, 1'b0, 1'b0, 1'b0};
+
+(* keep = 1 *) wire [7:0] gpio1_io_out_data;
+(* keep = 1 *) wire [7:0] gpio1_io_out_en;
+assign PIN_3_out_data = gpio1_io_out_data[0];
+assign PIN_3_out_en = gpio1_io_out_en[0];
+assign PIN_2_out_data = gpio1_io_out_data[1];
+assign PIN_2_out_en = gpio1_io_out_en[1];
+assign PIN_24_out_data = gpio1_io_out_data[2];
+assign PIN_24_out_en = gpio1_io_out_en[2];
+assign PIN_4_out_data = gpio1_io_out_data[3];
+assign PIN_4_out_en = gpio1_io_out_en[3];
+assign PIN_92_out_data = gpio1_io_out_data[4];
+assign PIN_92_out_en = gpio1_io_out_en[4];
+assign PIN_91_out_data = gpio1_io_out_data[5];
+assign PIN_91_out_en = gpio1_io_out_en[5];
+assign PIN_88_out_data = gpio1_io_out_data[6];
+assign PIN_88_out_en = gpio1_io_out_en[6];
+(* keep = 1 *) wire [7:0] gpio1_io_in = {1'b0, PIN_88_in, PIN_91_in, PIN_92_in, PIN_4_in, PIN_24_in, PIN_2_in, PIN_3_in};
+
+(* keep = 1 *) wire [7:0] gpio2_io_out_data;
+(* keep = 1 *) wire [7:0] gpio2_io_out_en;
+assign PIN_97_out_data = gpio2_io_out_data[0];
+assign PIN_97_out_en = gpio2_io_out_en[0];
+assign PIN_95_out_data = gpio2_io_out_data[1];
+assign PIN_95_out_en = gpio2_io_out_en[1];
+assign PIN_96_out_data = gpio2_io_out_data[2];
+assign PIN_96_out_en = gpio2_io_out_en[2];
+(* keep = 1 *) wire [7:0] gpio2_io_in = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, PIN_96_in, PIN_95_in, PIN_97_in};
+
+(* keep = 1 *) wire [7:0] gpio3_io_out_data;
+(* keep = 1 *) wire [7:0] gpio3_io_out_en;
+(* keep = 1 *) wire [7:0] gpio3_io_in = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
+
+(* keep = 1 *) wire [7:0] gpio4_io_out_data;
+(* keep = 1 *) wire [7:0] gpio4_io_out_en;
+(* keep = 1 *) wire [7:0] gpio4_io_in = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
+
+(* keep = 1 *) wire [7:0] gpio5_io_out_data;
+(* keep = 1 *) wire [7:0] gpio5_io_out_en;
+assign PIN_23_out_data = gpio5_io_out_data[0];
+assign PIN_23_out_en = gpio5_io_out_en[0];
+assign PIN_93_out_data = gpio5_io_out_data[1];
+assign PIN_93_out_en = gpio5_io_out_en[1];
+assign PIN_98_out_data = gpio5_io_out_data[2];
+assign PIN_98_out_en = gpio5_io_out_en[2];
+assign PIN_7_out_data = gpio5_io_out_data[3];
+assign PIN_7_out_en = gpio5_io_out_en[3];
+(* keep = 1 *) wire [7:0] gpio5_io_in = {1'b0, 1'b0, 1'b0, 1'b0, PIN_7_in, PIN_98_in, PIN_93_in, PIN_23_in};
+
+(* keep = 1 *) wire [7:0] gpio6_io_out_data;
+(* keep = 1 *) wire [7:0] gpio6_io_out_en;
+(* keep = 1 *) wire [7:0] gpio6_io_in = {1'b0, 1'b0, PIN_26_in, 1'b0, PIN_83_in, 1'b0, PIN_69_in, 1'b0};
+
+(* keep = 1 *) wire [7:0] gpio7_io_out_data;
+(* keep = 1 *) wire [7:0] gpio7_io_out_en;
+assign PIN_68_out_data = gpio7_io_out_data[6];
+assign PIN_68_out_en = gpio7_io_out_en[6];
+(* keep = 1 *) wire [7:0] gpio7_io_in = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
+
+(* keep = 1 *) wire [7:0] gpio8_io_out_data;
+(* keep = 1 *) wire [7:0] gpio8_io_out_en;
+assign PIN_80_out_data = gpio8_io_out_data[0];
+assign PIN_80_out_en = gpio8_io_out_en[0];
+assign PIN_25_out_data = gpio8_io_out_data[2];
+assign PIN_25_out_en = gpio8_io_out_en[2];
+(* keep = 1 *) wire [7:0] gpio8_io_in = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
+
+(* keep = 1 *) wire [7:0] gpio9_io_out_data;
+(* keep = 1 *) wire [7:0] gpio9_io_out_en;
+(* keep = 1 *) wire [7:0] gpio9_io_in = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0};
+
+alta_rv32 rv32(
+  .sys_clk            (sys_clk                                         ),
+  .sys_ctrl_stop      (sys_ctrl_stop                                   ),
+  .sys_ctrl_clkSource (sys_ctrl_clkSource                              ),
+  .resetn_out         (sys_resetn                                      ),
+  .sys_ctrl_pllEnable (PLL_ENABLE                                      ),
+  .sys_ctrl_pllReady  (PLL_LOCK                                        ),
+  .ext_resetn         (1'b1                                            ),
+  .test_mode          (2'b0                                            ),
+  .usb0_xcvr_clk      (usb0_xcvr_clk                                   ),
+  .usb0_id            (1'b1                                            ),
+  .ext_int            ({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0}),
+  .mem_ahb_htrans     (mem_ahb_htrans                                  ),
+  .mem_ahb_hready     (mem_ahb_hready                                  ),
+  .mem_ahb_hwrite     (mem_ahb_hwrite                                  ),
+  .mem_ahb_haddr      (mem_ahb_haddr                                   ),
+  .mem_ahb_hsize      (mem_ahb_hsize                                   ),
+  .mem_ahb_hburst     (mem_ahb_hburst                                  ),
+  .mem_ahb_hwdata     (mem_ahb_hwdata                                  ),
+  .mem_ahb_hreadyout  (mem_ahb_hreadyout                               ),
+  .mem_ahb_hresp      (mem_ahb_hresp                                   ),
+  .mem_ahb_hrdata     (mem_ahb_hrdata                                  ),
+  .slave_ahb_hsel     (slave_ahb_hsel                                  ),
+  .slave_ahb_hready   (slave_ahb_hready                                ),
+  .slave_ahb_hreadyout(slave_ahb_hreadyout                             ),
+  .slave_ahb_htrans   (slave_ahb_htrans                                ),
+  .slave_ahb_hsize    (slave_ahb_hsize                                 ),
+  .slave_ahb_hburst   (slave_ahb_hburst                                ),
+  .slave_ahb_hwrite   (slave_ahb_hwrite                                ),
+  .slave_ahb_haddr    (slave_ahb_haddr                                 ),
+  .slave_ahb_hwdata   (slave_ahb_hwdata                                ),
+  .slave_ahb_hresp    (slave_ahb_hresp                                 ),
+  .slave_ahb_hrdata   (slave_ahb_hrdata                                ),
+  .ext_dma_DMACBREQ   (ext_dma_DMACBREQ                                ),
+  .ext_dma_DMACLBREQ  (ext_dma_DMACLBREQ                               ),
+  .ext_dma_DMACSREQ   (ext_dma_DMACSREQ                                ),
+  .ext_dma_DMACLSREQ  (ext_dma_DMACLSREQ                               ),
+  .ext_dma_DMACCLR    (ext_dma_DMACCLR                                 ),
+  .ext_dma_DMACTC     (ext_dma_DMACTC                                  ),
+  .local_int          (local_int                                       ),
+  .gpio0_io_in        (gpio0_io_in                                     ),
+  .gpio0_io_out_data  (gpio0_io_out_data                               ),
+  .gpio0_io_out_en    (gpio0_io_out_en                                 ),
+  .gpio1_io_in        (gpio1_io_in                                     ),
+  .gpio1_io_out_data  (gpio1_io_out_data                               ),
+  .gpio1_io_out_en    (gpio1_io_out_en                                 ),
+  .gpio2_io_in        (gpio2_io_in                                     ),
+  .gpio2_io_out_data  (gpio2_io_out_data                               ),
+  .gpio2_io_out_en    (gpio2_io_out_en                                 ),
+  .gpio3_io_in        (gpio3_io_in                                     ),
+  .gpio3_io_out_data  (gpio3_io_out_data                               ),
+  .gpio3_io_out_en    (gpio3_io_out_en                                 ),
+  .gpio4_io_in        (gpio4_io_in                                     ),
+  .gpio4_io_out_data  (gpio4_io_out_data                               ),
+  .gpio4_io_out_en    (gpio4_io_out_en                                 ),
+  .gpio5_io_in        (gpio5_io_in                                     ),
+  .gpio5_io_out_data  (gpio5_io_out_data                               ),
+  .gpio5_io_out_en    (gpio5_io_out_en                                 ),
+  .gpio6_io_in        (gpio6_io_in                                     ),
+  .gpio6_io_out_data  (gpio6_io_out_data                               ),
+  .gpio6_io_out_en    (gpio6_io_out_en                                 ),
+  .gpio7_io_in        (gpio7_io_in                                     ),
+  .gpio7_io_out_data  (gpio7_io_out_data                               ),
+  .gpio7_io_out_en    (gpio7_io_out_en                                 ),
+  .gpio8_io_in        (gpio8_io_in                                     ),
+  .gpio8_io_out_data  (gpio8_io_out_data                               ),
+  .gpio8_io_out_en    (gpio8_io_out_en                                 ),
+  .gpio9_io_in        (gpio9_io_in                                     ),
+  .gpio9_io_out_data  (gpio9_io_out_data                               ),
+  .gpio9_io_out_en    (gpio9_io_out_en                                 )
+);
+
+endmodule
+

logic/PT_0104_assignment_defaults.qdf

@@ -0,0 +1,728 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, the Altera Quartus II License Agreement,
+# the Altera MegaCore Function License Agreement, or other 
+# applicable license agreement, including, without limitation, 
+# that your use is for the sole purpose of programming logic 
+# devices manufactured by Altera and sold by Altera or its 
+# authorized distributors.  Please refer to the applicable 
+# agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 15.0.0 Build 145 04/22/2015 SJ Full Version
+# Date created = 11:01:06  November 14, 2023
+#
+# -------------------------------------------------------------------------- #
+#
+# Note:
+#
+# 1) Do not modify this file. This file was generated
+#    automatically by the Quartus II software and is used
+#    to preserve global assignments across Quartus II versions.
+#
+# -------------------------------------------------------------------------- #
+
+set_global_assignment -name IP_COMPONENT_REPORT_HIERARCHY Off
+set_global_assignment -name IP_COMPONENT_INTERNAL Off
+set_global_assignment -name PROJECT_SHOW_ENTITY_NAME On
+set_global_assignment -name PROJECT_USE_SIMPLIFIED_NAMES Off
+set_global_assignment -name ENABLE_REDUCED_MEMORY_MODE Off
+set_global_assignment -name VER_COMPATIBLE_DB_DIR export_db
+set_global_assignment -name AUTO_EXPORT_VER_COMPATIBLE_DB Off
+set_global_assignment -name FLOW_DISABLE_ASSEMBLER Off
+set_global_assignment -name FLOW_ENABLE_POWER_ANALYZER Off
+set_global_assignment -name FLOW_ENABLE_HC_COMPARE Off
+set_global_assignment -name HC_OUTPUT_DIR hc_output
+set_global_assignment -name SAVE_MIGRATION_INFO_DURING_COMPILATION Off
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS Off
+set_global_assignment -name RUN_FULL_COMPILE_ON_DEVICE_CHANGE On
+set_global_assignment -name FLOW_ENABLE_RTL_VIEWER Off
+set_global_assignment -name READ_OR_WRITE_IN_BYTE_ADDRESS "Use global settings"
+set_global_assignment -name FLOW_HARDCOPY_DESIGN_READINESS_CHECK On
+set_global_assignment -name FLOW_ENABLE_PARALLEL_MODULES On
+set_global_assignment -name ENABLE_COMPACT_REPORT_TABLE Off
+set_global_assignment -name REVISION_TYPE Base
+set_global_assignment -name DEFAULT_HOLD_MULTICYCLE "Same as Multicycle"
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS On
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS On
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK On
+set_global_assignment -name DO_COMBINED_ANALYSIS Off
+set_global_assignment -name TDC_AGGRESSIVE_HOLD_CLOSURE_EFFORT Off
+set_global_assignment -name EMIF_SOC_PHYCLK_ADVANCE_MODELING Off
+set_global_assignment -name USE_DLL_FREQUENCY_FOR_DQS_DELAY_CHAIN Off
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS On
+set_global_assignment -name TIMEQUEST_REPORT_SCRIPT_INCLUDE_DEFAULT_ANALYSIS On
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS On -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING Off
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "MAX 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria 10"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Stratix V"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "MAX II"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_REPORT_WORST_CASE_TIMING_PATHS Off -family "Cyclone V"
+set_global_assignment -name TIMEQUEST_REPORT_NUM_WORST_CASE_TIMING_PATHS 100
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "MAX 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV E"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix IV"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria 10"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Stratix V"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria V GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL Off -family "MAX II"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Arria II GZ"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone IV GX"
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL On -family "Cyclone V"
+set_global_assignment -name OPTIMIZATION_MODE Balanced
+set_global_assignment -name ALLOW_REGISTER_MERGING On
+set_global_assignment -name ALLOW_REGISTER_DUPLICATION On
+set_global_assignment -name TIMEQUEST2 on -family "Arria 10"
+set_global_assignment -name TIMEQUEST2 OFF -family "Stratix V"
+set_global_assignment -name MUX_RESTRUCTURE Auto
+set_global_assignment -name MLAB_ADD_TIMING_CONSTRAINTS_FOR_MIXED_PORT_FEED_THROUGH_MODE_SETTING_DONT_CARE Off
+set_global_assignment -name ENABLE_IP_DEBUG Off
+set_global_assignment -name SAVE_DISK_SPACE On
+set_global_assignment -name DISABLE_OCP_HW_EVAL Off
+set_global_assignment -name DEVICE_FILTER_PACKAGE Any
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT Any
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE Any
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "<None>"
+set_global_assignment -name VERILOG_INPUT_VERSION Verilog_2001
+set_global_assignment -name VHDL_INPUT_VERSION VHDL_1993
+set_global_assignment -name FAMILY -value "Cyclone V"
+set_global_assignment -name TRUE_WYSIWYG_FLOW Off
+set_global_assignment -name SMART_COMPILE_IGNORES_TDC_FOR_STRATIX_PLL_CHANGES Off
+set_global_assignment -name STATE_MACHINE_PROCESSING Auto
+set_global_assignment -name SAFE_STATE_MACHINE Off
+set_global_assignment -name EXTRACT_VERILOG_STATE_MACHINES On
+set_global_assignment -name EXTRACT_VHDL_STATE_MACHINES On
+set_global_assignment -name IGNORE_VERILOG_INITIAL_CONSTRUCTS Off
+set_global_assignment -name VERILOG_CONSTANT_LOOP_LIMIT 5000
+set_global_assignment -name VERILOG_NON_CONSTANT_LOOP_LIMIT 250
+set_global_assignment -name INFER_RAMS_FROM_RAW_LOGIC On
+set_global_assignment -name PARALLEL_SYNTHESIS On
+set_global_assignment -name DSP_BLOCK_BALANCING Auto
+set_global_assignment -name MAX_BALANCING_DSP_BLOCKS "-1 (Unlimited)"
+set_global_assignment -name NOT_GATE_PUSH_BACK On
+set_global_assignment -name ALLOW_POWER_UP_DONT_CARE On
+set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS Off
+set_global_assignment -name REMOVE_DUPLICATE_REGISTERS On
+set_global_assignment -name IGNORE_CARRY_BUFFERS Off
+set_global_assignment -name IGNORE_CASCADE_BUFFERS Off
+set_global_assignment -name IGNORE_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_ROW_GLOBAL_BUFFERS Off
+set_global_assignment -name IGNORE_LCELL_BUFFERS Off
+set_global_assignment -name MAX7000_IGNORE_LCELL_BUFFERS AUTO
+set_global_assignment -name IGNORE_SOFT_BUFFERS On
+set_global_assignment -name MAX7000_IGNORE_SOFT_BUFFERS Off
+set_global_assignment -name LIMIT_AHDL_INTEGERS_TO_32_BITS Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK_MAX On
+set_global_assignment -name AUTO_GLOBAL_OE_MAX On
+set_global_assignment -name MAX_AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name AUTO_IMPLEMENT_IN_ROM Off
+set_global_assignment -name APEX20K_TECHNOLOGY_MAPPER Lut
+set_global_assignment -name OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONE_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name STRATIX_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAXII_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MAX7000_OPTIMIZATION_TECHNIQUE Speed
+set_global_assignment -name APEX20K_OPTIMIZATION_TECHNIQUE Balanced
+set_global_assignment -name MERCURY_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX6K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name FLEX10K_OPTIMIZATION_TECHNIQUE Area
+set_global_assignment -name ALLOW_XOR_GATE_USAGE On
+set_global_assignment -name AUTO_LCELL_INSERTION On
+set_global_assignment -name CARRY_CHAIN_LENGTH 48
+set_global_assignment -name FLEX6K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name FLEX10K_CARRY_CHAIN_LENGTH 32
+set_global_assignment -name MERCURY_CARRY_CHAIN_LENGTH 48
+set_global_assignment -name STRATIX_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name STRATIXII_CARRY_CHAIN_LENGTH 70
+set_global_assignment -name CASCADE_CHAIN_LENGTH 2
+set_global_assignment -name PARALLEL_EXPANDER_CHAIN_LENGTH 16
+set_global_assignment -name MAX7000_PARALLEL_EXPANDER_CHAIN_LENGTH 4
+set_global_assignment -name AUTO_CARRY_CHAINS On
+set_global_assignment -name AUTO_CASCADE_CHAINS On
+set_global_assignment -name AUTO_PARALLEL_EXPANDERS On
+set_global_assignment -name AUTO_OPEN_DRAIN_PINS On
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP Off
+set_global_assignment -name AUTO_ROM_RECOGNITION On
+set_global_assignment -name AUTO_RAM_RECOGNITION On
+set_global_assignment -name AUTO_DSP_RECOGNITION On
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION Auto
+set_global_assignment -name ALLOW_SHIFT_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name AUTO_CLOCK_ENABLE_RECOGNITION On
+set_global_assignment -name STRICT_RAM_RECOGNITION Off
+set_global_assignment -name ALLOW_SYNCH_CTRL_USAGE On
+set_global_assignment -name FORCE_SYNCH_CLEAR Off
+set_global_assignment -name AUTO_RAM_BLOCK_BALANCING On
+set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION Off
+set_global_assignment -name AUTO_RESOURCE_SHARING Off
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name ALLOW_ANY_SHIFT_REGISTER_SIZE_FOR_RECOGNITION Off
+set_global_assignment -name MAX7000_FANIN_PER_CELL 100
+set_global_assignment -name USE_LOGICLOCK_CONSTRAINTS_IN_BALANCING On
+set_global_assignment -name MAX_RAM_BLOCKS_M512 "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_M4K "-1 (Unlimited)"
+set_global_assignment -name MAX_RAM_BLOCKS_MRAM "-1 (Unlimited)"
+set_global_assignment -name IGNORE_TRANSLATE_OFF_AND_SYNTHESIS_OFF Off
+set_global_assignment -name STRATIXGX_BYPASS_REMAPPING_OF_FORCE_SIGNAL_DETECT_SIGNAL_THRESHOLD_SELECT Off
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "MAX 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix IV"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria 10"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Stratix V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria V GZ"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Cyclone V"
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS On -family "Arria II GX"
+set_global_assignment -name REPORT_PARAMETER_SETTINGS On
+set_global_assignment -name REPORT_SOURCE_ASSIGNMENTS On
+set_global_assignment -name REPORT_CONNECTIVITY_CHECKS On
+set_global_assignment -name IGNORE_MAX_FANOUT_ASSIGNMENTS Off
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV E"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix IV"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria 10"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Stratix V"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "MAX II"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria V GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Arria II GZ"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2 -family "Cyclone IV GX"
+set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 3 -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_POWER_DURING_SYNTHESIS "Normal compilation"
+set_global_assignment -name HDL_MESSAGE_LEVEL Level2
+set_global_assignment -name USE_HIGH_SPEED_ADDER Auto
+set_global_assignment -name NUMBER_OF_REMOVED_REGISTERS_REPORTED 5000
+set_global_assignment -name NUMBER_OF_SYNTHESIS_MIGRATION_ROWS 5000
+set_global_assignment -name SYNTHESIS_S10_MIGRATION_CHECKS Off
+set_global_assignment -name NUMBER_OF_SWEPT_NODES_REPORTED 5000
+set_global_assignment -name NUMBER_OF_INVERTED_REGISTERS_REPORTED 100
+set_global_assignment -name SYNTH_CLOCK_MUX_PROTECTION On
+set_global_assignment -name SYNTH_GATED_CLOCK_CONVERSION Off
+set_global_assignment -name BLOCK_DESIGN_NAMING Auto
+set_global_assignment -name SYNTH_PROTECT_SDC_CONSTRAINT Off
+set_global_assignment -name SYNTHESIS_EFFORT Auto
+set_global_assignment -name SHIFT_REGISTER_RECOGNITION_ACLR_SIGNAL On
+set_global_assignment -name PRE_MAPPING_RESYNTHESIS Off
+set_global_assignment -name SYNTH_MESSAGE_LEVEL Medium
+set_global_assignment -name DISABLE_REGISTER_MERGING_ACROSS_HIERARCHIES Auto
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "MAX 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV GX"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix IV"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone IV E"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria 10"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Stratix V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria V GZ"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Cyclone V"
+set_global_assignment -name SYNTH_RESOURCE_AWARE_INFERENCE_FOR_BLOCK_RAM On -family "Arria II GX"
+set_global_assignment -name MAX_LABS "-1 (Unlimited)"
+set_global_assignment -name RBCGEN_CRITICAL_WARNING_TO_ERROR On
+set_global_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS "-1 (Unlimited)"
+set_global_assignment -name AUTO_PARALLEL_SYNTHESIS On
+set_global_assignment -name PRPOF_ID Off
+set_global_assignment -name DISABLE_DSP_NEGATE_INFERENCING Off
+set_global_assignment -name FLEX10K_ENABLE_LOCK_OUTPUT Off
+set_global_assignment -name AUTO_MERGE_PLLS On
+set_global_assignment -name IGNORE_MODE_FOR_MERGE Off
+set_global_assignment -name TXPMA_SLEW_RATE Low
+set_global_assignment -name ADCE_ENABLED Auto
+set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL Normal
+set_global_assignment -name ROUTER_CLOCKING_TOPOLOGY_ANALYSIS Off
+set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 1.0
+set_global_assignment -name FIT_ATTEMPTS_TO_SKIP 0.0
+set_global_assignment -name ECO_ALLOW_ROUTING_CHANGES Off
+set_global_assignment -name DEVICE AUTO
+set_global_assignment -name BASE_PIN_OUT_FILE_ON_SAMEFRAME_DEVICE Off
+set_global_assignment -name ENABLE_JTAG_BST_SUPPORT Off
+set_global_assignment -name MAX7000_ENABLE_JTAG_BST_SUPPORT On
+set_global_assignment -name ENABLE_NCEO_OUTPUT Off
+set_global_assignment -name RESERVE_NCEO_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name STRATIXIII_UPDATE_MODE Standard
+set_global_assignment -name STRATIX_UPDATE_MODE Standard
+set_global_assignment -name INTERNAL_FLASH_UPDATE_MODE "Single Image"
+set_global_assignment -name CVP_MODE Off
+set_global_assignment -name STRATIXV_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIXIII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name MAX10FPGA_CONFIGURATION_SCHEME "Internal Configuration"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name STRATIXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONEII_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name APEX20K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name STRATIX_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name CYCLONE_CONFIGURATION_SCHEME "Active Serial"
+set_global_assignment -name MERCURY_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX6K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name FLEX10K_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name APEXII_CONFIGURATION_SCHEME "Passive Serial"
+set_global_assignment -name USER_START_UP_CLOCK Off
+set_global_assignment -name DEVICE_INITIALIZATION_CLOCK INIT_INTOSC
+set_global_assignment -name ENABLE_VREFA_PIN Off
+set_global_assignment -name ENABLE_VREFB_PIN Off
+set_global_assignment -name ALWAYS_ENABLE_INPUT_BUFFERS Off
+set_global_assignment -name ENABLE_ASMI_FOR_FLASH_LOADER Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_RESET Off
+set_global_assignment -name ENABLE_DEVICE_WIDE_OE Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS "As output driving ground"
+set_global_assignment -name ENABLE_INIT_DONE_OUTPUT Off
+set_global_assignment -name INIT_DONE_OPEN_DRAIN On
+set_global_assignment -name RESERVE_NWS_NRS_NCS_CS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_RDYNBUSY_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA31_THROUGH_DATA16_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA15_THROUGH_DATA8_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA1_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA2_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DATA7_THROUGH_DATA5_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "As input tri-stated"
+set_global_assignment -name RESERVE_OTHER_AP_PINS_AFTER_CONFIGURATION "Use as regular IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "Use as programming pin"
+set_global_assignment -name ENABLE_CONFIGURATION_PINS On
+set_global_assignment -name ENABLE_JTAG_PIN_SHARING Off
+set_global_assignment -name ENABLE_NCE_PIN Off
+set_global_assignment -name ENABLE_BOOT_SEL_PIN On
+set_global_assignment -name CRC_ERROR_CHECKING Off
+set_global_assignment -name INTERNAL_SCRUBBING Off
+set_global_assignment -name PR_ERROR_OPEN_DRAIN On
+set_global_assignment -name PR_READY_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CVP_CONFDONE Off
+set_global_assignment -name CVP_CONFDONE_OPEN_DRAIN On
+set_global_assignment -name ENABLE_NCONFIG_FROM_CORE On
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "MAX 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria 10"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Stratix V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO Paths and Minimum TPD Paths" -family "MAX II"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Cyclone V"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "All Paths" -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "MAX 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV E"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix IV"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria 10"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Stratix V"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria V GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING Off -family "MAX II"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Arria II GZ"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone IV GX"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING On -family "Cyclone V"
+set_global_assignment -name BLOCK_RAM_TO_MLAB_CELL_CONVERSION On
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_POWER_UP_CONDITIONS Auto
+set_global_assignment -name BLOCK_RAM_AND_MLAB_EQUIVALENT_PAUSED_READ_CAPABILITIES Care
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix IV"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria 10"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Stratix V"
+set_global_assignment -name PROGRAMMABLE_POWER_TECHNOLOGY_SETTING Automatic -family "Arria V GZ"
+set_global_assignment -name PROGRAMMABLE_POWER_MAXIMUM_HIGH_SPEED_FRACTION_OF_USED_LAB_TILES 1.0
+set_global_assignment -name GUARANTEE_MIN_DELAY_CORNER_IO_ZERO_HOLD_TIME On
+set_global_assignment -name OPTIMIZE_POWER_DURING_FITTING "Normal compilation"
+set_global_assignment -name OPTIMIZE_SSN Off
+set_global_assignment -name OPTIMIZE_TIMING "Normal compilation"
+set_global_assignment -name ECO_OPTIMIZE_TIMING Off
+set_global_assignment -name ECO_REGENERATE_REPORT Off
+set_global_assignment -name OPTIMIZE_IOC_REGISTER_PLACEMENT_FOR_TIMING Normal
+set_global_assignment -name FIT_ONLY_ONE_ATTEMPT Off
+set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION Automatically
+set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION Automatically
+set_global_assignment -name SEED 1
+set_global_assignment -name SLOW_SLEW_RATE Off
+set_global_assignment -name PCI_IO Off
+set_global_assignment -name TURBO_BIT On
+set_global_assignment -name WEAK_PULL_UP_RESISTOR Off
+set_global_assignment -name ENABLE_BUS_HOLD_CIRCUITRY Off
+set_global_assignment -name AUTO_GLOBAL_MEMORY_CONTROLS Off
+set_global_assignment -name MIGRATION_CONSTRAIN_CORE_RESOURCES On
+set_global_assignment -name QII_AUTO_PACKED_REGISTERS Auto
+set_global_assignment -name AUTO_PACKED_REGISTERS_MAX Auto
+set_global_assignment -name NORMAL_LCELL_INSERT On
+set_global_assignment -name CARRY_OUT_PINS_LCELL_INSERT On
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix IV"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV E"
+set_global_assignment -name AUTO_DELAY_CHAINS Off -family "Arria 10"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Stratix V"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "MAX II"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria V GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Arria II GZ"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone IV GX"
+set_global_assignment -name AUTO_DELAY_CHAINS On -family "Cyclone V"
+set_global_assignment -name AUTO_DELAY_CHAINS_FOR_HIGH_FANOUT_INPUT_PINS OFF
+set_global_assignment -name XSTL_INPUT_ALLOW_SE_BUFFER Off
+set_global_assignment -name TREAT_BIDIR_AS_OUTPUT Off
+set_global_assignment -name AUTO_TURBO_BIT ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_LOG_FILE Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING Off
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING Off
+set_global_assignment -name IO_PLACEMENT_OPTIMIZATION On
+set_global_assignment -name ALLOW_LVTTL_LVCMOS_INPUT_LEVELS_TO_OVERDRIVE_INPUT_BUFFER Off
+set_global_assignment -name OVERRIDE_DEFAULT_ELECTROMIGRATION_PARAMETERS Off
+set_global_assignment -name FITTER_EFFORT "Auto Fit"
+set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN 0ns
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT Normal
+set_global_assignment -name ROUTER_LCELL_INSERTION_AND_LOGIC_DUPLICATION Auto
+set_global_assignment -name ROUTER_REGISTER_DUPLICATION Auto
+set_global_assignment -name STRATIXGX_ALLOW_CLOCK_FANOUT_WITH_ANALOG_RESET Off
+set_global_assignment -name AUTO_GLOBAL_CLOCK On
+set_global_assignment -name AUTO_GLOBAL_OE On
+set_global_assignment -name AUTO_GLOBAL_REGISTER_CONTROLS On
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE Realistic
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_UNDER_FULL_DATARATE_RANGE Off
+set_global_assignment -name STRATIXGX_ALLOW_RX_CORECLK_FROM_NON_RX_CLKOUT_SOURCE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_PARALLEL_LOOPBACK_IN_DOUBLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_IN_SINGLE_DATA_WIDTH_MODE Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_XAUI_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_CORECLK_SELECTED_AT_RATE_MATCHER Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITHOUT_8B10B Off
+set_global_assignment -name STRATIXGX_ALLOW_GIGE_WITH_RX_CORECLK_FROM_NON_TXPLL_SOURCE Off
+set_global_assignment -name STRATIXGX_ALLOW_POST8B10B_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_REVERSE_PARALLEL_LOOPBACK Off
+set_global_assignment -name STRATIXGX_ALLOW_USE_OF_GXB_COUPLED_IOS Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF Off
+set_global_assignment -name GENERATE_GXB_RECONFIG_MIF_WITH_PLL Off
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "As input tri-stated with weak pull-up"
+set_global_assignment -name ENABLE_HOLD_BACK_OFF On
+set_global_assignment -name CONFIGURATION_VCCIO_LEVEL Auto
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO Off
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION Off
+set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION On
+set_global_assignment -name OPTIMIZE_FOR_METASTABILITY On
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "MAX 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN Off -family "Cyclone IV E"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria 10"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Stratix V"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Arria V GZ"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN On -family "Cyclone V"
+set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_REGIONAL_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_PERIPHERY_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name MAX_CLOCKS_ALLOWED "-1 (Unlimited)"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria 10"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Stratix V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Cyclone IV GX"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Arria V GZ"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_100MHz -family "Cyclone V"
+set_global_assignment -name ACTIVE_SERIAL_CLOCK FREQ_40MHz -family "Arria II GX"
+set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY Off
+set_global_assignment -name STRATIXIII_MRAM_COMPATIBILITY On
+set_global_assignment -name FORCE_FITTER_TO_AVOID_PERIPHERY_PLACEMENT_WARNINGS Off
+set_global_assignment -name AUTO_C3_M9K_BIT_SKIP Off
+set_global_assignment -name PR_DONE_OPEN_DRAIN On
+set_global_assignment -name NCEO_OPEN_DRAIN On
+set_global_assignment -name ENABLE_CRC_ERROR_PIN Off
+set_global_assignment -name ENABLE_PR_PINS Off
+set_global_assignment -name PR_PINS_OPEN_DRAIN Off
+set_global_assignment -name CLAMPING_DIODE Off
+set_global_assignment -name TRI_STATE_SPI_PINS Off
+set_global_assignment -name UNUSED_TSD_PINS_GND Off
+set_global_assignment -name IMPLEMENT_MLAB_IN_16_BIT_DEEP_MODE Off
+set_global_assignment -name FORM_DDR_CLUSTERING_CLIQUE Off
+set_global_assignment -name ALM_REGISTER_PACKING_EFFORT Medium
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION Off -family "Stratix IV"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria 10"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Stratix V"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Arria V GZ"
+set_global_assignment -name ADVANCED_PHYSICAL_OPTIMIZATION On -family "Cyclone V"
+set_global_assignment -name EDA_SIMULATION_TOOL "<None>"
+set_global_assignment -name EDA_TIMING_ANALYSIS_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TIMING_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SYMBOL_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_SIGNAL_INTEGRITY_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_BOUNDARY_SCAN_TOOL "<None>"
+set_global_assignment -name EDA_BOARD_DESIGN_TOOL "<None>"
+set_global_assignment -name EDA_FORMAL_VERIFICATION_TOOL "<None>"
+set_global_assignment -name EDA_RESYNTHESIS_TOOL "<None>"
+set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION On
+set_global_assignment -name COMPRESSION_MODE Off
+set_global_assignment -name CLOCK_SOURCE Internal
+set_global_assignment -name CONFIGURATION_CLOCK_FREQUENCY "10 MHz"
+set_global_assignment -name CONFIGURATION_CLOCK_DIVISOR 1
+set_global_assignment -name ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name FLEX6K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE Off
+set_global_assignment -name FLEX10K_ENABLE_LOW_VOLTAGE_MODE_ON_CONFIG_DEVICE On
+set_global_assignment -name MAX7000S_JTAG_USER_CODE FFFF
+set_global_assignment -name STRATIX_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name APEX20K_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_JTAG_USER_CODE 7F
+set_global_assignment -name MAX7000_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MAX7000_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name USE_CHECKSUM_AS_USERCODE On
+set_global_assignment -name SECURITY_BIT Off
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX 10"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV E"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Stratix IV"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX V"
+set_global_assignment -name USE_CONFIGURATION_DEVICE On -family "MAX II"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GX"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Arria II GZ"
+set_global_assignment -name USE_CONFIGURATION_DEVICE Off -family "Cyclone IV GX"
+set_global_assignment -name CYCLONEIII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIXII_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name MERCURY_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX6K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name FLEX10K_CONFIGURATION_DEVICE Auto
+set_global_assignment -name CYCLONE_CONFIGURATION_DEVICE Auto
+set_global_assignment -name STRATIX_CONFIGURATION_DEVICE Auto
+set_global_assignment -name APEX20K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name STRATIX_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name MERCURY_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name FLEX10K_CONFIG_DEVICE_JTAG_USER_CODE FFFFFFFF
+set_global_assignment -name EPROM_USE_CHECKSUM_AS_USERCODE Off
+set_global_assignment -name AUTO_INCREMENT_CONFIG_DEVICE_JTAG_USER_CODE On
+set_global_assignment -name DISABLE_NCS_AND_OE_PULLUPS_ON_CONFIG_DEVICE Off
+set_global_assignment -name GENERATE_TTF_FILE Off
+set_global_assignment -name GENERATE_RBF_FILE Off
+set_global_assignment -name GENERATE_HEX_FILE Off
+set_global_assignment -name HEXOUT_FILE_START_ADDRESS 0
+set_global_assignment -name HEXOUT_FILE_COUNT_DIRECTION Up
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_NO_OUTPUT_GND "As output driving an unspecified signal"
+set_global_assignment -name RELEASE_CLEARS_BEFORE_TRI_STATES Off
+set_global_assignment -name AUTO_RESTART_CONFIGURATION On
+set_global_assignment -name HARDCOPYII_POWER_ON_EXTRA_DELAY Off
+set_global_assignment -name STRATIXII_MRAM_COMPATIBILITY Off
+set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY On
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V"
+set_global_assignment -name ENABLE_OCT_DONE On -family "MAX 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV E"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria 10"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Stratix V"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria V GZ"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Arria II GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone IV GX"
+set_global_assignment -name ENABLE_OCT_DONE Off -family "Cyclone V"
+set_global_assignment -name USE_CHECKERED_PATTERN_AS_UNINITIALIZED_RAM_CONTENT OFF
+set_global_assignment -name ARRIAIIGX_RX_CDR_LOCKUP_FIX_OVERRIDE Off
+set_global_assignment -name ENABLE_AUTONOMOUS_PCIE_HIP Off
+set_global_assignment -name ENABLE_ADV_SEU_DETECTION Off
+set_global_assignment -name POR_SCHEME "Instant ON"
+set_global_assignment -name EN_USER_IO_WEAK_PULLUP On
+set_global_assignment -name EN_SPI_IO_WEAK_PULLUP On
+set_global_assignment -name POF_VERIFY_PROTECT Off
+set_global_assignment -name ENABLE_SPI_MODE_CHECK Off
+set_global_assignment -name FORCE_SSMCLK_TO_ISMCLK On
+set_global_assignment -name FALLBACK_TO_EXTERNAL_FLASH Off
+set_global_assignment -name EXTERNAL_FLASH_FALLBACK_ADDRESS 0
+set_global_assignment -name START_TIME 0ns
+set_global_assignment -name SIMULATION_MODE TIMING
+set_global_assignment -name AUTO_USE_SIMULATION_PDB_NETLIST Off
+set_global_assignment -name ADD_DEFAULT_PINS_TO_SIMULATION_OUTPUT_WAVEFORMS On
+set_global_assignment -name SETUP_HOLD_DETECTION Off
+set_global_assignment -name SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off
+set_global_assignment -name CHECK_OUTPUTS Off
+set_global_assignment -name SIMULATION_COVERAGE On
+set_global_assignment -name SIMULATION_COMPLETE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_1_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name SIMULATION_MISSING_0_VALUE_COVERAGE_REPORT_PANEL On
+set_global_assignment -name GLITCH_DETECTION Off
+set_global_assignment -name GLITCH_INTERVAL 1ns
+set_global_assignment -name SIMULATOR_GENERATE_SIGNAL_ACTIVITY_FILE Off
+set_global_assignment -name SIMULATION_WITH_GLITCH_FILTERING_WHEN_GENERATING_SAF On
+set_global_assignment -name SIMULATION_BUS_CHANNEL_GROUPING Off
+set_global_assignment -name SIMULATION_VDB_RESULT_FLUSH On
+set_global_assignment -name VECTOR_COMPARE_TRIGGER_MODE INPUT_EDGE
+set_global_assignment -name SIMULATION_NETLIST_VIEWER Off
+set_global_assignment -name SIMULATION_INTERCONNECT_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATION_CELL_DELAY_MODEL_TYPE TRANSPORT
+set_global_assignment -name SIMULATOR_GENERATE_POWERPLAY_VCD_FILE Off
+set_global_assignment -name SIMULATOR_PVT_TIMING_MODEL_TYPE AUTO
+set_global_assignment -name SIMULATION_WITH_AUTO_GLITCH_FILTERING AUTO
+set_global_assignment -name DRC_TOP_FANOUT 50
+set_global_assignment -name DRC_FANOUT_EXCEEDING 30
+set_global_assignment -name DRC_GATED_CLOCK_FEED 30
+set_global_assignment -name HARDCOPY_FLOW_AUTOMATION MIGRATION_ONLY
+set_global_assignment -name ENABLE_DRC_SETTINGS Off
+set_global_assignment -name CLK_RULE_CLKNET_CLKSPINES_THRESHOLD 25
+set_global_assignment -name DRC_DETAIL_MESSAGE_LIMIT 10
+set_global_assignment -name DRC_VIOLATION_MESSAGE_LIMIT 30
+set_global_assignment -name DRC_DEADLOCK_STATE_LIMIT 2
+set_global_assignment -name MERGE_HEX_FILE Off
+set_global_assignment -name GENERATE_SVF_FILE Off
+set_global_assignment -name GENERATE_ISC_FILE Off
+set_global_assignment -name GENERATE_JAM_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE Off
+set_global_assignment -name GENERATE_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_SVF_FILE Off
+set_global_assignment -name GENERATE_CONFIG_ISC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JAM_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE Off
+set_global_assignment -name GENERATE_CONFIG_JBC_FILE_COMPRESSED On
+set_global_assignment -name GENERATE_CONFIG_HEXOUT_FILE Off
+set_global_assignment -name ISP_CLAMP_STATE_DEFAULT "Tri-state"
+set_global_assignment -name HPS_EARLY_IO_RELEASE Off
+set_global_assignment -name SIGNALPROBE_ALLOW_OVERUSE Off
+set_global_assignment -name SIGNALPROBE_DURING_NORMAL_COMPILATION Off
+set_global_assignment -name POWER_DEFAULT_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_DEFAULT_INPUT_IO_TOGGLE_RATE 12.5%
+set_global_assignment -name POWER_USE_PVA On
+set_global_assignment -name POWER_USE_INPUT_FILE "No File"
+set_global_assignment -name POWER_USE_INPUT_FILES Off
+set_global_assignment -name POWER_VCD_FILTER_GLITCHES On
+set_global_assignment -name POWER_REPORT_SIGNAL_ACTIVITY Off
+set_global_assignment -name POWER_REPORT_POWER_DISSIPATION Off
+set_global_assignment -name POWER_USE_DEVICE_CHARACTERISTICS TYPICAL
+set_global_assignment -name POWER_AUTO_COMPUTE_TJ On
+set_global_assignment -name POWER_TJ_VALUE 25
+set_global_assignment -name POWER_USE_TA_VALUE 25
+set_global_assignment -name POWER_USE_CUSTOM_COOLING_SOLUTION Off
+set_global_assignment -name POWER_BOARD_TEMPERATURE 25
+set_global_assignment -name POWER_HPS_ENABLE Off
+set_global_assignment -name POWER_HPS_PROC_FREQ 0.0
+set_global_assignment -name ENABLE_SMART_VOLTAGE_ID Off
+set_global_assignment -name IGNORE_PARTITIONS Off
+set_global_assignment -name AUTO_EXPORT_INCREMENTAL_COMPILATION Off
+set_global_assignment -name RAPID_RECOMPILE_ASSIGNMENT_CHECKING On
+set_global_assignment -name OUTPUT_IO_TIMING_ENDPOINT "Near End"
+set_global_assignment -name RTLV_REMOVE_FANOUT_FREE_REGISTERS On
+set_global_assignment -name RTLV_SIMPLIFIED_LOGIC On
+set_global_assignment -name RTLV_GROUP_RELATED_NODES On
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD Off
+set_global_assignment -name RTLV_GROUP_COMB_LOGIC_IN_CLOUD_TMV Off
+set_global_assignment -name RTLV_GROUP_RELATED_NODES_TMV On
+set_global_assignment -name EQC_CONSTANT_DFF_DETECTION On
+set_global_assignment -name EQC_DUPLICATE_DFF_DETECTION On
+set_global_assignment -name EQC_BBOX_MERGE On
+set_global_assignment -name EQC_LVDS_MERGE On
+set_global_assignment -name EQC_RAM_UNMERGING On
+set_global_assignment -name EQC_DFF_SS_EMULATION On
+set_global_assignment -name EQC_RAM_REGISTER_UNPACK On
+set_global_assignment -name EQC_MAC_REGISTER_UNPACK On
+set_global_assignment -name EQC_SET_PARTITION_BB_TO_VCC_GND On
+set_global_assignment -name EQC_STRUCTURE_MATCHING On
+set_global_assignment -name EQC_AUTO_BREAK_CONE On
+set_global_assignment -name EQC_POWER_UP_COMPARE Off
+set_global_assignment -name EQC_AUTO_COMP_LOOP_CUT On
+set_global_assignment -name EQC_AUTO_INVERSION On
+set_global_assignment -name EQC_AUTO_TERMINATE On
+set_global_assignment -name EQC_SUB_CONE_REPORT Off
+set_global_assignment -name EQC_RENAMING_RULES On
+set_global_assignment -name EQC_PARAMETER_CHECK On
+set_global_assignment -name EQC_AUTO_PORTSWAP On
+set_global_assignment -name EQC_DETECT_DONT_CARES On
+set_global_assignment -name EQC_SHOW_ALL_MAPPED_POINTS Off
+set_global_assignment -name EDA_INPUT_GND_NAME GND -section_id ?
+set_global_assignment -name EDA_INPUT_VCC_NAME VCC -section_id ?
+set_global_assignment -name EDA_INPUT_DATA_FORMAT NONE -section_id ?
+set_global_assignment -name EDA_SHOW_LMF_MAPPING_MESSAGES Off -section_id ?
+set_global_assignment -name EDA_RUN_TOOL_AUTOMATICALLY Off -section_id ?
+set_global_assignment -name RESYNTHESIS_RETIMING FULL -section_id ?
+set_global_assignment -name RESYNTHESIS_OPTIMIZATION_EFFORT Normal -section_id ?
+set_global_assignment -name RESYNTHESIS_PHYSICAL_SYNTHESIS Normal -section_id ?
+set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS On -section_id ?
+set_global_assignment -name VCCPD_VOLTAGE 3.3V -section_id ?
+set_global_assignment -name EDA_USER_COMPILED_SIMULATION_LIBRARY_DIRECTORY "<None>" -section_id ?
+set_global_assignment -name EDA_LAUNCH_CMD_LINE_TOOL Off -section_id ?
+set_global_assignment -name EDA_ENABLE_IPUTF_MODE On -section_id ?
+set_global_assignment -name EDA_NATIVELINK_PORTABLE_FILE_PATHS Off -section_id ?
+set_global_assignment -name EDA_NATIVELINK_GENERATE_SCRIPT_ONLY Off -section_id ?
+set_global_assignment -name EDA_WAIT_FOR_GUI_TOOL_COMPLETION Off -section_id ?
+set_global_assignment -name EDA_TRUNCATE_LONG_HIERARCHY_PATHS Off -section_id ?
+set_global_assignment -name EDA_FLATTEN_BUSES Off -section_id ?
+set_global_assignment -name EDA_MAP_ILLEGAL_CHARACTERS Off -section_id ?
+set_global_assignment -name EDA_GENERATE_TIMING_CLOSURE_DATA Off -section_id ?
+set_global_assignment -name EDA_GENERATE_POWER_INPUT_FILE Off -section_id ?
+set_global_assignment -name EDA_TEST_BENCH_ENABLE_STATUS NOT_USED -section_id ?
+set_global_assignment -name EDA_RTL_SIM_MODE NOT_USED -section_id ?
+set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY OFF -section_id ?
+set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST Off -section_id ?
+set_global_assignment -name EDA_WRITE_DEVICE_CONTROL_PORTS Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_TCL_FILE Off -section_id ?
+set_global_assignment -name EDA_SIMULATION_VCD_OUTPUT_SIGNALS_TO_TCL_FILE "All Except Combinational Logic Element Outputs" -section_id ?
+set_global_assignment -name EDA_ENABLE_GLITCH_FILTERING Off -section_id ?
+set_global_assignment -name EDA_WRITE_NODES_FOR_POWER_ESTIMATION OFF -section_id ?
+set_global_assignment -name EDA_SETUP_HOLD_DETECTION_INPUT_REGISTERS_BIDIR_PINS_DISABLED Off -section_id ?
+set_global_assignment -name EDA_WRITER_DONT_WRITE_TOP_ENTITY Off -section_id ?
+set_global_assignment -name EDA_VHDL_ARCH_NAME structure -section_id ?
+set_global_assignment -name EDA_IBIS_MODEL_SELECTOR Off -section_id ?
+set_global_assignment -name EDA_IBIS_MUTUAL_COUPLING Off -section_id ?
+set_global_assignment -name EDA_FORMAL_VERIFICATION_ALLOW_RETIMING Off -section_id ?
+set_global_assignment -name EDA_BOARD_BOUNDARY_SCAN_OPERATION PRE_CONFIG -section_id ?
+set_global_assignment -name EDA_GENERATE_RTL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_GENERATE_GATE_LEVEL_SIMULATION_COMMAND_SCRIPT Off -section_id ?
+set_global_assignment -name EDA_IBIS_SPECIFICATION_VERSION 4p1 -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_OFFSET 0ns -section_id ?
+set_global_assignment -name SIM_VECTOR_COMPARED_CLOCK_DUTY_CYCLE 50 -section_id ?
+set_global_assignment -name APEX20K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MAX7K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name MERCURY_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX6K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name FLEX10K_CLIQUE_TYPE LAB -section_id ? -entity ?
+set_global_assignment -name PARTITION_PRESERVE_HIGH_SPEED_TILES On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IGNORE_SOURCE_FILE_CHANGES Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ALWAYS_USE_QXP_NETLIST Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_ASSIGNMENTS REPLACE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_EXISTING_LOGICLOCK_REGIONS UPDATE_CONFLICTING -section_id ? -entity ?
+set_global_assignment -name PARTITION_IMPORT_PROMOTE_ASSIGNMENTS On -section_id ? -entity ?
+set_global_assignment -name ALLOW_MULTIPLE_PERSONAS Off -section_id ? -entity ?
+set_global_assignment -name PARTITION_ASD_REGION_ID 1 -section_id ? -entity ?
+set_global_assignment -name CROSS_BOUNDARY_OPTIMIZATIONS Off -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_CONSTANTS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PROPAGATE_INVERSIONS_ON_INPUTS On -section_id ? -entity ?
+set_global_assignment -name REMOVE_LOGIC_ON_UNCONNECTED_OUTPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_INPUTS On -section_id ? -entity ?
+set_global_assignment -name MERGE_EQUIVALENT_BIDIRS On -section_id ? -entity ?
+set_global_assignment -name ABSORB_PATHS_FROM_OUTPUTS_TO_INPUTS On -section_id ? -entity ?
+set_global_assignment -name PARTITION_ENABLE_STRICT_PRESERVATION Off -section_id ? -entity ?

logic/PT_0104_fpga.v

@@ -0,0 +1,35 @@
+module PT_0104_fpga (
+  input         sys_clock,
+  input         bus_clock,
+  input         resetn,
+  input         stop,
+  input  [1:0]  mem_ahb_htrans,
+  input         mem_ahb_hready,
+  input         mem_ahb_hwrite,
+  input  [31:0] mem_ahb_haddr,
+  input  [2:0]  mem_ahb_hsize,
+  input  [2:0]  mem_ahb_hburst,
+  input  [31:0] mem_ahb_hwdata,
+  output tri1   mem_ahb_hreadyout,
+  output        mem_ahb_hresp,
+  output [31:0] mem_ahb_hrdata,
+  output        slave_ahb_hsel,
+  output tri1   slave_ahb_hready,
+  input         slave_ahb_hreadyout,
+  output [1:0]  slave_ahb_htrans,
+  output [2:0]  slave_ahb_hsize,
+  output [2:0]  slave_ahb_hburst,
+  output        slave_ahb_hwrite,
+  output [31:0] slave_ahb_haddr,
+  output [31:0] slave_ahb_hwdata,
+  input         slave_ahb_hresp,
+  input  [31:0] slave_ahb_hrdata,
+  output [3:0]  ext_dma_DMACBREQ,
+  output [3:0]  ext_dma_DMACLBREQ,
+  output [3:0]  ext_dma_DMACSREQ,
+  output [3:0]  ext_dma_DMACLSREQ,
+  input  [3:0]  ext_dma_DMACCLR,
+  input  [3:0]  ext_dma_DMACTC,
+  output [3:0]  local_int
+);
+endmodule

logic/PT_0104_routed.v

@@ -0,0 +1,2173 @@
+`timescale 1 ps/ 1 ps
+
+module top(
+	PIN_15,
+	PIN_16,
+	PIN_17,
+	PIN_18,
+	PIN_2,
+	PIN_23,
+	PIN_24,
+	PIN_25,
+	PIN_26,
+	PIN_3,
+	PIN_4,
+	PIN_68,
+	PIN_69,
+	PIN_7,
+	PIN_80,
+	PIN_83,
+	PIN_88,
+	PIN_91,
+	PIN_92,
+	PIN_93,
+	PIN_95,
+	PIN_96,
+	PIN_97,
+	PIN_98,
+	PIN_HSE,
+	PIN_HSI,
+	PIN_OSC);
+inout	PIN_15;
+inout	PIN_16;
+inout	PIN_17;
+inout	PIN_18;
+inout	PIN_2;
+inout	PIN_23;
+inout	PIN_24;
+output	PIN_25;
+input	PIN_26;
+inout	PIN_3;
+inout	PIN_4;
+output	PIN_68;
+input	PIN_69;
+inout	PIN_7;
+output	PIN_80;
+input	PIN_83;
+inout	PIN_88;
+inout	PIN_91;
+inout	PIN_92;
+inout	PIN_93;
+inout	PIN_95;
+inout	PIN_96;
+inout	PIN_97;
+inout	PIN_98;
+input	PIN_HSE;
+input	PIN_HSI;
+input	PIN_OSC;
+
+//wire	gnd;
+//wire	vcc;
+wire	\PIN_15~input_o ;
+wire	\PIN_16~input_o ;
+wire	\PIN_17~input_o ;
+wire	\PIN_18~input_o ;
+wire	\PIN_23~input_o ;
+wire	\PIN_24~input_o ;
+wire	\PIN_26~input_o ;
+wire	\PIN_2~input_o ;
+wire	\PIN_3~input_o ;
+wire	\PIN_4~input_o ;
+wire	\PIN_69~input_o ;
+wire	\PIN_7~input_o ;
+wire	\PIN_83~input_o ;
+wire	\PIN_88~input_o ;
+wire	\PIN_91~input_o ;
+wire	\PIN_92~input_o ;
+wire	\PIN_93~input_o ;
+wire	\PIN_95~input_o ;
+wire	\PIN_96~input_o ;
+wire	\PIN_97~input_o ;
+wire	\PIN_98~input_o ;
+wire	\PIN_HSE~input_o ;
+wire	\PIN_HSI~input_o ;
+wire	\PIN_OSC~input_o ;
+wire	\PLL_ENABLE~clkctrl_outclk ;
+wire	\PLL_ENABLE~clkctrl_outclk__AsyncReset_X50_Y1_SIG ;
+wire	\PLL_ENABLE~combout ;
+wire	\PLL_LOCK~combout ;
+wire	\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp ;
+wire	\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp_X50_Y1_SIG_VCC ;
+wire	\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ;
+tri1	devclrn;
+tri1	devoe;
+tri1	devpor;
+wire	[3:0] ext_dma_DMACBREQ;
+//wire	ext_dma_DMACBREQ[0];
+//wire	ext_dma_DMACBREQ[1];
+//wire	ext_dma_DMACBREQ[2];
+//wire	ext_dma_DMACBREQ[3];
+wire	[3:0] ext_dma_DMACLBREQ;
+//wire	ext_dma_DMACLBREQ[0];
+//wire	ext_dma_DMACLBREQ[1];
+//wire	ext_dma_DMACLBREQ[2];
+//wire	ext_dma_DMACLBREQ[3];
+wire	[3:0] ext_dma_DMACLSREQ;
+//wire	ext_dma_DMACLSREQ[0];
+//wire	ext_dma_DMACLSREQ[1];
+//wire	ext_dma_DMACLSREQ[2];
+//wire	ext_dma_DMACLSREQ[3];
+wire	[3:0] ext_dma_DMACSREQ;
+//wire	ext_dma_DMACSREQ[0];
+//wire	ext_dma_DMACSREQ[1];
+//wire	ext_dma_DMACSREQ[2];
+//wire	ext_dma_DMACSREQ[3];
+wire	\gclksw_inst|gclk_switch__alta_gclksw__clkout ;
+wire	[7:0] gpio0_io_in;
+//wire	gpio0_io_in[0];
+//wire	gpio0_io_in[1];
+//wire	gpio0_io_in[2];
+//wire	gpio0_io_in[3];
+//wire	gpio0_io_in[4];
+//wire	gpio0_io_in[5];
+//wire	gpio0_io_in[6];
+//wire	gpio0_io_in[7];
+wire	[7:0] gpio0_io_out_data;
+//wire	gpio0_io_out_data[0];
+//wire	gpio0_io_out_data[1];
+//wire	gpio0_io_out_data[2];
+//wire	gpio0_io_out_data[3];
+//wire	gpio0_io_out_data[4];
+//wire	gpio0_io_out_data[5];
+//wire	gpio0_io_out_data[6];
+//wire	gpio0_io_out_data[7];
+wire	[7:0] gpio0_io_out_en;
+//wire	gpio0_io_out_en[0];
+//wire	gpio0_io_out_en[1];
+//wire	gpio0_io_out_en[2];
+//wire	gpio0_io_out_en[3];
+//wire	gpio0_io_out_en[4];
+//wire	gpio0_io_out_en[5];
+//wire	gpio0_io_out_en[6];
+//wire	gpio0_io_out_en[7];
+wire	[7:0] gpio1_io_in;
+//wire	gpio1_io_in[0];
+//wire	gpio1_io_in[1];
+//wire	gpio1_io_in[2];
+//wire	gpio1_io_in[3];
+//wire	gpio1_io_in[4];
+//wire	gpio1_io_in[5];
+//wire	gpio1_io_in[6];
+//wire	gpio1_io_in[7];
+wire	[7:0] gpio1_io_out_data;
+//wire	gpio1_io_out_data[0];
+//wire	gpio1_io_out_data[1];
+//wire	gpio1_io_out_data[2];
+//wire	gpio1_io_out_data[3];
+//wire	gpio1_io_out_data[4];
+//wire	gpio1_io_out_data[5];
+//wire	gpio1_io_out_data[6];
+//wire	gpio1_io_out_data[7];
+wire	[7:0] gpio1_io_out_en;
+//wire	gpio1_io_out_en[0];
+//wire	gpio1_io_out_en[1];
+//wire	gpio1_io_out_en[2];
+//wire	gpio1_io_out_en[3];
+//wire	gpio1_io_out_en[4];
+//wire	gpio1_io_out_en[5];
+//wire	gpio1_io_out_en[6];
+//wire	gpio1_io_out_en[7];
+wire	[7:0] gpio2_io_in;
+//wire	gpio2_io_in[0];
+//wire	gpio2_io_in[1];
+//wire	gpio2_io_in[2];
+//wire	gpio2_io_in[3];
+//wire	gpio2_io_in[4];
+//wire	gpio2_io_in[5];
+//wire	gpio2_io_in[6];
+//wire	gpio2_io_in[7];
+wire	[7:0] gpio2_io_out_data;
+//wire	gpio2_io_out_data[0];
+//wire	gpio2_io_out_data[1];
+//wire	gpio2_io_out_data[2];
+//wire	gpio2_io_out_data[3];
+//wire	gpio2_io_out_data[4];
+//wire	gpio2_io_out_data[5];
+//wire	gpio2_io_out_data[6];
+//wire	gpio2_io_out_data[7];
+wire	[7:0] gpio2_io_out_en;
+//wire	gpio2_io_out_en[0];
+//wire	gpio2_io_out_en[1];
+//wire	gpio2_io_out_en[2];
+//wire	gpio2_io_out_en[3];
+//wire	gpio2_io_out_en[4];
+//wire	gpio2_io_out_en[5];
+//wire	gpio2_io_out_en[6];
+//wire	gpio2_io_out_en[7];
+wire	[7:0] gpio3_io_in;
+//wire	gpio3_io_in[0];
+//wire	gpio3_io_in[1];
+//wire	gpio3_io_in[2];
+//wire	gpio3_io_in[3];
+//wire	gpio3_io_in[4];
+//wire	gpio3_io_in[5];
+//wire	gpio3_io_in[6];
+//wire	gpio3_io_in[7];
+wire	[7:0] gpio4_io_in;
+//wire	gpio4_io_in[0];
+//wire	gpio4_io_in[1];
+//wire	gpio4_io_in[2];
+//wire	gpio4_io_in[3];
+//wire	gpio4_io_in[4];
+//wire	gpio4_io_in[5];
+//wire	gpio4_io_in[6];
+//wire	gpio4_io_in[7];
+wire	[7:0] gpio5_io_in;
+//wire	gpio5_io_in[0];
+//wire	gpio5_io_in[1];
+//wire	gpio5_io_in[2];
+//wire	gpio5_io_in[3];
+//wire	gpio5_io_in[4];
+//wire	gpio5_io_in[5];
+//wire	gpio5_io_in[6];
+//wire	gpio5_io_in[7];
+wire	[7:0] gpio5_io_out_data;
+//wire	gpio5_io_out_data[0];
+//wire	gpio5_io_out_data[1];
+//wire	gpio5_io_out_data[2];
+//wire	gpio5_io_out_data[3];
+//wire	gpio5_io_out_data[4];
+//wire	gpio5_io_out_data[5];
+//wire	gpio5_io_out_data[6];
+//wire	gpio5_io_out_data[7];
+wire	[7:0] gpio5_io_out_en;
+//wire	gpio5_io_out_en[0];
+//wire	gpio5_io_out_en[1];
+//wire	gpio5_io_out_en[2];
+//wire	gpio5_io_out_en[3];
+//wire	gpio5_io_out_en[4];
+//wire	gpio5_io_out_en[5];
+//wire	gpio5_io_out_en[6];
+//wire	gpio5_io_out_en[7];
+wire	[7:0] gpio6_io_in;
+//wire	gpio6_io_in[0];
+//wire	gpio6_io_in[1];
+//wire	gpio6_io_in[2];
+//wire	gpio6_io_in[3];
+//wire	gpio6_io_in[4];
+//wire	gpio6_io_in[5];
+//wire	gpio6_io_in[6];
+//wire	gpio6_io_in[7];
+wire	[7:0] gpio7_io_in;
+//wire	gpio7_io_in[0];
+//wire	gpio7_io_in[1];
+//wire	gpio7_io_in[2];
+//wire	gpio7_io_in[3];
+//wire	gpio7_io_in[4];
+//wire	gpio7_io_in[5];
+//wire	gpio7_io_in[6];
+//wire	gpio7_io_in[7];
+wire	[7:0] gpio7_io_out_data;
+//wire	gpio7_io_out_data[0];
+//wire	gpio7_io_out_data[1];
+//wire	gpio7_io_out_data[2];
+//wire	gpio7_io_out_data[3];
+//wire	gpio7_io_out_data[4];
+//wire	gpio7_io_out_data[5];
+//wire	gpio7_io_out_data[6];
+//wire	gpio7_io_out_data[7];
+wire	[7:0] gpio7_io_out_en;
+//wire	gpio7_io_out_en[0];
+//wire	gpio7_io_out_en[1];
+//wire	gpio7_io_out_en[2];
+//wire	gpio7_io_out_en[3];
+//wire	gpio7_io_out_en[4];
+//wire	gpio7_io_out_en[5];
+//wire	gpio7_io_out_en[6];
+//wire	gpio7_io_out_en[7];
+wire	[7:0] gpio8_io_in;
+//wire	gpio8_io_in[0];
+//wire	gpio8_io_in[1];
+//wire	gpio8_io_in[2];
+//wire	gpio8_io_in[3];
+//wire	gpio8_io_in[4];
+//wire	gpio8_io_in[5];
+//wire	gpio8_io_in[6];
+//wire	gpio8_io_in[7];
+wire	[7:0] gpio8_io_out_data;
+//wire	gpio8_io_out_data[0];
+//wire	gpio8_io_out_data[1];
+//wire	gpio8_io_out_data[2];
+//wire	gpio8_io_out_data[3];
+//wire	gpio8_io_out_data[4];
+//wire	gpio8_io_out_data[5];
+//wire	gpio8_io_out_data[6];
+//wire	gpio8_io_out_data[7];
+wire	[7:0] gpio8_io_out_en;
+//wire	gpio8_io_out_en[0];
+//wire	gpio8_io_out_en[1];
+//wire	gpio8_io_out_en[2];
+//wire	gpio8_io_out_en[3];
+//wire	gpio8_io_out_en[4];
+//wire	gpio8_io_out_en[5];
+//wire	gpio8_io_out_en[6];
+//wire	gpio8_io_out_en[7];
+wire	[7:0] gpio9_io_in;
+//wire	gpio9_io_in[0];
+//wire	gpio9_io_in[1];
+//wire	gpio9_io_in[2];
+//wire	gpio9_io_in[3];
+//wire	gpio9_io_in[4];
+//wire	gpio9_io_in[5];
+//wire	gpio9_io_in[6];
+//wire	gpio9_io_in[7];
+wire	hbi_274_0_9cb2c0024f9919c5_bp;
+wire	hbi_274_1_9cb2c0024f9919c5_bp;
+wire	[3:0] local_int;
+//wire	local_int[0];
+//wire	local_int[1];
+//wire	local_int[2];
+//wire	local_int[3];
+wire	[31:0] mem_ahb_hrdata;
+//wire	mem_ahb_hrdata[0];
+//wire	mem_ahb_hrdata[10];
+//wire	mem_ahb_hrdata[11];
+//wire	mem_ahb_hrdata[12];
+//wire	mem_ahb_hrdata[13];
+//wire	mem_ahb_hrdata[14];
+//wire	mem_ahb_hrdata[15];
+//wire	mem_ahb_hrdata[16];
+//wire	mem_ahb_hrdata[17];
+//wire	mem_ahb_hrdata[18];
+//wire	mem_ahb_hrdata[19];
+//wire	mem_ahb_hrdata[1];
+//wire	mem_ahb_hrdata[20];
+//wire	mem_ahb_hrdata[21];
+//wire	mem_ahb_hrdata[22];
+//wire	mem_ahb_hrdata[23];
+//wire	mem_ahb_hrdata[24];
+//wire	mem_ahb_hrdata[25];
+//wire	mem_ahb_hrdata[26];
+//wire	mem_ahb_hrdata[27];
+//wire	mem_ahb_hrdata[28];
+//wire	mem_ahb_hrdata[29];
+//wire	mem_ahb_hrdata[2];
+//wire	mem_ahb_hrdata[30];
+//wire	mem_ahb_hrdata[31];
+//wire	mem_ahb_hrdata[3];
+//wire	mem_ahb_hrdata[4];
+//wire	mem_ahb_hrdata[5];
+//wire	mem_ahb_hrdata[6];
+//wire	mem_ahb_hrdata[7];
+//wire	mem_ahb_hrdata[8];
+//wire	mem_ahb_hrdata[9];
+wire	\mem_ahb_hreadyout~combout ;
+wire	\mem_ahb_hresp~combout ;
+wire	[4:0] \pll_inst|auto_generated|clk ;
+//wire	\pll_inst|auto_generated|clk [0];
+//wire	\pll_inst|auto_generated|clk [1];
+//wire	\pll_inst|auto_generated|clk [2];
+//wire	\pll_inst|auto_generated|clk [3];
+//wire	\pll_inst|auto_generated|clk [4];
+wire	[4:0] \pll_inst|auto_generated|pll1_CLK_bus ;
+//wire	\pll_inst|auto_generated|pll1_CLK_bus [0];
+//wire	\pll_inst|auto_generated|pll1_CLK_bus [1];
+//wire	\pll_inst|auto_generated|pll1_CLK_bus [2];
+//wire	\pll_inst|auto_generated|pll1_CLK_bus [3];
+//wire	\pll_inst|auto_generated|pll1_CLK_bus [4];
+wire	\pll_inst|auto_generated|pll1~FBOUT ;
+wire	\pll_inst|auto_generated|pll_lock_sync~feeder_combout ;
+wire	\pll_inst|auto_generated|pll_lock_sync~q ;
+wire	\rv32.dmactive ;
+wire	\rv32.ext_dma_DMACCLR[0] ;
+wire	\rv32.ext_dma_DMACCLR[1] ;
+wire	\rv32.ext_dma_DMACCLR[2] ;
+wire	\rv32.ext_dma_DMACCLR[3] ;
+wire	\rv32.ext_dma_DMACTC[0] ;
+wire	\rv32.ext_dma_DMACTC[1] ;
+wire	\rv32.ext_dma_DMACTC[2] ;
+wire	\rv32.ext_dma_DMACTC[3] ;
+wire	\rv32.gpio0_io_out_data[0] ;
+wire	\rv32.gpio0_io_out_data[1] ;
+wire	\rv32.gpio0_io_out_data[2] ;
+wire	\rv32.gpio0_io_out_data[3] ;
+wire	\rv32.gpio0_io_out_data[4] ;
+wire	\rv32.gpio0_io_out_data[5] ;
+wire	\rv32.gpio0_io_out_data[6] ;
+wire	\rv32.gpio0_io_out_data[7] ;
+wire	\rv32.gpio0_io_out_en[0] ;
+wire	\rv32.gpio0_io_out_en[1] ;
+wire	\rv32.gpio0_io_out_en[2] ;
+wire	\rv32.gpio0_io_out_en[3] ;
+wire	\rv32.gpio0_io_out_en[4] ;
+wire	\rv32.gpio0_io_out_en[5] ;
+wire	\rv32.gpio0_io_out_en[6] ;
+wire	\rv32.gpio0_io_out_en[7] ;
+wire	\rv32.gpio1_io_out_data[0] ;
+wire	\rv32.gpio1_io_out_data[1] ;
+wire	\rv32.gpio1_io_out_data[2] ;
+wire	\rv32.gpio1_io_out_data[3] ;
+wire	\rv32.gpio1_io_out_data[4] ;
+wire	\rv32.gpio1_io_out_data[5] ;
+wire	\rv32.gpio1_io_out_data[6] ;
+wire	\rv32.gpio1_io_out_data[7] ;
+wire	\rv32.gpio1_io_out_en[0] ;
+wire	\rv32.gpio1_io_out_en[1] ;
+wire	\rv32.gpio1_io_out_en[2] ;
+wire	\rv32.gpio1_io_out_en[3] ;
+wire	\rv32.gpio1_io_out_en[4] ;
+wire	\rv32.gpio1_io_out_en[5] ;
+wire	\rv32.gpio1_io_out_en[6] ;
+wire	\rv32.gpio1_io_out_en[7] ;
+wire	\rv32.gpio2_io_out_data[0] ;
+wire	\rv32.gpio2_io_out_data[1] ;
+wire	\rv32.gpio2_io_out_data[2] ;
+wire	\rv32.gpio2_io_out_data[3] ;
+wire	\rv32.gpio2_io_out_data[4] ;
+wire	\rv32.gpio2_io_out_data[5] ;
+wire	\rv32.gpio2_io_out_data[6] ;
+wire	\rv32.gpio2_io_out_data[7] ;
+wire	\rv32.gpio2_io_out_en[0] ;
+wire	\rv32.gpio2_io_out_en[1] ;
+wire	\rv32.gpio2_io_out_en[2] ;
+wire	\rv32.gpio2_io_out_en[3] ;
+wire	\rv32.gpio2_io_out_en[4] ;
+wire	\rv32.gpio2_io_out_en[5] ;
+wire	\rv32.gpio2_io_out_en[6] ;
+wire	\rv32.gpio2_io_out_en[7] ;
+wire	\rv32.gpio3_io_out_data[0] ;
+wire	\rv32.gpio3_io_out_data[1] ;
+wire	\rv32.gpio3_io_out_data[2] ;
+wire	\rv32.gpio3_io_out_data[3] ;
+wire	\rv32.gpio3_io_out_data[4] ;
+wire	\rv32.gpio3_io_out_data[5] ;
+wire	\rv32.gpio3_io_out_data[6] ;
+wire	\rv32.gpio3_io_out_data[7] ;
+wire	\rv32.gpio3_io_out_en[0] ;
+wire	\rv32.gpio3_io_out_en[1] ;
+wire	\rv32.gpio3_io_out_en[2] ;
+wire	\rv32.gpio3_io_out_en[3] ;
+wire	\rv32.gpio3_io_out_en[4] ;
+wire	\rv32.gpio3_io_out_en[5] ;
+wire	\rv32.gpio3_io_out_en[6] ;
+wire	\rv32.gpio3_io_out_en[7] ;
+wire	\rv32.gpio4_io_out_data[0] ;
+wire	\rv32.gpio4_io_out_data[1] ;
+wire	\rv32.gpio4_io_out_data[2] ;
+wire	\rv32.gpio4_io_out_data[3] ;
+wire	\rv32.gpio4_io_out_data[4] ;
+wire	\rv32.gpio4_io_out_data[5] ;
+wire	\rv32.gpio4_io_out_data[6] ;
+wire	\rv32.gpio4_io_out_data[7] ;
+wire	\rv32.gpio4_io_out_en[0] ;
+wire	\rv32.gpio4_io_out_en[1] ;
+wire	\rv32.gpio4_io_out_en[2] ;
+wire	\rv32.gpio4_io_out_en[3] ;
+wire	\rv32.gpio4_io_out_en[4] ;
+wire	\rv32.gpio4_io_out_en[5] ;
+wire	\rv32.gpio4_io_out_en[6] ;
+wire	\rv32.gpio4_io_out_en[7] ;
+wire	\rv32.gpio5_io_out_data[0] ;
+wire	\rv32.gpio5_io_out_data[1] ;
+wire	\rv32.gpio5_io_out_data[2] ;
+wire	\rv32.gpio5_io_out_data[3] ;
+wire	\rv32.gpio5_io_out_data[4] ;
+wire	\rv32.gpio5_io_out_data[5] ;
+wire	\rv32.gpio5_io_out_data[6] ;
+wire	\rv32.gpio5_io_out_data[7] ;
+wire	\rv32.gpio5_io_out_en[0] ;
+wire	\rv32.gpio5_io_out_en[1] ;
+wire	\rv32.gpio5_io_out_en[2] ;
+wire	\rv32.gpio5_io_out_en[3] ;
+wire	\rv32.gpio5_io_out_en[4] ;
+wire	\rv32.gpio5_io_out_en[5] ;
+wire	\rv32.gpio5_io_out_en[6] ;
+wire	\rv32.gpio5_io_out_en[7] ;
+wire	\rv32.gpio6_io_out_data[0] ;
+wire	\rv32.gpio6_io_out_data[1] ;
+wire	\rv32.gpio6_io_out_data[2] ;
+wire	\rv32.gpio6_io_out_data[3] ;
+wire	\rv32.gpio6_io_out_data[4] ;
+wire	\rv32.gpio6_io_out_data[5] ;
+wire	\rv32.gpio6_io_out_data[6] ;
+wire	\rv32.gpio6_io_out_data[7] ;
+wire	\rv32.gpio6_io_out_en[0] ;
+wire	\rv32.gpio6_io_out_en[1] ;
+wire	\rv32.gpio6_io_out_en[2] ;
+wire	\rv32.gpio6_io_out_en[3] ;
+wire	\rv32.gpio6_io_out_en[4] ;
+wire	\rv32.gpio6_io_out_en[5] ;
+wire	\rv32.gpio6_io_out_en[6] ;
+wire	\rv32.gpio6_io_out_en[7] ;
+wire	\rv32.gpio7_io_out_data[0] ;
+wire	\rv32.gpio7_io_out_data[1] ;
+wire	\rv32.gpio7_io_out_data[2] ;
+wire	\rv32.gpio7_io_out_data[3] ;
+wire	\rv32.gpio7_io_out_data[4] ;
+wire	\rv32.gpio7_io_out_data[5] ;
+wire	\rv32.gpio7_io_out_data[6] ;
+wire	\rv32.gpio7_io_out_data[7] ;
+wire	\rv32.gpio7_io_out_en[0] ;
+wire	\rv32.gpio7_io_out_en[1] ;
+wire	\rv32.gpio7_io_out_en[2] ;
+wire	\rv32.gpio7_io_out_en[3] ;
+wire	\rv32.gpio7_io_out_en[4] ;
+wire	\rv32.gpio7_io_out_en[5] ;
+wire	\rv32.gpio7_io_out_en[6] ;
+wire	\rv32.gpio7_io_out_en[7] ;
+wire	\rv32.gpio8_io_out_data[0] ;
+wire	\rv32.gpio8_io_out_data[1] ;
+wire	\rv32.gpio8_io_out_data[2] ;
+wire	\rv32.gpio8_io_out_data[3] ;
+wire	\rv32.gpio8_io_out_data[4] ;
+wire	\rv32.gpio8_io_out_data[5] ;
+wire	\rv32.gpio8_io_out_data[6] ;
+wire	\rv32.gpio8_io_out_data[7] ;
+wire	\rv32.gpio8_io_out_en[0] ;
+wire	\rv32.gpio8_io_out_en[1] ;
+wire	\rv32.gpio8_io_out_en[2] ;
+wire	\rv32.gpio8_io_out_en[3] ;
+wire	\rv32.gpio8_io_out_en[4] ;
+wire	\rv32.gpio8_io_out_en[5] ;
+wire	\rv32.gpio8_io_out_en[6] ;
+wire	\rv32.gpio8_io_out_en[7] ;
+wire	\rv32.gpio9_io_out_data[0] ;
+wire	\rv32.gpio9_io_out_data[1] ;
+wire	\rv32.gpio9_io_out_data[2] ;
+wire	\rv32.gpio9_io_out_data[3] ;
+wire	\rv32.gpio9_io_out_data[4] ;
+wire	\rv32.gpio9_io_out_data[5] ;
+wire	\rv32.gpio9_io_out_data[6] ;
+wire	\rv32.gpio9_io_out_data[7] ;
+wire	\rv32.gpio9_io_out_en[0] ;
+wire	\rv32.gpio9_io_out_en[1] ;
+wire	\rv32.gpio9_io_out_en[2] ;
+wire	\rv32.gpio9_io_out_en[3] ;
+wire	\rv32.gpio9_io_out_en[4] ;
+wire	\rv32.gpio9_io_out_en[5] ;
+wire	\rv32.gpio9_io_out_en[6] ;
+wire	\rv32.gpio9_io_out_en[7] ;
+wire	\rv32.mem_ahb_haddr[0] ;
+wire	\rv32.mem_ahb_haddr[10] ;
+wire	\rv32.mem_ahb_haddr[11] ;
+wire	\rv32.mem_ahb_haddr[12] ;
+wire	\rv32.mem_ahb_haddr[13] ;
+wire	\rv32.mem_ahb_haddr[14] ;
+wire	\rv32.mem_ahb_haddr[15] ;
+wire	\rv32.mem_ahb_haddr[16] ;
+wire	\rv32.mem_ahb_haddr[17] ;
+wire	\rv32.mem_ahb_haddr[18] ;
+wire	\rv32.mem_ahb_haddr[19] ;
+wire	\rv32.mem_ahb_haddr[1] ;
+wire	\rv32.mem_ahb_haddr[20] ;
+wire	\rv32.mem_ahb_haddr[21] ;
+wire	\rv32.mem_ahb_haddr[22] ;
+wire	\rv32.mem_ahb_haddr[23] ;
+wire	\rv32.mem_ahb_haddr[24] ;
+wire	\rv32.mem_ahb_haddr[25] ;
+wire	\rv32.mem_ahb_haddr[26] ;
+wire	\rv32.mem_ahb_haddr[27] ;
+wire	\rv32.mem_ahb_haddr[28] ;
+wire	\rv32.mem_ahb_haddr[29] ;
+wire	\rv32.mem_ahb_haddr[2] ;
+wire	\rv32.mem_ahb_haddr[30] ;
+wire	\rv32.mem_ahb_haddr[31] ;
+wire	\rv32.mem_ahb_haddr[3] ;
+wire	\rv32.mem_ahb_haddr[4] ;
+wire	\rv32.mem_ahb_haddr[5] ;
+wire	\rv32.mem_ahb_haddr[6] ;
+wire	\rv32.mem_ahb_haddr[7] ;
+wire	\rv32.mem_ahb_haddr[8] ;
+wire	\rv32.mem_ahb_haddr[9] ;
+wire	\rv32.mem_ahb_hburst[0] ;
+wire	\rv32.mem_ahb_hburst[1] ;
+wire	\rv32.mem_ahb_hburst[2] ;
+wire	\rv32.mem_ahb_hready ;
+wire	\rv32.mem_ahb_hsize[0] ;
+wire	\rv32.mem_ahb_hsize[1] ;
+wire	\rv32.mem_ahb_hsize[2] ;
+wire	\rv32.mem_ahb_htrans[0] ;
+wire	\rv32.mem_ahb_htrans[1] ;
+wire	\rv32.mem_ahb_hwdata[0] ;
+wire	\rv32.mem_ahb_hwdata[10] ;
+wire	\rv32.mem_ahb_hwdata[11] ;
+wire	\rv32.mem_ahb_hwdata[12] ;
+wire	\rv32.mem_ahb_hwdata[13] ;
+wire	\rv32.mem_ahb_hwdata[14] ;
+wire	\rv32.mem_ahb_hwdata[15] ;
+wire	\rv32.mem_ahb_hwdata[16] ;
+wire	\rv32.mem_ahb_hwdata[17] ;
+wire	\rv32.mem_ahb_hwdata[18] ;
+wire	\rv32.mem_ahb_hwdata[19] ;
+wire	\rv32.mem_ahb_hwdata[1] ;
+wire	\rv32.mem_ahb_hwdata[20] ;
+wire	\rv32.mem_ahb_hwdata[21] ;
+wire	\rv32.mem_ahb_hwdata[22] ;
+wire	\rv32.mem_ahb_hwdata[23] ;
+wire	\rv32.mem_ahb_hwdata[24] ;
+wire	\rv32.mem_ahb_hwdata[25] ;
+wire	\rv32.mem_ahb_hwdata[26] ;
+wire	\rv32.mem_ahb_hwdata[27] ;
+wire	\rv32.mem_ahb_hwdata[28] ;
+wire	\rv32.mem_ahb_hwdata[29] ;
+wire	\rv32.mem_ahb_hwdata[2] ;
+wire	\rv32.mem_ahb_hwdata[30] ;
+wire	\rv32.mem_ahb_hwdata[31] ;
+wire	\rv32.mem_ahb_hwdata[3] ;
+wire	\rv32.mem_ahb_hwdata[4] ;
+wire	\rv32.mem_ahb_hwdata[5] ;
+wire	\rv32.mem_ahb_hwdata[6] ;
+wire	\rv32.mem_ahb_hwdata[7] ;
+wire	\rv32.mem_ahb_hwdata[8] ;
+wire	\rv32.mem_ahb_hwdata[9] ;
+wire	\rv32.mem_ahb_hwrite ;
+wire	\rv32.resetn_out ;
+wire	\rv32.slave_ahb_hrdata[0] ;
+wire	\rv32.slave_ahb_hrdata[10] ;
+wire	\rv32.slave_ahb_hrdata[11] ;
+wire	\rv32.slave_ahb_hrdata[12] ;
+wire	\rv32.slave_ahb_hrdata[13] ;
+wire	\rv32.slave_ahb_hrdata[14] ;
+wire	\rv32.slave_ahb_hrdata[15] ;
+wire	\rv32.slave_ahb_hrdata[16] ;
+wire	\rv32.slave_ahb_hrdata[17] ;
+wire	\rv32.slave_ahb_hrdata[18] ;
+wire	\rv32.slave_ahb_hrdata[19] ;
+wire	\rv32.slave_ahb_hrdata[1] ;
+wire	\rv32.slave_ahb_hrdata[20] ;
+wire	\rv32.slave_ahb_hrdata[21] ;
+wire	\rv32.slave_ahb_hrdata[22] ;
+wire	\rv32.slave_ahb_hrdata[23] ;
+wire	\rv32.slave_ahb_hrdata[24] ;
+wire	\rv32.slave_ahb_hrdata[25] ;
+wire	\rv32.slave_ahb_hrdata[26] ;
+wire	\rv32.slave_ahb_hrdata[27] ;
+wire	\rv32.slave_ahb_hrdata[28] ;
+wire	\rv32.slave_ahb_hrdata[29] ;
+wire	\rv32.slave_ahb_hrdata[2] ;
+wire	\rv32.slave_ahb_hrdata[30] ;
+wire	\rv32.slave_ahb_hrdata[31] ;
+wire	\rv32.slave_ahb_hrdata[3] ;
+wire	\rv32.slave_ahb_hrdata[4] ;
+wire	\rv32.slave_ahb_hrdata[5] ;
+wire	\rv32.slave_ahb_hrdata[6] ;
+wire	\rv32.slave_ahb_hrdata[7] ;
+wire	\rv32.slave_ahb_hrdata[8] ;
+wire	\rv32.slave_ahb_hrdata[9] ;
+wire	\rv32.slave_ahb_hreadyout ;
+wire	\rv32.slave_ahb_hresp ;
+wire	\rv32.swj_JTAGIR[0] ;
+wire	\rv32.swj_JTAGIR[1] ;
+wire	\rv32.swj_JTAGIR[2] ;
+wire	\rv32.swj_JTAGIR[3] ;
+wire	\rv32.swj_JTAGNSW ;
+wire	\rv32.swj_JTAGSTATE[0] ;
+wire	\rv32.swj_JTAGSTATE[1] ;
+wire	\rv32.swj_JTAGSTATE[2] ;
+wire	\rv32.swj_JTAGSTATE[3] ;
+wire	\rv32.sys_ctrl_clkSource[0] ;
+wire	\rv32.sys_ctrl_clkSource[1] ;
+wire	\rv32.sys_ctrl_hseBypass ;
+wire	\rv32.sys_ctrl_hseEnable ;
+wire	\rv32.sys_ctrl_pllEnable ;
+wire	\rv32.sys_ctrl_sleep ;
+wire	\rv32.sys_ctrl_standby ;
+wire	\rv32.sys_ctrl_stop ;
+wire	[31:0] slave_ahb_haddr;
+//wire	slave_ahb_haddr[0];
+//wire	slave_ahb_haddr[10];
+//wire	slave_ahb_haddr[11];
+//wire	slave_ahb_haddr[12];
+//wire	slave_ahb_haddr[13];
+//wire	slave_ahb_haddr[14];
+//wire	slave_ahb_haddr[15];
+//wire	slave_ahb_haddr[16];
+//wire	slave_ahb_haddr[17];
+//wire	slave_ahb_haddr[18];
+//wire	slave_ahb_haddr[19];
+//wire	slave_ahb_haddr[1];
+//wire	slave_ahb_haddr[20];
+//wire	slave_ahb_haddr[21];
+//wire	slave_ahb_haddr[22];
+//wire	slave_ahb_haddr[23];
+//wire	slave_ahb_haddr[24];
+//wire	slave_ahb_haddr[25];
+//wire	slave_ahb_haddr[26];
+//wire	slave_ahb_haddr[27];
+//wire	slave_ahb_haddr[28];
+//wire	slave_ahb_haddr[29];
+//wire	slave_ahb_haddr[2];
+//wire	slave_ahb_haddr[30];
+//wire	slave_ahb_haddr[31];
+//wire	slave_ahb_haddr[3];
+//wire	slave_ahb_haddr[4];
+//wire	slave_ahb_haddr[5];
+//wire	slave_ahb_haddr[6];
+//wire	slave_ahb_haddr[7];
+//wire	slave_ahb_haddr[8];
+//wire	slave_ahb_haddr[9];
+wire	[2:0] slave_ahb_hburst;
+//wire	slave_ahb_hburst[0];
+//wire	slave_ahb_hburst[1];
+//wire	slave_ahb_hburst[2];
+wire	\slave_ahb_hready~combout ;
+wire	\slave_ahb_hsel~combout ;
+wire	[2:0] slave_ahb_hsize;
+//wire	slave_ahb_hsize[0];
+//wire	slave_ahb_hsize[1];
+//wire	slave_ahb_hsize[2];
+wire	[1:0] slave_ahb_htrans;
+//wire	slave_ahb_htrans[0];
+//wire	slave_ahb_htrans[1];
+wire	[31:0] slave_ahb_hwdata;
+//wire	slave_ahb_hwdata[0];
+//wire	slave_ahb_hwdata[10];
+//wire	slave_ahb_hwdata[11];
+//wire	slave_ahb_hwdata[12];
+//wire	slave_ahb_hwdata[13];
+//wire	slave_ahb_hwdata[14];
+//wire	slave_ahb_hwdata[15];
+//wire	slave_ahb_hwdata[16];
+//wire	slave_ahb_hwdata[17];
+//wire	slave_ahb_hwdata[18];
+//wire	slave_ahb_hwdata[19];
+//wire	slave_ahb_hwdata[1];
+//wire	slave_ahb_hwdata[20];
+//wire	slave_ahb_hwdata[21];
+//wire	slave_ahb_hwdata[22];
+//wire	slave_ahb_hwdata[23];
+//wire	slave_ahb_hwdata[24];
+//wire	slave_ahb_hwdata[25];
+//wire	slave_ahb_hwdata[26];
+//wire	slave_ahb_hwdata[27];
+//wire	slave_ahb_hwdata[28];
+//wire	slave_ahb_hwdata[29];
+//wire	slave_ahb_hwdata[2];
+//wire	slave_ahb_hwdata[30];
+//wire	slave_ahb_hwdata[31];
+//wire	slave_ahb_hwdata[3];
+//wire	slave_ahb_hwdata[4];
+//wire	slave_ahb_hwdata[5];
+//wire	slave_ahb_hwdata[6];
+//wire	slave_ahb_hwdata[7];
+//wire	slave_ahb_hwdata[8];
+//wire	slave_ahb_hwdata[9];
+wire	\slave_ahb_hwrite~combout ;
+wire	unknown;
+wire	\~GND~combout ;
+wire	\~VCC~combout ;
+
+wire vcc;
+wire gnd;
+assign vcc = 1'b1;
+assign gnd = 1'b0;
+
+alta_rio \PIN_15~output (
+	.padio(PIN_15),
+	.datain(\rv32.gpio0_io_out_data[4] ),
+	.oe(\rv32.gpio0_io_out_en[4] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_15~input_o ),
+	.regout());
+defparam \PIN_15~output .coord_x = 22;
+defparam \PIN_15~output .coord_y = 3;
+defparam \PIN_15~output .coord_z = 3;
+defparam \PIN_15~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_15~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_15~output .IN_POWERUP = 1'b0;
+defparam \PIN_15~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_15~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_15~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_15~output .OUT_POWERUP = 1'b0;
+defparam \PIN_15~output .OE_REG_MODE = 1'b0;
+defparam \PIN_15~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_15~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_15~output .OE_POWERUP = 1'b0;
+defparam \PIN_15~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_15~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_15~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_15~output .CFG_SLR = 1'b0;
+defparam \PIN_15~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_15~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_15~output .CFG_KEEP = 2'b00;
+defparam \PIN_15~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_15~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_15~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_15~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_15~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_15~output .OUT_DELAY = 1'b0;
+defparam \PIN_15~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_15~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_16~output (
+	.padio(PIN_16),
+	.datain(\rv32.gpio0_io_out_data[5] ),
+	.oe(\rv32.gpio0_io_out_en[5] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_16~input_o ),
+	.regout());
+defparam \PIN_16~output .coord_x = 22;
+defparam \PIN_16~output .coord_y = 3;
+defparam \PIN_16~output .coord_z = 2;
+defparam \PIN_16~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_16~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_16~output .IN_POWERUP = 1'b0;
+defparam \PIN_16~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_16~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_16~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_16~output .OUT_POWERUP = 1'b0;
+defparam \PIN_16~output .OE_REG_MODE = 1'b0;
+defparam \PIN_16~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_16~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_16~output .OE_POWERUP = 1'b0;
+defparam \PIN_16~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_16~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_16~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_16~output .CFG_SLR = 1'b0;
+defparam \PIN_16~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_16~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_16~output .CFG_KEEP = 2'b00;
+defparam \PIN_16~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_16~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_16~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_16~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_16~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_16~output .OUT_DELAY = 1'b0;
+defparam \PIN_16~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_16~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_17~output (
+	.padio(PIN_17),
+	.datain(\rv32.gpio0_io_out_data[6] ),
+	.oe(\rv32.gpio0_io_out_en[6] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_17~input_o ),
+	.regout());
+defparam \PIN_17~output .coord_x = 22;
+defparam \PIN_17~output .coord_y = 3;
+defparam \PIN_17~output .coord_z = 1;
+defparam \PIN_17~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_17~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_17~output .IN_POWERUP = 1'b0;
+defparam \PIN_17~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_17~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_17~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_17~output .OUT_POWERUP = 1'b0;
+defparam \PIN_17~output .OE_REG_MODE = 1'b0;
+defparam \PIN_17~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_17~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_17~output .OE_POWERUP = 1'b0;
+defparam \PIN_17~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_17~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_17~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_17~output .CFG_SLR = 1'b0;
+defparam \PIN_17~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_17~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_17~output .CFG_KEEP = 2'b00;
+defparam \PIN_17~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_17~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_17~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_17~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_17~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_17~output .OUT_DELAY = 1'b0;
+defparam \PIN_17~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_17~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_18~output (
+	.padio(PIN_18),
+	.datain(\rv32.gpio0_io_out_data[7] ),
+	.oe(\rv32.gpio0_io_out_en[7] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_18~input_o ),
+	.regout());
+defparam \PIN_18~output .coord_x = 22;
+defparam \PIN_18~output .coord_y = 3;
+defparam \PIN_18~output .coord_z = 0;
+defparam \PIN_18~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_18~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_18~output .IN_POWERUP = 1'b0;
+defparam \PIN_18~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_18~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_18~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_18~output .OUT_POWERUP = 1'b0;
+defparam \PIN_18~output .OE_REG_MODE = 1'b0;
+defparam \PIN_18~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_18~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_18~output .OE_POWERUP = 1'b0;
+defparam \PIN_18~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_18~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_18~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_18~output .CFG_SLR = 1'b0;
+defparam \PIN_18~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_18~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_18~output .CFG_KEEP = 2'b00;
+defparam \PIN_18~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_18~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_18~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_18~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_18~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_18~output .OUT_DELAY = 1'b0;
+defparam \PIN_18~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_18~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_23~output (
+	.padio(PIN_23),
+	.datain(\rv32.gpio5_io_out_data[0] ),
+	.oe(\rv32.gpio5_io_out_en[0] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_23~input_o ),
+	.regout());
+defparam \PIN_23~output .coord_x = 20;
+defparam \PIN_23~output .coord_y = 13;
+defparam \PIN_23~output .coord_z = 1;
+defparam \PIN_23~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_23~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_23~output .IN_POWERUP = 1'b0;
+defparam \PIN_23~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_23~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_23~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_23~output .OUT_POWERUP = 1'b0;
+defparam \PIN_23~output .OE_REG_MODE = 1'b0;
+defparam \PIN_23~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_23~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_23~output .OE_POWERUP = 1'b0;
+defparam \PIN_23~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_23~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_23~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_23~output .CFG_SLR = 1'b0;
+defparam \PIN_23~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_23~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_23~output .CFG_KEEP = 2'b00;
+defparam \PIN_23~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_23~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_23~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_23~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_23~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_23~output .OUT_DELAY = 1'b0;
+defparam \PIN_23~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_23~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_24~output (
+	.padio(PIN_24),
+	.datain(\rv32.gpio1_io_out_data[2] ),
+	.oe(\rv32.gpio1_io_out_en[2] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_24~input_o ),
+	.regout());
+defparam \PIN_24~output .coord_x = 20;
+defparam \PIN_24~output .coord_y = 13;
+defparam \PIN_24~output .coord_z = 2;
+defparam \PIN_24~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_24~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_24~output .IN_POWERUP = 1'b0;
+defparam \PIN_24~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_24~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_24~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_24~output .OUT_POWERUP = 1'b0;
+defparam \PIN_24~output .OE_REG_MODE = 1'b0;
+defparam \PIN_24~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_24~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_24~output .OE_POWERUP = 1'b0;
+defparam \PIN_24~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_24~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_24~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_24~output .CFG_SLR = 1'b0;
+defparam \PIN_24~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_24~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_24~output .CFG_KEEP = 2'b00;
+defparam \PIN_24~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_24~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_24~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_24~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_24~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_24~output .OUT_DELAY = 1'b0;
+defparam \PIN_24~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_24~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_25~output (
+	.padio(PIN_25),
+	.datain(\rv32.gpio8_io_out_data[2] ),
+	.oe(\rv32.gpio8_io_out_en[2] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout());
+defparam \PIN_25~output .coord_x = 20;
+defparam \PIN_25~output .coord_y = 13;
+defparam \PIN_25~output .coord_z = 3;
+defparam \PIN_25~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_25~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_25~output .IN_POWERUP = 1'b0;
+defparam \PIN_25~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_25~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_25~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_25~output .OUT_POWERUP = 1'b0;
+defparam \PIN_25~output .OE_REG_MODE = 1'b0;
+defparam \PIN_25~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_25~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_25~output .OE_POWERUP = 1'b0;
+defparam \PIN_25~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_25~output .CFG_INPUT_EN = 1'b0;
+defparam \PIN_25~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_25~output .CFG_SLR = 1'b0;
+defparam \PIN_25~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_25~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_25~output .CFG_KEEP = 2'b00;
+defparam \PIN_25~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_25~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_25~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_25~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_25~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_25~output .OUT_DELAY = 1'b0;
+defparam \PIN_25~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_25~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_26~input (
+	.padio(PIN_26),
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_26~input_o ),
+	.regout());
+defparam \PIN_26~input .coord_x = 19;
+defparam \PIN_26~input .coord_y = 13;
+defparam \PIN_26~input .coord_z = 3;
+defparam \PIN_26~input .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_26~input .IN_SYNC_MODE = 1'b0;
+defparam \PIN_26~input .IN_POWERUP = 1'b0;
+defparam \PIN_26~input .OUT_REG_MODE = 1'b0;
+defparam \PIN_26~input .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_26~input .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_26~input .OUT_POWERUP = 1'b0;
+defparam \PIN_26~input .OE_REG_MODE = 1'b0;
+defparam \PIN_26~input .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_26~input .OE_SYNC_MODE = 1'b0;
+defparam \PIN_26~input .OE_POWERUP = 1'b0;
+defparam \PIN_26~input .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_26~input .CFG_INPUT_EN = 1'b1;
+defparam \PIN_26~input .CFG_PULL_UP = 1'b1;
+defparam \PIN_26~input .CFG_SLR = 1'b0;
+defparam \PIN_26~input .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_26~input .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_26~input .CFG_KEEP = 2'b00;
+defparam \PIN_26~input .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_26~input .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_26~input .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_26~input .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_26~input .DPCLK_DELAY = 4'b0000;
+defparam \PIN_26~input .OUT_DELAY = 1'b0;
+defparam \PIN_26~input .IN_DATA_DELAY = 3'b000;
+defparam \PIN_26~input .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_2~output (
+	.padio(PIN_2),
+	.datain(\rv32.gpio1_io_out_data[1] ),
+	.oe(\rv32.gpio1_io_out_en[1] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_2~input_o ),
+	.regout());
+defparam \PIN_2~output .coord_x = 22;
+defparam \PIN_2~output .coord_y = 1;
+defparam \PIN_2~output .coord_z = 3;
+defparam \PIN_2~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_2~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_2~output .IN_POWERUP = 1'b0;
+defparam \PIN_2~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_2~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_2~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_2~output .OUT_POWERUP = 1'b0;
+defparam \PIN_2~output .OE_REG_MODE = 1'b0;
+defparam \PIN_2~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_2~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_2~output .OE_POWERUP = 1'b0;
+defparam \PIN_2~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_2~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_2~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_2~output .CFG_SLR = 1'b0;
+defparam \PIN_2~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_2~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_2~output .CFG_KEEP = 2'b00;
+defparam \PIN_2~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_2~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_2~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_2~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_2~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_2~output .OUT_DELAY = 1'b0;
+defparam \PIN_2~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_2~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_3~output (
+	.padio(PIN_3),
+	.datain(\rv32.gpio1_io_out_data[0] ),
+	.oe(\rv32.gpio1_io_out_en[0] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_3~input_o ),
+	.regout());
+defparam \PIN_3~output .coord_x = 22;
+defparam \PIN_3~output .coord_y = 1;
+defparam \PIN_3~output .coord_z = 2;
+defparam \PIN_3~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_3~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_3~output .IN_POWERUP = 1'b0;
+defparam \PIN_3~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_3~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_3~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_3~output .OUT_POWERUP = 1'b0;
+defparam \PIN_3~output .OE_REG_MODE = 1'b0;
+defparam \PIN_3~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_3~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_3~output .OE_POWERUP = 1'b0;
+defparam \PIN_3~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_3~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_3~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_3~output .CFG_SLR = 1'b0;
+defparam \PIN_3~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_3~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_3~output .CFG_KEEP = 2'b00;
+defparam \PIN_3~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_3~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_3~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_3~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_3~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_3~output .OUT_DELAY = 1'b0;
+defparam \PIN_3~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_3~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_4~output (
+	.padio(PIN_4),
+	.datain(\rv32.gpio1_io_out_data[3] ),
+	.oe(\rv32.gpio1_io_out_en[3] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_4~input_o ),
+	.regout());
+defparam \PIN_4~output .coord_x = 22;
+defparam \PIN_4~output .coord_y = 1;
+defparam \PIN_4~output .coord_z = 0;
+defparam \PIN_4~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_4~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_4~output .IN_POWERUP = 1'b0;
+defparam \PIN_4~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_4~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_4~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_4~output .OUT_POWERUP = 1'b0;
+defparam \PIN_4~output .OE_REG_MODE = 1'b0;
+defparam \PIN_4~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_4~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_4~output .OE_POWERUP = 1'b0;
+defparam \PIN_4~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_4~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_4~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_4~output .CFG_SLR = 1'b0;
+defparam \PIN_4~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_4~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_4~output .CFG_KEEP = 2'b00;
+defparam \PIN_4~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_4~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_4~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_4~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_4~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_4~output .OUT_DELAY = 1'b0;
+defparam \PIN_4~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_4~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_68~output (
+	.padio(PIN_68),
+	.datain(\rv32.gpio7_io_out_data[6] ),
+	.oe(\rv32.gpio7_io_out_en[6] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout());
+defparam \PIN_68~output .coord_x = 0;
+defparam \PIN_68~output .coord_y = 2;
+defparam \PIN_68~output .coord_z = 5;
+defparam \PIN_68~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_68~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_68~output .IN_POWERUP = 1'b0;
+defparam \PIN_68~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_68~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_68~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_68~output .OUT_POWERUP = 1'b0;
+defparam \PIN_68~output .OE_REG_MODE = 1'b0;
+defparam \PIN_68~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_68~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_68~output .OE_POWERUP = 1'b0;
+defparam \PIN_68~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_68~output .CFG_INPUT_EN = 1'b0;
+defparam \PIN_68~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_68~output .CFG_SLR = 1'b0;
+defparam \PIN_68~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_68~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_68~output .CFG_KEEP = 2'b00;
+defparam \PIN_68~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_68~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_68~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_68~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_68~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_68~output .OUT_DELAY = 1'b0;
+defparam \PIN_68~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_68~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_69~input (
+	.padio(PIN_69),
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_69~input_o ),
+	.regout());
+defparam \PIN_69~input .coord_x = 0;
+defparam \PIN_69~input .coord_y = 1;
+defparam \PIN_69~input .coord_z = 0;
+defparam \PIN_69~input .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_69~input .IN_SYNC_MODE = 1'b0;
+defparam \PIN_69~input .IN_POWERUP = 1'b0;
+defparam \PIN_69~input .OUT_REG_MODE = 1'b0;
+defparam \PIN_69~input .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_69~input .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_69~input .OUT_POWERUP = 1'b0;
+defparam \PIN_69~input .OE_REG_MODE = 1'b0;
+defparam \PIN_69~input .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_69~input .OE_SYNC_MODE = 1'b0;
+defparam \PIN_69~input .OE_POWERUP = 1'b0;
+defparam \PIN_69~input .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_69~input .CFG_INPUT_EN = 1'b1;
+defparam \PIN_69~input .CFG_PULL_UP = 1'b0;
+defparam \PIN_69~input .CFG_SLR = 1'b0;
+defparam \PIN_69~input .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_69~input .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_69~input .CFG_KEEP = 2'b00;
+defparam \PIN_69~input .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_69~input .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_69~input .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_69~input .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_69~input .DPCLK_DELAY = 4'b0000;
+defparam \PIN_69~input .OUT_DELAY = 1'b0;
+defparam \PIN_69~input .IN_DATA_DELAY = 3'b000;
+defparam \PIN_69~input .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_7~output (
+	.padio(PIN_7),
+	.datain(\rv32.gpio5_io_out_data[3] ),
+	.oe(\rv32.gpio5_io_out_en[3] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_7~input_o ),
+	.regout());
+defparam \PIN_7~output .coord_x = 22;
+defparam \PIN_7~output .coord_y = 2;
+defparam \PIN_7~output .coord_z = 3;
+defparam \PIN_7~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_7~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_7~output .IN_POWERUP = 1'b0;
+defparam \PIN_7~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_7~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_7~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_7~output .OUT_POWERUP = 1'b0;
+defparam \PIN_7~output .OE_REG_MODE = 1'b0;
+defparam \PIN_7~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_7~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_7~output .OE_POWERUP = 1'b0;
+defparam \PIN_7~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_7~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_7~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_7~output .CFG_SLR = 1'b0;
+defparam \PIN_7~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_7~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_7~output .CFG_KEEP = 2'b00;
+defparam \PIN_7~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_7~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_7~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_7~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_7~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_7~output .OUT_DELAY = 1'b0;
+defparam \PIN_7~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_7~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_80~output (
+	.padio(PIN_80),
+	.datain(\rv32.gpio8_io_out_data[0] ),
+	.oe(\rv32.gpio8_io_out_en[0] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(),
+	.regout());
+defparam \PIN_80~output .coord_x = 6;
+defparam \PIN_80~output .coord_y = 0;
+defparam \PIN_80~output .coord_z = 0;
+defparam \PIN_80~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_80~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_80~output .IN_POWERUP = 1'b0;
+defparam \PIN_80~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_80~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_80~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_80~output .OUT_POWERUP = 1'b0;
+defparam \PIN_80~output .OE_REG_MODE = 1'b0;
+defparam \PIN_80~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_80~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_80~output .OE_POWERUP = 1'b0;
+defparam \PIN_80~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_80~output .CFG_INPUT_EN = 1'b0;
+defparam \PIN_80~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_80~output .CFG_SLR = 1'b0;
+defparam \PIN_80~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_80~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_80~output .CFG_KEEP = 2'b00;
+defparam \PIN_80~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_80~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_80~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_80~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_80~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_80~output .OUT_DELAY = 1'b0;
+defparam \PIN_80~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_80~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_83~input (
+	.padio(PIN_83),
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_83~input_o ),
+	.regout());
+defparam \PIN_83~input .coord_x = 7;
+defparam \PIN_83~input .coord_y = 0;
+defparam \PIN_83~input .coord_z = 1;
+defparam \PIN_83~input .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_83~input .IN_SYNC_MODE = 1'b0;
+defparam \PIN_83~input .IN_POWERUP = 1'b0;
+defparam \PIN_83~input .OUT_REG_MODE = 1'b0;
+defparam \PIN_83~input .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_83~input .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_83~input .OUT_POWERUP = 1'b0;
+defparam \PIN_83~input .OE_REG_MODE = 1'b0;
+defparam \PIN_83~input .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_83~input .OE_SYNC_MODE = 1'b0;
+defparam \PIN_83~input .OE_POWERUP = 1'b0;
+defparam \PIN_83~input .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_83~input .CFG_INPUT_EN = 1'b1;
+defparam \PIN_83~input .CFG_PULL_UP = 1'b0;
+defparam \PIN_83~input .CFG_SLR = 1'b0;
+defparam \PIN_83~input .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_83~input .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_83~input .CFG_KEEP = 2'b00;
+defparam \PIN_83~input .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_83~input .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_83~input .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_83~input .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_83~input .DPCLK_DELAY = 4'b0000;
+defparam \PIN_83~input .OUT_DELAY = 1'b0;
+defparam \PIN_83~input .IN_DATA_DELAY = 3'b000;
+defparam \PIN_83~input .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_88~output (
+	.padio(PIN_88),
+	.datain(\rv32.gpio1_io_out_data[6] ),
+	.oe(\rv32.gpio1_io_out_en[6] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_88~input_o ),
+	.regout());
+defparam \PIN_88~output .coord_x = 8;
+defparam \PIN_88~output .coord_y = 0;
+defparam \PIN_88~output .coord_z = 3;
+defparam \PIN_88~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_88~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_88~output .IN_POWERUP = 1'b0;
+defparam \PIN_88~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_88~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_88~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_88~output .OUT_POWERUP = 1'b0;
+defparam \PIN_88~output .OE_REG_MODE = 1'b0;
+defparam \PIN_88~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_88~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_88~output .OE_POWERUP = 1'b0;
+defparam \PIN_88~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_88~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_88~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_88~output .CFG_SLR = 1'b0;
+defparam \PIN_88~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_88~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_88~output .CFG_KEEP = 2'b00;
+defparam \PIN_88~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_88~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_88~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_88~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_88~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_88~output .OUT_DELAY = 1'b0;
+defparam \PIN_88~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_88~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_91~output (
+	.padio(PIN_91),
+	.datain(\rv32.gpio1_io_out_data[5] ),
+	.oe(\rv32.gpio1_io_out_en[5] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_91~input_o ),
+	.regout());
+defparam \PIN_91~output .coord_x = 17;
+defparam \PIN_91~output .coord_y = 0;
+defparam \PIN_91~output .coord_z = 2;
+defparam \PIN_91~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_91~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_91~output .IN_POWERUP = 1'b0;
+defparam \PIN_91~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_91~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_91~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_91~output .OUT_POWERUP = 1'b0;
+defparam \PIN_91~output .OE_REG_MODE = 1'b0;
+defparam \PIN_91~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_91~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_91~output .OE_POWERUP = 1'b0;
+defparam \PIN_91~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_91~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_91~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_91~output .CFG_SLR = 1'b0;
+defparam \PIN_91~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_91~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_91~output .CFG_KEEP = 2'b00;
+defparam \PIN_91~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_91~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_91~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_91~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_91~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_91~output .OUT_DELAY = 1'b0;
+defparam \PIN_91~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_91~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_92~output (
+	.padio(PIN_92),
+	.datain(\rv32.gpio1_io_out_data[4] ),
+	.oe(\rv32.gpio1_io_out_en[4] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_92~input_o ),
+	.regout());
+defparam \PIN_92~output .coord_x = 18;
+defparam \PIN_92~output .coord_y = 0;
+defparam \PIN_92~output .coord_z = 0;
+defparam \PIN_92~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_92~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_92~output .IN_POWERUP = 1'b0;
+defparam \PIN_92~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_92~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_92~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_92~output .OUT_POWERUP = 1'b0;
+defparam \PIN_92~output .OE_REG_MODE = 1'b0;
+defparam \PIN_92~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_92~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_92~output .OE_POWERUP = 1'b0;
+defparam \PIN_92~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_92~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_92~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_92~output .CFG_SLR = 1'b0;
+defparam \PIN_92~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_92~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_92~output .CFG_KEEP = 2'b00;
+defparam \PIN_92~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_92~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_92~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_92~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_92~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_92~output .OUT_DELAY = 1'b0;
+defparam \PIN_92~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_92~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_93~output (
+	.padio(PIN_93),
+	.datain(\rv32.gpio5_io_out_data[1] ),
+	.oe(\rv32.gpio5_io_out_en[1] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_93~input_o ),
+	.regout());
+defparam \PIN_93~output .coord_x = 18;
+defparam \PIN_93~output .coord_y = 0;
+defparam \PIN_93~output .coord_z = 1;
+defparam \PIN_93~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_93~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_93~output .IN_POWERUP = 1'b0;
+defparam \PIN_93~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_93~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_93~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_93~output .OUT_POWERUP = 1'b0;
+defparam \PIN_93~output .OE_REG_MODE = 1'b0;
+defparam \PIN_93~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_93~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_93~output .OE_POWERUP = 1'b0;
+defparam \PIN_93~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_93~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_93~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_93~output .CFG_SLR = 1'b0;
+defparam \PIN_93~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_93~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_93~output .CFG_KEEP = 2'b00;
+defparam \PIN_93~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_93~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_93~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_93~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_93~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_93~output .OUT_DELAY = 1'b0;
+defparam \PIN_93~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_93~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_95~output (
+	.padio(PIN_95),
+	.datain(\rv32.gpio2_io_out_data[1] ),
+	.oe(\rv32.gpio2_io_out_en[1] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_95~input_o ),
+	.regout());
+defparam \PIN_95~output .coord_x = 19;
+defparam \PIN_95~output .coord_y = 0;
+defparam \PIN_95~output .coord_z = 1;
+defparam \PIN_95~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_95~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_95~output .IN_POWERUP = 1'b0;
+defparam \PIN_95~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_95~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_95~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_95~output .OUT_POWERUP = 1'b0;
+defparam \PIN_95~output .OE_REG_MODE = 1'b0;
+defparam \PIN_95~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_95~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_95~output .OE_POWERUP = 1'b0;
+defparam \PIN_95~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_95~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_95~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_95~output .CFG_SLR = 1'b0;
+defparam \PIN_95~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_95~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_95~output .CFG_KEEP = 2'b00;
+defparam \PIN_95~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_95~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_95~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_95~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_95~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_95~output .OUT_DELAY = 1'b0;
+defparam \PIN_95~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_95~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_96~output (
+	.padio(PIN_96),
+	.datain(\rv32.gpio2_io_out_data[2] ),
+	.oe(\rv32.gpio2_io_out_en[2] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_96~input_o ),
+	.regout());
+defparam \PIN_96~output .coord_x = 19;
+defparam \PIN_96~output .coord_y = 0;
+defparam \PIN_96~output .coord_z = 3;
+defparam \PIN_96~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_96~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_96~output .IN_POWERUP = 1'b0;
+defparam \PIN_96~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_96~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_96~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_96~output .OUT_POWERUP = 1'b0;
+defparam \PIN_96~output .OE_REG_MODE = 1'b0;
+defparam \PIN_96~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_96~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_96~output .OE_POWERUP = 1'b0;
+defparam \PIN_96~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_96~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_96~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_96~output .CFG_SLR = 1'b0;
+defparam \PIN_96~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_96~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_96~output .CFG_KEEP = 2'b00;
+defparam \PIN_96~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_96~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_96~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_96~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_96~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_96~output .OUT_DELAY = 1'b0;
+defparam \PIN_96~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_96~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_97~output (
+	.padio(PIN_97),
+	.datain(\rv32.gpio2_io_out_data[0] ),
+	.oe(\rv32.gpio2_io_out_en[0] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_97~input_o ),
+	.regout());
+defparam \PIN_97~output .coord_x = 20;
+defparam \PIN_97~output .coord_y = 0;
+defparam \PIN_97~output .coord_z = 0;
+defparam \PIN_97~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_97~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_97~output .IN_POWERUP = 1'b0;
+defparam \PIN_97~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_97~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_97~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_97~output .OUT_POWERUP = 1'b0;
+defparam \PIN_97~output .OE_REG_MODE = 1'b0;
+defparam \PIN_97~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_97~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_97~output .OE_POWERUP = 1'b0;
+defparam \PIN_97~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_97~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_97~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_97~output .CFG_SLR = 1'b0;
+defparam \PIN_97~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_97~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_97~output .CFG_KEEP = 2'b00;
+defparam \PIN_97~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_97~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_97~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_97~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_97~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_97~output .OUT_DELAY = 1'b0;
+defparam \PIN_97~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_97~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_98~output (
+	.padio(PIN_98),
+	.datain(\rv32.gpio5_io_out_data[2] ),
+	.oe(\rv32.gpio5_io_out_en[2] ),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_98~input_o ),
+	.regout());
+defparam \PIN_98~output .coord_x = 20;
+defparam \PIN_98~output .coord_y = 0;
+defparam \PIN_98~output .coord_z = 2;
+defparam \PIN_98~output .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_98~output .IN_SYNC_MODE = 1'b0;
+defparam \PIN_98~output .IN_POWERUP = 1'b0;
+defparam \PIN_98~output .OUT_REG_MODE = 1'b0;
+defparam \PIN_98~output .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_98~output .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_98~output .OUT_POWERUP = 1'b0;
+defparam \PIN_98~output .OE_REG_MODE = 1'b0;
+defparam \PIN_98~output .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_98~output .OE_SYNC_MODE = 1'b0;
+defparam \PIN_98~output .OE_POWERUP = 1'b0;
+defparam \PIN_98~output .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_98~output .CFG_INPUT_EN = 1'b1;
+defparam \PIN_98~output .CFG_PULL_UP = 1'b0;
+defparam \PIN_98~output .CFG_SLR = 1'b0;
+defparam \PIN_98~output .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_98~output .CFG_PDRCTRL = 4'b0100;
+defparam \PIN_98~output .CFG_KEEP = 2'b00;
+defparam \PIN_98~output .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_98~output .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_98~output .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_98~output .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_98~output .DPCLK_DELAY = 4'b0000;
+defparam \PIN_98~output .OUT_DELAY = 1'b0;
+defparam \PIN_98~output .IN_DATA_DELAY = 3'b000;
+defparam \PIN_98~output .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_HSE~input (
+	.padio(PIN_HSE),
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_HSE~input_o ),
+	.regout());
+defparam \PIN_HSE~input .coord_x = 22;
+defparam \PIN_HSE~input .coord_y = 4;
+defparam \PIN_HSE~input .coord_z = 1;
+defparam \PIN_HSE~input .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_HSE~input .IN_SYNC_MODE = 1'b0;
+defparam \PIN_HSE~input .IN_POWERUP = 1'b0;
+defparam \PIN_HSE~input .OUT_REG_MODE = 1'b0;
+defparam \PIN_HSE~input .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_HSE~input .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_HSE~input .OUT_POWERUP = 1'b0;
+defparam \PIN_HSE~input .OE_REG_MODE = 1'b0;
+defparam \PIN_HSE~input .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_HSE~input .OE_SYNC_MODE = 1'b0;
+defparam \PIN_HSE~input .OE_POWERUP = 1'b0;
+defparam \PIN_HSE~input .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_HSE~input .CFG_PULL_UP = 1'b0;
+defparam \PIN_HSE~input .CFG_SLR = 1'b0;
+defparam \PIN_HSE~input .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_HSE~input .CFG_PDRCTRL = 4'b0010;
+defparam \PIN_HSE~input .CFG_KEEP = 2'b00;
+defparam \PIN_HSE~input .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_HSE~input .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_HSE~input .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_HSE~input .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_HSE~input .DPCLK_DELAY = 4'b0000;
+defparam \PIN_HSE~input .OUT_DELAY = 1'b0;
+defparam \PIN_HSE~input .IN_DATA_DELAY = 3'b000;
+defparam \PIN_HSE~input .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_HSI~input (
+	.padio(PIN_HSI),
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_HSI~input_o ),
+	.regout());
+defparam \PIN_HSI~input .coord_x = 22;
+defparam \PIN_HSI~input .coord_y = 4;
+defparam \PIN_HSI~input .coord_z = 0;
+defparam \PIN_HSI~input .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_HSI~input .IN_SYNC_MODE = 1'b0;
+defparam \PIN_HSI~input .IN_POWERUP = 1'b0;
+defparam \PIN_HSI~input .OUT_REG_MODE = 1'b0;
+defparam \PIN_HSI~input .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_HSI~input .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_HSI~input .OUT_POWERUP = 1'b0;
+defparam \PIN_HSI~input .OE_REG_MODE = 1'b0;
+defparam \PIN_HSI~input .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_HSI~input .OE_SYNC_MODE = 1'b0;
+defparam \PIN_HSI~input .OE_POWERUP = 1'b0;
+defparam \PIN_HSI~input .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_HSI~input .CFG_PULL_UP = 1'b0;
+defparam \PIN_HSI~input .CFG_SLR = 1'b0;
+defparam \PIN_HSI~input .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_HSI~input .CFG_PDRCTRL = 4'b0010;
+defparam \PIN_HSI~input .CFG_KEEP = 2'b00;
+defparam \PIN_HSI~input .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_HSI~input .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_HSI~input .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_HSI~input .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_HSI~input .DPCLK_DELAY = 4'b0000;
+defparam \PIN_HSI~input .OUT_DELAY = 1'b0;
+defparam \PIN_HSI~input .IN_DATA_DELAY = 3'b000;
+defparam \PIN_HSI~input .IN_REG_DELAY = 3'b000;
+
+alta_rio \PIN_OSC~input (
+	.padio(PIN_OSC),
+	.datain(gnd),
+	.oe(gnd),
+	.outclk(gnd),
+	.outclkena(vcc),
+	.inclk(gnd),
+	.inclkena(vcc),
+	.areset(gnd),
+	.sreset(gnd),
+	.combout(\PIN_OSC~input_o ),
+	.regout());
+defparam \PIN_OSC~input .coord_x = 22;
+defparam \PIN_OSC~input .coord_y = 4;
+defparam \PIN_OSC~input .coord_z = 2;
+defparam \PIN_OSC~input .IN_ASYNC_MODE = 1'b0;
+defparam \PIN_OSC~input .IN_SYNC_MODE = 1'b0;
+defparam \PIN_OSC~input .IN_POWERUP = 1'b0;
+defparam \PIN_OSC~input .OUT_REG_MODE = 1'b0;
+defparam \PIN_OSC~input .OUT_ASYNC_MODE = 1'b0;
+defparam \PIN_OSC~input .OUT_SYNC_MODE = 1'b0;
+defparam \PIN_OSC~input .OUT_POWERUP = 1'b0;
+defparam \PIN_OSC~input .OE_REG_MODE = 1'b0;
+defparam \PIN_OSC~input .OE_ASYNC_MODE = 1'b0;
+defparam \PIN_OSC~input .OE_SYNC_MODE = 1'b0;
+defparam \PIN_OSC~input .OE_POWERUP = 1'b0;
+defparam \PIN_OSC~input .CFG_TRI_INPUT = 1'b0;
+defparam \PIN_OSC~input .CFG_PULL_UP = 1'b0;
+defparam \PIN_OSC~input .CFG_SLR = 1'b0;
+defparam \PIN_OSC~input .CFG_OPEN_DRAIN = 1'b0;
+defparam \PIN_OSC~input .CFG_PDRCTRL = 4'b0010;
+defparam \PIN_OSC~input .CFG_KEEP = 2'b00;
+defparam \PIN_OSC~input .CFG_LVDS_OUT_EN = 1'b0;
+defparam \PIN_OSC~input .CFG_LVDS_SEL_CUA = 2'b00;
+defparam \PIN_OSC~input .CFG_LVDS_IREF = 10'b0110000000;
+defparam \PIN_OSC~input .CFG_LVDS_IN_EN = 1'b0;
+defparam \PIN_OSC~input .DPCLK_DELAY = 4'b0000;
+defparam \PIN_OSC~input .OUT_DELAY = 1'b0;
+defparam \PIN_OSC~input .IN_DATA_DELAY = 3'b000;
+defparam \PIN_OSC~input .IN_REG_DELAY = 3'b000;
+
+alta_slice PLL_ENABLE(
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(\rv32.sys_ctrl_pllEnable ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\PLL_ENABLE~combout ),
+	.Cout(),
+	.Q());
+defparam PLL_ENABLE.coord_x = 17;
+defparam PLL_ENABLE.coord_y = 5;
+defparam PLL_ENABLE.coord_z = 14;
+defparam PLL_ENABLE.mask = 16'h00FF;
+defparam PLL_ENABLE.modeMux = 1'b0;
+defparam PLL_ENABLE.FeedbackMux = 1'b0;
+defparam PLL_ENABLE.ShiftMux = 1'b0;
+defparam PLL_ENABLE.BypassEn = 1'b0;
+defparam PLL_ENABLE.CarryEnb = 1'b1;
+
+alta_io_gclk \PLL_ENABLE~clkctrl (
+	.inclk(\PLL_ENABLE~combout ),
+	.outclk(\PLL_ENABLE~clkctrl_outclk ));
+defparam \PLL_ENABLE~clkctrl .coord_x = 22;
+defparam \PLL_ENABLE~clkctrl .coord_y = 4;
+defparam \PLL_ENABLE~clkctrl .coord_z = 4;
+
+alta_slice PLL_LOCK(
+	.A(vcc),
+	.B(\pll_inst|auto_generated|pll_lock_sync~q ),
+	.C(vcc),
+	.D(\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp ),
+	.Cin(),
+	.Qin(),
+	.Clk(),
+	.AsyncReset(),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\PLL_LOCK~combout ),
+	.Cout(),
+	.Q());
+defparam PLL_LOCK.coord_x = 20;
+defparam PLL_LOCK.coord_y = 5;
+defparam PLL_LOCK.coord_z = 14;
+defparam PLL_LOCK.mask = 16'hCC00;
+defparam PLL_LOCK.modeMux = 1'b0;
+defparam PLL_LOCK.FeedbackMux = 1'b0;
+defparam PLL_LOCK.ShiftMux = 1'b0;
+defparam PLL_LOCK.BypassEn = 1'b0;
+defparam PLL_LOCK.CarryEnb = 1'b1;
+
+alta_asyncctrl asyncreset_ctrl_X50_Y1_N0(
+	.Din(\PLL_ENABLE~clkctrl_outclk ),
+	.Dout(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X50_Y1_SIG ));
+defparam asyncreset_ctrl_X50_Y1_N0.coord_x = 20;
+defparam asyncreset_ctrl_X50_Y1_N0.coord_y = 5;
+defparam asyncreset_ctrl_X50_Y1_N0.coord_z = 0;
+defparam asyncreset_ctrl_X50_Y1_N0.AsyncCtrlMux = 2'b10;
+
+alta_clkenctrl clken_ctrl_X50_Y1_N0(
+	.ClkIn(\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp ),
+	.ClkEn(),
+	.ClkOut(\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp_X50_Y1_SIG_VCC ));
+defparam clken_ctrl_X50_Y1_N0.coord_x = 20;
+defparam clken_ctrl_X50_Y1_N0.coord_y = 5;
+defparam clken_ctrl_X50_Y1_N0.coord_z = 0;
+defparam clken_ctrl_X50_Y1_N0.ClkMux = 2'b10;
+defparam clken_ctrl_X50_Y1_N0.ClkEnMux = 2'b01;
+
+alta_io_gclk \gclksw_inst|gclk_switch (
+	.inclk(\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
+	.outclk(\auto_generated_inst.hbo_22_f9ff3d300b43c0f2_bp ));
+defparam \gclksw_inst|gclk_switch .coord_x = 22;
+defparam \gclksw_inst|gclk_switch .coord_y = 4;
+defparam \gclksw_inst|gclk_switch .coord_z = 5;
+
+alta_gclksw \gclksw_inst|gclk_switch__alta_gclksw (
+	.resetn(\rv32.resetn_out ),
+	.clkin0(\PIN_HSI~input_o ),
+	.clkin1(\PIN_HSE~input_o ),
+	.clkin2(\pll_inst|auto_generated|pll1_CLK_bus [0]),
+	.clkin3(vcc),
+	.select({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
+	.clkout(\gclksw_inst|gclk_switch__alta_gclksw__clkout ));
+defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_x = 22;
+defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_y = 4;
+defparam \gclksw_inst|gclk_switch__alta_gclksw .coord_z = 0;
+
+alta_pllve \pll_inst|auto_generated|pll1 (
+	.clkin(\PIN_HSE~input_o ),
+	.clkfb(\pll_inst|auto_generated|pll1~FBOUT ),
+	.pfden(vcc),
+	.resetn(!\PLL_ENABLE~combout ),
+	.phasecounterselect({gnd, gnd, gnd}),
+	.phaseupdown(gnd),
+	.phasestep(gnd),
+	.scanclk(gnd),
+	.scanclkena(vcc),
+	.scandata(gnd),
+	.configupdate(gnd),
+	.scandataout(),
+	.scandone(),
+	.phasedone(),
+	.clkout0(\pll_inst|auto_generated|pll1_CLK_bus [0]),
+	.clkout1(\pll_inst|auto_generated|pll1_CLK_bus [1]),
+	.clkout2(\pll_inst|auto_generated|pll1_CLK_bus [2]),
+	.clkout3(\pll_inst|auto_generated|pll1_CLK_bus [3]),
+	.clkout4(\pll_inst|auto_generated|pll1_CLK_bus [4]),
+	.clkfbout(\pll_inst|auto_generated|pll1~FBOUT ),
+	.lock(\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp ));
+defparam \pll_inst|auto_generated|pll1 .coord_x = 22;
+defparam \pll_inst|auto_generated|pll1 .coord_y = 5;
+defparam \pll_inst|auto_generated|pll1 .coord_z = 0;
+defparam \pll_inst|auto_generated|pll1 .CLKIN_HIGH = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKIN_LOW = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKIN_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKIN_BYPASS = 1'b1;
+defparam \pll_inst|auto_generated|pll1 .CLKFB_HIGH = 8'b00011101;
+defparam \pll_inst|auto_generated|pll1 .CLKFB_LOW = 8'b00011101;
+defparam \pll_inst|auto_generated|pll1 .CLKFB_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKFB_BYPASS = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKDIV0_EN = 1'b1;
+defparam \pll_inst|auto_generated|pll1 .CLKDIV1_EN = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKDIV2_EN = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKDIV3_EN = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKDIV4_EN = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT0_HIGH = 8'b00000001;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT0_LOW = 8'b00000001;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT0_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT0_BYPASS = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_HIGH = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_LOW = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_BYPASS = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_HIGH = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_LOW = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_BYPASS = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_HIGH = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_LOW = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_BYPASS = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_HIGH = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_LOW = 8'b11111111;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_TRIM = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_BYPASS = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT0_DEL = 8'b00000000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_DEL = 8'b00000000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_DEL = 8'b00000000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_DEL = 8'b00000000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_DEL = 8'b00000000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT0_PHASE = 3'b000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_PHASE = 3'b000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_PHASE = 3'b000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_PHASE = 3'b000;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_PHASE = 3'b000;
+defparam \pll_inst|auto_generated|pll1 .CLKFB_DEL = 8'b00000000;
+defparam \pll_inst|auto_generated|pll1 .CLKFB_PHASE = 3'b000;
+defparam \pll_inst|auto_generated|pll1 .FEEDBACK_MODE = 3'b100;
+defparam \pll_inst|auto_generated|pll1 .FBDELAY_VAL = 3'b100;
+defparam \pll_inst|auto_generated|pll1 .PLLOUTP_EN = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .PLLOUTN_EN = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT1_CASCADE = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT2_CASCADE = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT3_CASCADE = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .CLKOUT4_CASCADE = 1'b0;
+defparam \pll_inst|auto_generated|pll1 .VCO_POST_DIV = 1'b1;
+defparam \pll_inst|auto_generated|pll1 .REG_CTRL = 2'b00;
+defparam \pll_inst|auto_generated|pll1 .CP = 3'b100;
+defparam \pll_inst|auto_generated|pll1 .RREF = 2'b01;
+defparam \pll_inst|auto_generated|pll1 .RVI = 2'b01;
+defparam \pll_inst|auto_generated|pll1 .IVCO = 3'b010;
+defparam \pll_inst|auto_generated|pll1 .PLL_EN_FLAG = 1'b1;
+
+alta_slice \pll_inst|auto_generated|pll_lock_sync (
+	.A(vcc),
+	.B(vcc),
+	.C(vcc),
+	.D(vcc),
+	.Cin(),
+	.Qin(\pll_inst|auto_generated|pll_lock_sync~q ),
+	.Clk(\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp_X50_Y1_SIG_VCC ),
+	.AsyncReset(\PLL_ENABLE~clkctrl_outclk__AsyncReset_X50_Y1_SIG ),
+	.SyncReset(),
+	.ShiftData(),
+	.SyncLoad(),
+	.LutOut(\pll_inst|auto_generated|pll_lock_sync~feeder_combout ),
+	.Cout(),
+	.Q(\pll_inst|auto_generated|pll_lock_sync~q ));
+defparam \pll_inst|auto_generated|pll_lock_sync .coord_x = 20;
+defparam \pll_inst|auto_generated|pll_lock_sync .coord_y = 5;
+defparam \pll_inst|auto_generated|pll_lock_sync .coord_z = 9;
+defparam \pll_inst|auto_generated|pll_lock_sync .mask = 16'hFFFF;
+defparam \pll_inst|auto_generated|pll_lock_sync .modeMux = 1'b0;
+defparam \pll_inst|auto_generated|pll_lock_sync .FeedbackMux = 1'b0;
+defparam \pll_inst|auto_generated|pll_lock_sync .ShiftMux = 1'b0;
+defparam \pll_inst|auto_generated|pll_lock_sync .BypassEn = 1'b0;
+defparam \pll_inst|auto_generated|pll_lock_sync .CarryEnb = 1'b1;
+
+alta_rv32 rv32(
+	.sys_clk(\gclksw_inst|gclk_switch__alta_gclksw__clkout ),
+	.mem_ahb_hready(\rv32.mem_ahb_hready ),
+	.mem_ahb_hreadyout(vcc),
+	.mem_ahb_htrans({\rv32.mem_ahb_htrans[1] , \rv32.mem_ahb_htrans[0] }),
+	.mem_ahb_hsize({\rv32.mem_ahb_hsize[2] , \rv32.mem_ahb_hsize[1] , \rv32.mem_ahb_hsize[0] }),
+	.mem_ahb_hburst({\rv32.mem_ahb_hburst[2] , \rv32.mem_ahb_hburst[1] , \rv32.mem_ahb_hburst[0] }),
+	.mem_ahb_hwrite(\rv32.mem_ahb_hwrite ),
+	.mem_ahb_haddr({\rv32.mem_ahb_haddr[31] , \rv32.mem_ahb_haddr[30] , \rv32.mem_ahb_haddr[29] , \rv32.mem_ahb_haddr[28] , \rv32.mem_ahb_haddr[27] , \rv32.mem_ahb_haddr[26] , \rv32.mem_ahb_haddr[25] , \rv32.mem_ahb_haddr[24] , \rv32.mem_ahb_haddr[23] , \rv32.mem_ahb_haddr[22] , \rv32.mem_ahb_haddr[21] , \rv32.mem_ahb_haddr[20] , \rv32.mem_ahb_haddr[19] , \rv32.mem_ahb_haddr[18] , \rv32.mem_ahb_haddr[17] , \rv32.mem_ahb_haddr[16] , \rv32.mem_ahb_haddr[15] , \rv32.mem_ahb_haddr[14] , \rv32.mem_ahb_haddr[13] , \rv32.mem_ahb_haddr[12] , \rv32.mem_ahb_haddr[11] , \rv32.mem_ahb_haddr[10] , \rv32.mem_ahb_haddr[9] , \rv32.mem_ahb_haddr[8] , \rv32.mem_ahb_haddr[7] , \rv32.mem_ahb_haddr[6] , \rv32.mem_ahb_haddr[5] , \rv32.mem_ahb_haddr[4] , \rv32.mem_ahb_haddr[3] , \rv32.mem_ahb_haddr[2] , \rv32.mem_ahb_haddr[1] , \rv32.mem_ahb_haddr[0] }),
+	.mem_ahb_hwdata({\rv32.mem_ahb_hwdata[31] , \rv32.mem_ahb_hwdata[30] , \rv32.mem_ahb_hwdata[29] , \rv32.mem_ahb_hwdata[28] , \rv32.mem_ahb_hwdata[27] , \rv32.mem_ahb_hwdata[26] , \rv32.mem_ahb_hwdata[25] , \rv32.mem_ahb_hwdata[24] , \rv32.mem_ahb_hwdata[23] , \rv32.mem_ahb_hwdata[22] , \rv32.mem_ahb_hwdata[21] , \rv32.mem_ahb_hwdata[20] , \rv32.mem_ahb_hwdata[19] , \rv32.mem_ahb_hwdata[18] , \rv32.mem_ahb_hwdata[17] , \rv32.mem_ahb_hwdata[16] , \rv32.mem_ahb_hwdata[15] , \rv32.mem_ahb_hwdata[14] , \rv32.mem_ahb_hwdata[13] , \rv32.mem_ahb_hwdata[12] , \rv32.mem_ahb_hwdata[11] , \rv32.mem_ahb_hwdata[10] , \rv32.mem_ahb_hwdata[9] , \rv32.mem_ahb_hwdata[8] , \rv32.mem_ahb_hwdata[7] , \rv32.mem_ahb_hwdata[6] , \rv32.mem_ahb_hwdata[5] , \rv32.mem_ahb_hwdata[4] , \rv32.mem_ahb_hwdata[3] , \rv32.mem_ahb_hwdata[2] , \rv32.mem_ahb_hwdata[1] , \rv32.mem_ahb_hwdata[0] }),
+	.mem_ahb_hresp(gnd),
+	.mem_ahb_hrdata({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.slave_ahb_hsel(gnd),
+	.slave_ahb_hready(vcc),
+	.slave_ahb_hreadyout(\rv32.slave_ahb_hreadyout ),
+	.slave_ahb_htrans({gnd, gnd}),
+	.slave_ahb_hsize({gnd, gnd, gnd}),
+	.slave_ahb_hburst({gnd, gnd, gnd}),
+	.slave_ahb_hwrite(gnd),
+	.slave_ahb_haddr({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.slave_ahb_hwdata({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.slave_ahb_hresp(\rv32.slave_ahb_hresp ),
+	.slave_ahb_hrdata({\rv32.slave_ahb_hrdata[31] , \rv32.slave_ahb_hrdata[30] , \rv32.slave_ahb_hrdata[29] , \rv32.slave_ahb_hrdata[28] , \rv32.slave_ahb_hrdata[27] , \rv32.slave_ahb_hrdata[26] , \rv32.slave_ahb_hrdata[25] , \rv32.slave_ahb_hrdata[24] , \rv32.slave_ahb_hrdata[23] , \rv32.slave_ahb_hrdata[22] , \rv32.slave_ahb_hrdata[21] , \rv32.slave_ahb_hrdata[20] , \rv32.slave_ahb_hrdata[19] , \rv32.slave_ahb_hrdata[18] , \rv32.slave_ahb_hrdata[17] , \rv32.slave_ahb_hrdata[16] , \rv32.slave_ahb_hrdata[15] , \rv32.slave_ahb_hrdata[14] , \rv32.slave_ahb_hrdata[13] , \rv32.slave_ahb_hrdata[12] , \rv32.slave_ahb_hrdata[11] , \rv32.slave_ahb_hrdata[10] , \rv32.slave_ahb_hrdata[9] , \rv32.slave_ahb_hrdata[8] , \rv32.slave_ahb_hrdata[7] , \rv32.slave_ahb_hrdata[6] , \rv32.slave_ahb_hrdata[5] , \rv32.slave_ahb_hrdata[4] , \rv32.slave_ahb_hrdata[3] , \rv32.slave_ahb_hrdata[2] , \rv32.slave_ahb_hrdata[1] , \rv32.slave_ahb_hrdata[0] }),
+	.gpio0_io_in({\PIN_18~input_o , \PIN_17~input_o , \PIN_16~input_o , \PIN_15~input_o , gnd, gnd, gnd, gnd}),
+	.gpio0_io_out_data({\rv32.gpio0_io_out_data[7] , \rv32.gpio0_io_out_data[6] , \rv32.gpio0_io_out_data[5] , \rv32.gpio0_io_out_data[4] , \rv32.gpio0_io_out_data[3] , \rv32.gpio0_io_out_data[2] , \rv32.gpio0_io_out_data[1] , \rv32.gpio0_io_out_data[0] }),
+	.gpio0_io_out_en({\rv32.gpio0_io_out_en[7] , \rv32.gpio0_io_out_en[6] , \rv32.gpio0_io_out_en[5] , \rv32.gpio0_io_out_en[4] , \rv32.gpio0_io_out_en[3] , \rv32.gpio0_io_out_en[2] , \rv32.gpio0_io_out_en[1] , \rv32.gpio0_io_out_en[0] }),
+	.gpio1_io_in({gnd, \PIN_88~input_o , \PIN_91~input_o , \PIN_92~input_o , \PIN_4~input_o , \PIN_24~input_o , \PIN_2~input_o , \PIN_3~input_o }),
+	.gpio1_io_out_data({\rv32.gpio1_io_out_data[7] , \rv32.gpio1_io_out_data[6] , \rv32.gpio1_io_out_data[5] , \rv32.gpio1_io_out_data[4] , \rv32.gpio1_io_out_data[3] , \rv32.gpio1_io_out_data[2] , \rv32.gpio1_io_out_data[1] , \rv32.gpio1_io_out_data[0] }),
+	.gpio1_io_out_en({\rv32.gpio1_io_out_en[7] , \rv32.gpio1_io_out_en[6] , \rv32.gpio1_io_out_en[5] , \rv32.gpio1_io_out_en[4] , \rv32.gpio1_io_out_en[3] , \rv32.gpio1_io_out_en[2] , \rv32.gpio1_io_out_en[1] , \rv32.gpio1_io_out_en[0] }),
+	.sys_ctrl_clkSource({\rv32.sys_ctrl_clkSource[1] , \rv32.sys_ctrl_clkSource[0] }),
+	.sys_ctrl_hseEnable(\rv32.sys_ctrl_hseEnable ),
+	.sys_ctrl_hseBypass(\rv32.sys_ctrl_hseBypass ),
+	.sys_ctrl_pllEnable(\rv32.sys_ctrl_pllEnable ),
+	.sys_ctrl_pllReady(\auto_generated_inst.hbo_13_a07d11f4c42b3d12_bp ),
+	.sys_ctrl_sleep(\rv32.sys_ctrl_sleep ),
+	.sys_ctrl_stop(\rv32.sys_ctrl_stop ),
+	.sys_ctrl_standby(\rv32.sys_ctrl_standby ),
+	.gpio2_io_in({gnd, gnd, gnd, gnd, gnd, \PIN_96~input_o , \PIN_95~input_o , \PIN_97~input_o }),
+	.gpio2_io_out_data({\rv32.gpio2_io_out_data[7] , \rv32.gpio2_io_out_data[6] , \rv32.gpio2_io_out_data[5] , \rv32.gpio2_io_out_data[4] , \rv32.gpio2_io_out_data[3] , \rv32.gpio2_io_out_data[2] , \rv32.gpio2_io_out_data[1] , \rv32.gpio2_io_out_data[0] }),
+	.gpio2_io_out_en({\rv32.gpio2_io_out_en[7] , \rv32.gpio2_io_out_en[6] , \rv32.gpio2_io_out_en[5] , \rv32.gpio2_io_out_en[4] , \rv32.gpio2_io_out_en[3] , \rv32.gpio2_io_out_en[2] , \rv32.gpio2_io_out_en[1] , \rv32.gpio2_io_out_en[0] }),
+	.gpio3_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.gpio3_io_out_data({\rv32.gpio3_io_out_data[7] , \rv32.gpio3_io_out_data[6] , \rv32.gpio3_io_out_data[5] , \rv32.gpio3_io_out_data[4] , \rv32.gpio3_io_out_data[3] , \rv32.gpio3_io_out_data[2] , \rv32.gpio3_io_out_data[1] , \rv32.gpio3_io_out_data[0] }),
+	.gpio3_io_out_en({\rv32.gpio3_io_out_en[7] , \rv32.gpio3_io_out_en[6] , \rv32.gpio3_io_out_en[5] , \rv32.gpio3_io_out_en[4] , \rv32.gpio3_io_out_en[3] , \rv32.gpio3_io_out_en[2] , \rv32.gpio3_io_out_en[1] , \rv32.gpio3_io_out_en[0] }),
+	.gpio4_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.gpio4_io_out_data({\rv32.gpio4_io_out_data[7] , \rv32.gpio4_io_out_data[6] , \rv32.gpio4_io_out_data[5] , \rv32.gpio4_io_out_data[4] , \rv32.gpio4_io_out_data[3] , \rv32.gpio4_io_out_data[2] , \rv32.gpio4_io_out_data[1] , \rv32.gpio4_io_out_data[0] }),
+	.gpio4_io_out_en({\rv32.gpio4_io_out_en[7] , \rv32.gpio4_io_out_en[6] , \rv32.gpio4_io_out_en[5] , \rv32.gpio4_io_out_en[4] , \rv32.gpio4_io_out_en[3] , \rv32.gpio4_io_out_en[2] , \rv32.gpio4_io_out_en[1] , \rv32.gpio4_io_out_en[0] }),
+	.gpio5_io_in({gnd, gnd, gnd, gnd, \PIN_7~input_o , \PIN_98~input_o , \PIN_93~input_o , \PIN_23~input_o }),
+	.gpio5_io_out_data({\rv32.gpio5_io_out_data[7] , \rv32.gpio5_io_out_data[6] , \rv32.gpio5_io_out_data[5] , \rv32.gpio5_io_out_data[4] , \rv32.gpio5_io_out_data[3] , \rv32.gpio5_io_out_data[2] , \rv32.gpio5_io_out_data[1] , \rv32.gpio5_io_out_data[0] }),
+	.gpio5_io_out_en({\rv32.gpio5_io_out_en[7] , \rv32.gpio5_io_out_en[6] , \rv32.gpio5_io_out_en[5] , \rv32.gpio5_io_out_en[4] , \rv32.gpio5_io_out_en[3] , \rv32.gpio5_io_out_en[2] , \rv32.gpio5_io_out_en[1] , \rv32.gpio5_io_out_en[0] }),
+	.gpio6_io_in({gnd, gnd, \PIN_26~input_o , gnd, \PIN_83~input_o , gnd, \PIN_69~input_o , gnd}),
+	.gpio6_io_out_data({\rv32.gpio6_io_out_data[7] , \rv32.gpio6_io_out_data[6] , \rv32.gpio6_io_out_data[5] , \rv32.gpio6_io_out_data[4] , \rv32.gpio6_io_out_data[3] , \rv32.gpio6_io_out_data[2] , \rv32.gpio6_io_out_data[1] , \rv32.gpio6_io_out_data[0] }),
+	.gpio6_io_out_en({\rv32.gpio6_io_out_en[7] , \rv32.gpio6_io_out_en[6] , \rv32.gpio6_io_out_en[5] , \rv32.gpio6_io_out_en[4] , \rv32.gpio6_io_out_en[3] , \rv32.gpio6_io_out_en[2] , \rv32.gpio6_io_out_en[1] , \rv32.gpio6_io_out_en[0] }),
+	.gpio7_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.gpio7_io_out_data({\rv32.gpio7_io_out_data[7] , \rv32.gpio7_io_out_data[6] , \rv32.gpio7_io_out_data[5] , \rv32.gpio7_io_out_data[4] , \rv32.gpio7_io_out_data[3] , \rv32.gpio7_io_out_data[2] , \rv32.gpio7_io_out_data[1] , \rv32.gpio7_io_out_data[0] }),
+	.gpio7_io_out_en({\rv32.gpio7_io_out_en[7] , \rv32.gpio7_io_out_en[6] , \rv32.gpio7_io_out_en[5] , \rv32.gpio7_io_out_en[4] , \rv32.gpio7_io_out_en[3] , \rv32.gpio7_io_out_en[2] , \rv32.gpio7_io_out_en[1] , \rv32.gpio7_io_out_en[0] }),
+	.gpio8_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.gpio8_io_out_data({\rv32.gpio8_io_out_data[7] , \rv32.gpio8_io_out_data[6] , \rv32.gpio8_io_out_data[5] , \rv32.gpio8_io_out_data[4] , \rv32.gpio8_io_out_data[3] , \rv32.gpio8_io_out_data[2] , \rv32.gpio8_io_out_data[1] , \rv32.gpio8_io_out_data[0] }),
+	.gpio8_io_out_en({\rv32.gpio8_io_out_en[7] , \rv32.gpio8_io_out_en[6] , \rv32.gpio8_io_out_en[5] , \rv32.gpio8_io_out_en[4] , \rv32.gpio8_io_out_en[3] , \rv32.gpio8_io_out_en[2] , \rv32.gpio8_io_out_en[1] , \rv32.gpio8_io_out_en[0] }),
+	.gpio9_io_in({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.gpio9_io_out_data({\rv32.gpio9_io_out_data[7] , \rv32.gpio9_io_out_data[6] , \rv32.gpio9_io_out_data[5] , \rv32.gpio9_io_out_data[4] , \rv32.gpio9_io_out_data[3] , \rv32.gpio9_io_out_data[2] , \rv32.gpio9_io_out_data[1] , \rv32.gpio9_io_out_data[0] }),
+	.gpio9_io_out_en({\rv32.gpio9_io_out_en[7] , \rv32.gpio9_io_out_en[6] , \rv32.gpio9_io_out_en[5] , \rv32.gpio9_io_out_en[4] , \rv32.gpio9_io_out_en[3] , \rv32.gpio9_io_out_en[2] , \rv32.gpio9_io_out_en[1] , \rv32.gpio9_io_out_en[0] }),
+	.ext_resetn(vcc),
+	.resetn_out(\rv32.resetn_out ),
+	.dmactive(\rv32.dmactive ),
+	.swj_JTAGNSW(\rv32.swj_JTAGNSW ),
+	.swj_JTAGSTATE({\rv32.swj_JTAGSTATE[3] , \rv32.swj_JTAGSTATE[2] , \rv32.swj_JTAGSTATE[1] , \rv32.swj_JTAGSTATE[0] }),
+	.swj_JTAGIR({\rv32.swj_JTAGIR[3] , \rv32.swj_JTAGIR[2] , \rv32.swj_JTAGIR[1] , \rv32.swj_JTAGIR[0] }),
+	.ext_int({gnd, gnd, gnd, gnd, gnd, gnd, gnd, gnd}),
+	.ext_dma_DMACBREQ({gnd, gnd, gnd, gnd}),
+	.ext_dma_DMACLBREQ({gnd, gnd, gnd, gnd}),
+	.ext_dma_DMACSREQ({gnd, gnd, gnd, gnd}),
+	.ext_dma_DMACLSREQ({gnd, gnd, gnd, gnd}),
+	.ext_dma_DMACCLR({\rv32.ext_dma_DMACCLR[3] , \rv32.ext_dma_DMACCLR[2] , \rv32.ext_dma_DMACCLR[1] , \rv32.ext_dma_DMACCLR[0] }),
+	.ext_dma_DMACTC({\rv32.ext_dma_DMACTC[3] , \rv32.ext_dma_DMACTC[2] , \rv32.ext_dma_DMACTC[1] , \rv32.ext_dma_DMACTC[0] }),
+	.local_int({gnd, gnd, gnd, gnd}),
+	.test_mode({gnd, gnd}),
+	.usb0_xcvr_clk(gnd),
+	.usb0_id(vcc));
+defparam rv32.coord_x = 0;
+defparam rv32.coord_y = 5;
+defparam rv32.coord_z = 0;
+
+endmodule

logic/af_ip.tcl

@@ -0,0 +1,50 @@
+set AGM_SUPRA true
+set DESIGN "PT_0104"
+set IPLIST {alta_bram alta_bram9k alta_sram alta_wram alta_pll alta_pllx alta_pllv alta_pllve alta_boot alta_osc alta_mult alta_multm alta_ufm alta_ufms alta_ufml alta_i2c alta_spi alta_irda alta_mcu alta_mcu_m3 alta_saradc alta_adc alta_dac alta_cmp }
+lappend IPLIST alta_rv32
+
+proc set_alta_partition {inst tag} {
+  set full_name [get_name_info -observable_type pre_synthesis -info full_path $inst]
+  set inst_name [get_name_info -observable_type pre_synthesis -info short_full_path $inst]
+  set base_name [get_name_info -observable_type pre_synthesis -info instance_name $inst]
+  set section_id [string map { [ _ ] _ . _ | _} $inst_name]
+  eval "set_global_assignment -name PARTITION_COLOR 52377 -section_id $section_id -tag $tag"
+  eval "set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id $section_id -tag $tag"
+  eval "set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id $section_id -tag $tag"
+  eval "set_instance_assignment -name PARTITION_HIERARCHY $section_id -to $full_name -section_id $section_id -tag $tag"
+}
+
+load_package flow
+if { $DESIGN == "" } {
+  set DESIGN $::quartus(args)
+}
+project_open $DESIGN
+
+set tag alta_auto
+if { [llength $IPLIST] > 0 } {
+  # A Quartus bug saves PARTITION_HIERARCHY assignments without tag. Use section_id to remove them.
+  set asgn_col [get_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag]
+  foreach_in_collection part $asgn_col {
+    set section_id [lindex $part 0]
+    eval "remove_all_instance_assignments -name PARTITION_HIERARCHY -section_id $section_id"
+  }
+  eval "remove_all_global_assignments -name PARTITION_COLOR -tag $tag"
+  eval "remove_all_global_assignments -name PARTITION_NETLIST_TYPE -tag $tag"
+  eval "remove_all_global_assignments -name PARTITION_FITTER_PRESERVATION_LEVEL -tag $tag"
+  catch { execute_module -tool map }
+
+  foreach ip $IPLIST {
+    foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "$ip:*"] {
+      set_alta_partition $inst $tag
+    }
+    foreach_in_collection inst [get_names -node_type hierarchy -observable_type pre_synthesis -filter "*|$ip:*"] {
+      set_alta_partition $inst $tag
+    }
+  }
+}
+eval "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation"
+
+project_close
+
+exit
+

logic/af_quartus.tcl

@@ -0,0 +1,50 @@
+set AGM_SUPRA true
+set RETRY 0
+set DESIGN "PT_0104"
+
+if { [is_project_open] } {
+  export_assignments
+}
+
+set is_compatible false
+if { $is_compatible } {
+  cd 
+  qexec "[file join $::quartus(binpath) quartus_eda] $DESIGN --simulation --tool=modelsim --format=verilog"
+} else {
+  set FITTER_EFFORTS    {"STANDARD FIT" "STANDARD FIT" "FAST FIT" "FAST FIT" "FAST FIT"}
+  set SEEDS             [list [expr int(rand()*100)] \
+                              [expr int(rand()*100)] \
+                              [expr int(rand()*100)] \
+                              [expr int(rand()*100)] \
+                              [expr int(rand()*100)]]
+  set PLACEMENT_EFFORTS [list [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1] \
+                              [expr rand()*5+0.1]]
+  set    ROUTER_EFFORTS [list [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25] \
+                              [expr rand()*5+0.25]]
+
+  qexec "[file join $::quartus(binpath) quartus_sh] -t af_ip.tcl"
+
+  load_package flow
+  project_open $DESIGN
+
+  set RETRY [expr $RETRY<[llength $FITTER_EFFORTS]?$RETRY:[llength $FITTER_EFFORTS]]
+  for {set nn -1} {$nn < $RETRY} {incr nn} {
+    if {$nn >= 0}  {
+      set_global_assignment -name FITTER_EFFORT \"[lindex $FITTER_EFFORTS $nn]\"
+      set_global_assignment -name SEED [lindex $SEEDS $nn]
+      set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER [lindex $PLACEMENT_EFFORTS $nn]
+      set_global_assignment -name    ROUTER_EFFORT_MULTIPLIER [lindex    $ROUTER_EFFORTS $nn]
+    }
+
+    set code [catch {execute_flow -compile} msg]
+    if { $code == 0 } { break }
+  }
+}
+
+

logic/af_run.tcl

@@ -0,0 +1,350 @@
+set ALTA_SUPRA true
+set sh_continue_on_error false
+set sh_echo_on_source  true
+set sh_quiet_on_source true
+set cc_critical_as_fatal true
+set rt_incremental_route true
+set ta_report_auto 1
+set ta_report_auto_constraints $ta_report_auto
+
+if { ! [info exists RESULT_DIR] } {
+  set RESULT_DIR "."
+} elseif { ! [info exists alta_work] } {
+  set alta_work [file join ${RESULT_DIR} alta_db]
+}
+if { ! [info exists DEVICE] } {
+  set DEVICE "AGRV2KL100"
+}
+if { [info exists DESIGN] && ! [info exists TOP_MODULE] } {
+  set TOP_MODULE "$DESIGN"
+}
+if { ! [info exists DESIGN] } {
+  set DESIGN "PT_0104"
+}
+if { ! [info exists TOP_MODULE] } {
+  set TOP_MODULE "top"
+}
+if { ! [info exists IP_FILES] } {
+  set IP_FILES {}
+}
+if { ! [info exists VE_FILE] } {
+  set VE_FILE ""
+}
+if { ! [info exists TIMING_DERATE] } {
+  set TIMING_DERATE {1.000000 1.000000}
+}
+if { [info exists NO_ROUTE] && $NO_ROUTE } {
+  set no_route "-no_route"
+} else {
+  set no_route ""
+}
+if { ! [info exists RETRY] } { set RETRY 0 }
+if { ! [info exists SEED ] } { set SEED 666 }
+set seed_rand ""
+if { $SEED == 0 } { set seed_rand "-seed_rand" }
+if { [info exists QUARTUS_SDC] } {
+  set sdc_remove_quartus_column_name $QUARTUS_SDC
+}
+if { ! [info exists ORG_PLACE] } { set ORG_PLACE false }
+if { ! [info exists MODE] } { set MODE "QUARTUS" }
+if { ! [info exists FLOW] } { set FLOW "ALL"    }
+if { $FLOW == "PROBE" } {
+  if { ! [info exists PROBE_FORCE] } { set PROBE_FORCE false }
+  if { ! [info exists PREFIX] } { set PREFIX "probe_" }
+}
+if { ! [info exists PREFIX] } {
+  set RESULT $DESIGN
+} else {
+  set RESULT $PREFIX$DESIGN
+}
+if { $FLOW == "GEN" || $FLOW == "PACK" || $FLOW == "LOAD" } { set no_route "-no_route" }
+set RUN "run"
+if { $FLOW == "CHECK" } {
+  set RUN "check"
+} elseif { $FLOW == "PROBE" } {
+  set RUN "probe"
+} elseif { $FLOW == "GEN" } {
+  set RUN "gen"
+}
+
+if { ! [info exists alta_logs] } {
+  set alta_logs [file join ${RESULT_DIR} alta_logs]
+}
+file mkdir $alta_logs
+alta::begin_log_cmd [file join $alta_logs ${RUN}.log] [file join $alta_logs ${RUN}.err]
+alta::tcl_whisper "Cmd : [alta::prog_path] [alta::prog_version]([alta::prog_subversion])\n"
+alta::tcl_whisper "Args : [string map {\{ \" \} \"} $tcl_cmd_args]\n"
+
+set_seed_rand $SEED
+set ar_timing_derate ${TIMING_DERATE}
+
+date_time
+if { [file exists [file join . ${DESIGN}.pre.asf]] } {
+  alta::tcl_highlight "Using pre-ASF file ${DESIGN}.pre.asf.\n"
+  source [file join . ${DESIGN}.pre.asf]
+}
+
+set LOAD_DB    false
+set LOAD_PLACE false
+set LOAD_ROUTE false
+if { $FLOW == "LOAD" || $FLOW == "CHECK" || $FLOW == "PROBE" } {
+  set LOAD_DB    true
+  set LOAD_PLACE true
+  set LOAD_ROUTE true
+} elseif { $FLOW == "R" || $FLOW == "ROUTE" } {
+  set LOAD_DB    true
+  set LOAD_PLACE true
+}
+
+set ORIGINAL_QSF "./PT_0104.qsf"
+set ORIGINAL_PIN ""
+
+#################################################################################
+
+while (1) {
+if { [info exists CORNER] } { set_mode -corner $CORNER; }
+
+eval "load_architect ${no_route} -type ${DEVICE} 1 1 1000 1000"
+foreach ip_file $IP_FILES { read_ip $ip_file; }
+
+
+if { $FLOW == "GEN" } {
+  if { ! [info exists CONFIG_BITS] } {
+    set CONFIG_BITS [file join ${RESULT_DIR} ${DESIGN}.bin]
+  }
+  if { [llength $CONFIG_BITS] > 1 } {
+    if { ! [info exists BOOT_BINARY] } {
+      set BOOT_BINARY [file join ${RESULT_DIR} ${DESIGN}_boot.bin]
+    }
+    if { ! [info exists CONFIG_ADDRESSES] } {
+      set CONFIG_ADDRESSES ""
+    }
+    generate_binary -master $BOOT_BINARY -inputs $CONFIG_BITS -address $CONFIG_ADDRESSES
+  } else {
+    set CONFIG_ROOT   [file rootname [lindex $CONFIG_BITS 0]]
+    set SLAVE_RBF     "${CONFIG_ROOT}_slave.rbf"
+    set MASTER_BINARY "${CONFIG_ROOT}_master.bin"
+    if { [file exists [lindex $CONFIG_BITS 0]] } {
+      generate_binary -slave  $SLAVE_RBF     -inputs [lindex $CONFIG_BITS 0] -reverse
+      generate_binary -master $MASTER_BINARY -inputs [lindex $CONFIG_BITS 0]
+    }
+    if { ! [info exists BOOT_BINARY] } {
+      set BOOT_BINARY $MASTER_BINARY
+    }
+  }
+  set PRG_FILE [file rootname $BOOT_BINARY].prg
+  set AS_FILE  [file rootname $BOOT_BINARY]_as.prg
+  generate_programming_file $BOOT_BINARY -erase $ERASE \
+                            -program $PROGRAM -verify $VERIFY -offset $OFFSET \
+                            -prg $PRG_FILE -as $AS_FILE
+  break
+}
+
+if { $LOAD_DB } {
+  load_db -top ${TOP_MODULE}
+  set sdc [file join . ${DESIGN}.adc]
+  if { ! [file exists $sdc] } { set sdc [file join . ${DESIGN}.sdc]; }
+  if { [file exists $sdc] } { read_sdc $sdc; }
+
+} elseif { $MODE == "QUARTUS" } {
+  set verilog ${DESIGN}.vo
+  set is_migrated false
+  if { ! [file exists $verilog] } {
+    set verilog [file join . simulation modelsim ${DESIGN}.vo]
+    set is_migrated true
+  }
+  if { ! [file exists $verilog] } {
+    error "Can not find design verilog file $verilog"
+  }
+  alta::tcl_highlight "Using design verilog file $verilog.\n"
+  set ret [read_design -top ${TOP_MODULE} -ve $VE_FILE -qsf $ORIGINAL_QSF $verilog -hierachy 1]
+  if { !$ret } { exit -1; }
+
+  set sdc [file join . ${DESIGN}.adc]
+  if { ! [file exists $sdc] } { set sdc [file join . ${DESIGN}.sdc]; }
+  if { ! [file exists $sdc] } {
+    alta::tcl_warn "Can not find design SDC file $sdc"
+  } else {
+    alta::tcl_highlight "Using design SDC file $sdc.\n"
+    read_sdc $sdc
+  }
+
+} elseif { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } {
+  set db_gclk_assignment_level 2
+  set verilog ${DESIGN}.vqm
+  set is_migrated false
+  if { ! [file exists $verilog] } {
+    error "Can not find design verilog file $verilog"
+  }
+
+  set sdc [file join . ${DESIGN}.adc]
+  if { ! [file exists $sdc] } { set sdc [file join . ${DESIGN}.sdc]; }
+  alta::tcl_highlight "Using design verilog file $verilog.\n"
+  if { ! [file exists $sdc] } {
+    alta::tcl_warn "Can not find design SDC file $sdc"
+    set ret [read_design_and_pack -sdc $sdc  -top ${TOP_MODULE} $verilog]
+  } else {
+    alta::tcl_highlight "Using design SDC file $sdc.\n"
+    set ret [read_design_and_pack -top ${TOP_MODULE} $verilog]
+  }
+  if { !$ret } { exit -1; }
+
+} else {
+  error "Unsupported mode $MODE"
+}
+
+if { $FLOW == "PACK" } { break }
+
+if { [info exists FITTING] } {
+  if { $FITTING == "Auto" } { set FITTING auto; }
+  set_mode -fitting $FITTING
+}
+if { [info exists FITTER] } {
+  if { $FITTER == "Auto" } {
+    if { $MODE == "QUARTUS" } { set FITTER hybrid; } else { set FITTER full; }
+  }
+  if { $MODE == "SYNPLICITY" || $MODE == "NATIVE" } { set FITTER full; }
+  set_mode -fitter $FITTER
+}
+if { [info exists EFFORT] } { set_mode -effort $EFFORT; }
+if { [info exists SKEW  ] } { set_mode -skew   $SKEW  ; }
+if { [info exists SKOPE ] } { set_mode -skope  $SKOPE ; }
+if { [info exists HOLDX ] } { set_mode -holdx  $HOLDX; }
+if { [info exists TUNING] } { set_mode -tuning $TUNING; }
+if { [info exists TARGET] } { set_mode -target $TARGET; }
+if { [info exists PRESET] } { set_mode -preset $PRESET; }
+if { [info exists ADJUST] } { set pl_criticality_wadjust $ADJUST; }
+
+set alta_aqf [file join $::alta_work alta.aqf]
+if { $LOAD_DB } {
+  # Empty
+} elseif { true } {
+  if { $ORIGINAL_PIN != "" } {
+    if { [file exists $VE_FILE] } {
+      set ORIGINAL_PIN ""
+    } elseif { $ORIGINAL_PIN == "-" } {
+      set ORIGINAL_PIN ""
+    } elseif { ! [file exists $ORIGINAL_PIN] } {
+      if { $is_migrated } {
+        error "Can not find design PIN file $ORIGINAL_PIN, please compile design first"
+      }
+      set ORIGINAL_PIN ""
+    }
+  }
+  if { $ORIGINAL_QSF != "" } {
+    if { $ORIGINAL_QSF == "-" } {
+      set ORIGINAL_QSF ""
+    } elseif { ! [file exists $ORIGINAL_QSF] } {
+      if { $is_migrated } {
+        error "Can not find design exported QSF file $ORIGINAL_QSF, please export assigments first"
+      }
+    }
+  }
+  alta::convert_quartus_settings_cmd $ORIGINAL_QSF $ORIGINAL_PIN $alta_aqf
+}
+if { [file exists "$alta_aqf"] } {
+  alta::tcl_highlight "Using AQF file $alta_aqf.\n"
+  source "$alta_aqf"
+}
+if { [file exists [file join . ${DESIGN}.asf]] } {
+  alta::tcl_highlight "Using ASF file ${DESIGN}.asf.\n"
+  source [file join . ${DESIGN}.asf]
+}
+
+if { $FLOW == "PROBE" } {
+  set ret [place_pseudo -user_io -place_io -place_pll -place_gclk]
+  if { !$ret } { exit -1 }
+
+  set force ""
+  if { [info exists PROBE_FORCE] && $PROBE_FORCE } { set force "-force" }
+  eval "probe_design -froms {${PROBE_FROMS}} -tos {${PROBE_TOS}} ${force}"
+
+} elseif { $FLOW == "CHECK" } {
+  set ret [place_pseudo -user_io -place_io -place_pll -place_gclk]
+  if { !$ret } { exit -1 }
+
+  if { [file exists [file join . ${DESIGN}.chk]] } {
+    alta::tcl_highlight "Using CHK file ${DESIGN}.chk.\n"
+    source [file join . ${DESIGN}.chk]
+    place_design -dry
+    check_design -rule led_guide
+  } else {
+    error "Can not find design CHECK file ${DESIGN}.chk"
+  }
+
+} else {
+  set ret [place_pseudo -user_io -place_io -place_pll -place_gclk -warn_io]
+  if { !$ret } { exit -1 }
+
+  set org_place ""
+  set load_place ""
+  set load_route ""
+  set quiet ""
+  if {  $ORG_PLACE } { set  org_place "-org_place" ; }
+  if { $LOAD_PLACE } { set load_place "-load_place"; }
+  if { $LOAD_ROUTE } { set load_route "-load_route"; }
+  eval "place_and_route_design $org_place $load_place $load_route \
+                               -retry $RETRY $seed_rand $quiet"
+}
+
+date_time
+if { $FLOW != "CHECK" } {
+if { $FLOW != "PROBE" } {
+report_timing -verbose 2 -setup -file $::alta_work/setup.rpt.gz
+report_timing -verbose 1 -setup -file $::alta_work/setup_summary.rpt
+report_timing -verbose 2 -hold -file $::alta_work/hold.rpt.gz
+report_timing -verbose 1 -hold -file $::alta_work/hold_summary.rpt
+
+set ta_report_auto_constraints 0
+report_timing -fmax -file $::alta_work/fmax.rpt
+report_timing -xfer -file $::alta_work/xfer.rpt
+set ta_report_auto_constraints $ta_report_auto
+
+set ta_dump_uncovered 1
+report_timing -verbose 1 -coverage >! $::alta_work/coverage.rpt.gz
+set ta_dump_uncovered -1
+
+
+if { ! [info exists rt_report_timing_fast] } {
+  set rt_report_timing_fast false
+}
+if { $rt_report_timing_fast } {
+  set_timing_corner fast
+  route_delay -quiet
+  report_timing -verbose 2 -setup -file $::alta_work/setup_fast.rpt.gz
+  report_timing -verbose 1 -setup -file $::alta_work/setup_fast_summary.rpt
+  report_timing -verbose 2 -hold -file $::alta_work/hold_fast.rpt.gz
+  report_timing -verbose 1 -hold -file $::alta_work/hold_fast_summary.rpt
+  set ta_report_auto_constraints 0
+  report_timing -fmax -file $::alta_work/fmax_fast.rpt
+  report_timing -xfer -file $::alta_work/xfer_fast.rpt
+  set ta_report_auto_constraints $ta_report_auto
+}
+
+write_routed_design "${RESULT_DIR}/${RESULT}_routed.v"
+}
+
+bitgen normal -prg "${RESULT_DIR}/${RESULT}.prg" -bin "${RESULT_DIR}/${RESULT}.bin"
+if { true } {
+alta::bin_to_asc "${RESULT_DIR}/${RESULT}.bin" "${RESULT_DIR}/${RESULT}.inc"
+} else {
+bitgen sram -prg "${RESULT_DIR}/${RESULT}_sram.prg"
+bitgen download -bin "${RESULT_DIR}/${RESULT}.bin" -svf "${RESULT_DIR}/${RESULT}_download.svf"
+generate_binary -slave "${RESULT_DIR}/${RESULT}_slave.rbf" \
+                -inputs "${RESULT_DIR}/${RESULT}.bin" -reverse
+generate_binary -master "${RESULT_DIR}/${RESULT}_master.bin" \
+                -inputs "${RESULT_DIR}/${RESULT}.bin"
+generate_programming_file "${RESULT_DIR}/${RESULT}_master.bin" -prg "${RESULT_DIR}/${RESULT}_master.prg" \
+  -as "${RESULT_DIR}/${RESULT}_master_as.prg" -hybrid "${RESULT_DIR}/${RESULT}_hybrid.prg"
+}
+}
+break
+}
+
+if { [file exists "./${DESIGN}.post.asf"] } {
+  alta::tcl_highlight "Using post-ASF file ${DESIGN}.post.asf.\n"
+  source "./${DESIGN}.post.asf"
+}
+date_time
+exit
+

logic/logic_log.txt

@@ -0,0 +1,367 @@
+> set sh_continue_on_error false
+> set sh_echo_on_source  true
+> set sh_quiet_on_source true
+> set cc_critical_as_fatal true
+> 
+> set_seed_rand 10
+> if { ! [info exists LOGIC_DEVICE] } {
+  set LOGIC_DEVICE AGRV2KL100
+}
+> if { ! [info exists LOGIC_DESIGN] } {
+  set LOGIC_DESIGN top
+}
+> if { ! [info exists LOGIC_MODULE] } {
+  set LOGIC_MODULE top
+}
+> if { ! [info exists IP_INSTALL_DIR] } {
+  set IP_INSTALL_DIR ""
+}
+> if { ! [info exists LOGIC_DIR] } {
+  set LOGIC_DIR .
+}
+> if { ! [info exists LOGIC_VV] } {
+  set LOGIC_VV "${LOGIC_DESIGN}.v"
+}
+> if { ! [info exists IP_VV] } {
+  set IP_VV ""
+}
+> if { ! [info exists LOGIC_ASF] } {
+  set LOGIC_ASF ""
+}
+> if { ! [info exists LOGIC_PRE] } {
+  set LOGIC_PRE ""
+}
+> if { ! [info exists LOGIC_POST] } {
+  set LOGIC_POST ""
+}
+> if { ! [info exists LOGIC_FORCE] } {
+  set LOGIC_FORCE false
+}
+> if { ! [info exists LOGIC_COMPRESS] } {
+  set LOGIC_COMPRESS false
+}
+> 
+> cd $LOGIC_DIR
+> 
+> alta::set_verbose_cmd false
+> set logic_qsf ${LOGIC_DESIGN}.qsf
+> set skip_setup false
+> if { [file exists $logic_qsf] } {
+  if { $LOGIC_FORCE } {
+    alta::tcl_info "Overwrite existing LOGIC preparation files in $LOGIC_DIR"
+  } else {
+    alta::tcl_warn "Files for LOGIC preparation already exist in $LOGIC_DIR, will not overwrite"
+    set skip_setup true
+  }
+}
+Warn: Files for LOGIC preparation already exist in logic, will not overwrite.
+> set logic_ip false
+> if { $IP_INSTALL_DIR != "" } {
+  set logic_ip true
+}
+> 
+> set ETC_DIR [file join [alta::prog_home] "etc"]
+> set IP_FILES ""
+> set VERILOG_FILES $LOGIC_VV
+> if { $IP_VV != "" } {
+  set VERILOG_FILES "$VERILOG_FILES $IP_VV"
+}
+> set VQM_FILES ""
+> set VHDL_FILES ""
+> set AF_QUARTUS_TEMPL [file join $ETC_DIR "af_quartus.tcl"]
+> set AF_QUARTUS "af_quartus.tcl"
+> set AF_IP_TEMPL [file join $ETC_DIR "af_ip.tcl"]
+> set AF_IP "af_ip.tcl"
+> set AF_MAP_TEMPL ""
+> set AF_MAP ""
+> set AF_RUN_TEMPL [file join $ETC_DIR "af_run.tcl"]
+> set AF_RUN "af_run.tcl"
+> set AF_BATCH_TEMPL ""
+> set AF_BATCH ""
+> set VE_FILE ""
+> 
+> if { ! [info exists ORIGINAL_DIR] } {
+  set ORIGINAL_DIR ""
+}
+> if { ! [info exists ORIGINAL_OUTPUT] } {
+  set ORIGINAL_OUTPUT ""
+}
+> if { ! [info exists ORIGINAL_QSF] } {
+  set ORIGINAL_QSF ""
+}
+> if { ! [info exists ORIGINAL_PIN] } {
+  set ORIGINAL_PIN ""
+}
+> 
+> set GCLK_CNT -1; # Allow an extra gclk for GCLKSW
+> set USE_DESIGN_TEMPL true
+> 
+> set logic_hx ${LOGIC_DESIGN}.hx
+> set hx_fp [open $logic_hx r]
+> set hsi_freq 0
+> set hse_freq 0
+> set sys_freq 0
+> set bus_freq 0
+> while { [gets $hx_fp line] >= 0 } {
+  set words [split $line]
+  if { [lindex $words 0] == "#define" } {
+    if { [lindex $words 1] == "BOARD_HSI_FREQUENCY" } {
+      set hsi_freq [lindex $words 2]
+    } elseif { [lindex $words 1] == "BOARD_HSE_FREQUENCY" } {
+      set hse_freq [lindex $words 2]
+    } elseif { [lindex $words 1] == "BOARD_PLL_FREQUENCY" } {
+      set sys_freq [lindex $words 2]
+    } elseif { [lindex $words 1] == "BOARD_BUS_FREQUENCY" } {
+      set bus_freq [lindex $words 2]
+    }
+    if { [lindex $words 1] == "BOARD_PLL_CLKIN" } {
+      set BOARD_PLL_CLKIN [lindex $words 2]
+    }
+    if { [lindex $words 1] == "USB0_MODE" } {
+      set USB0_MODE [lindex $words 2]
+    }
+  }
+}
+> close $hx_fp
+> 
+> if { ! $logic_ip } {
+  set sdc_file ${LOGIC_DESIGN}.sdc
+  set sdc_ip ""
+} else {
+  set sdc_file ${LOGIC_DESIGN}_.sdc
+  set sdc_ip ${LOGIC_DESIGN}.sdc
+}
+> 
+> if { ! $skip_setup } {
+  if { ! [file exists $sdc_file] } {
+    set sdc_fp [open $sdc_file w]
+    puts $sdc_fp "# pio_begin"
+    if { $hsi_freq != 0 } {
+      set hsi_period [expr 1000000000.0/$hsi_freq]
+      puts $sdc_fp "if { ! \[info exists ::HSI_PERIOD\] } {"
+      puts $sdc_fp "  set ::HSI_PERIOD $hsi_period"
+      puts $sdc_fp "}"
+      puts $sdc_fp "create_clock -name PIN_HSI -period \$::HSI_PERIOD \[get_ports PIN_HSI\]"
+      puts $sdc_fp "set_clock_groups -asynchronous -group PIN_HSI"
+    }
+    if { $hse_freq != 0 } {
+      set hse_period [expr 1000000000.0/$hse_freq]
+      puts $sdc_fp "if { ! \[info exists ::HSE_PERIOD\] } {"
+      puts $sdc_fp "  set ::HSE_PERIOD $hse_period"
+      puts $sdc_fp "}"
+      puts $sdc_fp "create_clock -name PIN_HSE -period \$::HSE_PERIOD \[get_ports PIN_HSE\]"
+      puts $sdc_fp "set_clock_groups -asynchronous -group PIN_HSE"
+    }
+    puts $sdc_fp "derive_pll_clocks -create_base_clocks"
+    puts $sdc_fp "# pio_end"
+    close $sdc_fp
+  }
+
+  if { $sdc_ip != "" && ! [file exists $sdc_ip] } {
+    set sdc_fp [open $sdc_ip w]
+    puts $sdc_fp "# pio_begin"
+    if { $sys_freq != 0 } {
+      set sys_period [expr 1000000000.0/$sys_freq]
+      puts $sdc_fp "create_clock -name sys_clock -period $sys_period \[get_ports sys_clock\]"
+    }
+    if { $bus_freq != 0 } {
+      set bus_period [expr 1000000000.0/$bus_freq]
+      puts $sdc_fp "create_clock -name bus_clock -period $bus_period \[get_ports bus_clock\]"
+    }
+    puts $sdc_fp "# pio_end"
+    close $sdc_fp
+  }
+
+  load_architect -no_route -type $LOGIC_DEVICE
+
+  alta::setupRun ${LOGIC_DESIGN} ${LOGIC_MODULE} \
+                 "${IP_FILES}" \
+                 "${VERILOG_FILES}" \
+                 "${VQM_FILES}" \
+                 "${VHDL_FILES}"\
+                 "${AF_QUARTUS_TEMPL}" "${AF_QUARTUS}"\
+                 "${AF_IP_TEMPL}" "${AF_IP}" \
+                 "${AF_MAP_TEMPL}" "${AF_MAP}" \
+                 "${AF_RUN_TEMPL}" "${AF_RUN}" \
+                 "${AF_BATCH_TEMPL}" "${AF_BATCH}" \
+                 "${VE_FILE}" \
+                 "." "${ORIGINAL_DIR}" "${ORIGINAL_OUTPUT}"\
+                 "${ORIGINAL_QSF}" "${ORIGINAL_PIN}" \
+                 "${GCLK_CNT}" "${USE_DESIGN_TEMPL}"
+
+  if { $logic_ip } {
+    set qsf_fp [open $logic_qsf]
+    set qsf_lines {}
+    set is_pio false
+    while { [gets $qsf_fp line] >= 0 } {
+      if { [string first "pio_begin" $line] >= 0 } {
+        set is_pio true
+      } elseif { [string first "pio_end" $line] >= 0 } {
+        set is_pio false
+      } elseif { ! $is_pio } {
+        lappend qsf_lines $line
+      }
+    }
+    close $qsf_fp
+    set qsf_fp [open $logic_qsf w]
+    puts $qsf_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
+    puts $qsf_fp "set_instance_assignment -name VIRTUAL_PIN ON -to *"
+    puts $qsf_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
+    foreach line $qsf_lines {
+      puts $qsf_fp $line
+    }
+    close $qsf_fp
+
+    set af_run af_run.tcl
+    set run_fp [open $af_run]
+    set run_lines {}
+    set is_pio false
+    while { [gets $run_fp line] >= 0 } {
+      if { [string first "pio_begin" $line] >= 0 } {
+        set is_pio true
+      } elseif { [string first "pio_end" $line] >= 0 } {
+        set is_pio false
+      } elseif { ! $is_pio } {
+        lappend run_lines $line
+      }
+    }
+    close $run_fp
+    set run_fp [open $af_run w]
+    puts $run_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
+    puts $run_fp "set FLOW PACK"
+    puts $run_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
+    foreach line $run_lines {
+      puts $run_fp $line
+    }
+    close $run_fp
+  }
+
+  if { true } {
+    set supra_proj ${LOGIC_DESIGN}.proj
+    set proj_fp [open $supra_proj w]
+    puts $proj_fp {[GuiMigrateSetupPage]}
+    puts $proj_fp "design=$LOGIC_DESIGN"
+    puts $proj_fp "device=$LOGIC_DEVICE"
+    puts $proj_fp ""
+    puts $proj_fp {[GuiMigrateRunPage]}
+    puts $proj_fp "fitting=1"
+    puts $proj_fp "fitter=5"
+    puts $proj_fp "effort=2"
+    puts $proj_fp "skew=2"
+    if { $logic_ip } {
+      puts $proj_fp "flow=0"
+    }
+    close $proj_fp
+  }
+}
+> 
+> if { true } {
+  set pre_asf ${LOGIC_DESIGN}.pre.asf
+  set pre_fp [open $pre_asf r];
+  set pre_lines {}
+  set is_pio false
+  while { [gets $pre_fp line] >= 0 } {
+    if { [string first "db_io_name_priority" $line] >= 0 ||
+         [string first "pio_begin" $line] >= 0 } {
+      set is_pio true
+    } elseif { [string first "pio_end" $line] >= 0 } {
+      set is_pio false
+    } elseif { ! $is_pio } {
+      lappend pre_lines $line
+    }
+  }
+  close $pre_fp
+  set pre_fp [open $pre_asf w]
+  foreach line $pre_lines {
+    puts $pre_fp $line
+  }
+  puts $pre_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
+  if { "$LOGIC_PRE" != "" } {
+    set logic_fp [open $LOGIC_PRE r]; set logic_data [read $logic_fp]; close $logic_fp
+    puts -nonewline $pre_fp $logic_data
+  }
+  if { [info exists BOARD_PLL_CLKIN] } {
+    puts $pre_fp "set BOARD_PLL_CLKIN $BOARD_PLL_CLKIN"
+  }
+  if { [info exists USB0_MODE] } {
+    puts $pre_fp "set USB0_MODE $USB0_MODE"
+  }
+  puts $pre_fp "set db_io_name_priority true"
+  puts $pre_fp "set ip_pll_vco_lowpower true"
+  if { $LOGIC_COMPRESS } {
+    puts $pre_fp "set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION \"ON\""
+  } else {
+    puts $pre_fp "set_global_assignment -name ON_CHIP_BITSTREAM_DECOMPRESSION \"OFF\""
+  }
+  puts $pre_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
+  close $pre_fp
+}
+> 
+> if { true } {
+  set asf_asf ${LOGIC_DESIGN}.asf
+  set asf_fp [open $asf_asf r];
+  set asf_lines {}
+  set is_pio false
+  while { [gets $asf_fp line] >= 0 } {
+    if { [string first "db_io_name_priority" $line] >= 0 ||
+         [string first "pio_begin" $line] >= 0 } {
+      set is_pio true
+    } elseif { [string first "pio_end" $line] >= 0 } {
+      set is_pio false
+    } elseif { ! $is_pio } {
+      lappend asf_lines $line
+    }
+  }
+  close $asf_fp
+  set asf_fp [open $asf_asf w]
+  foreach line $asf_lines {
+    puts $asf_fp $line
+  }
+  puts $asf_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
+  if { "$LOGIC_ASF" != "" } {
+    set logic_fp [open $LOGIC_ASF r]; set logic_data [read $logic_fp]; close $logic_fp
+    puts -nonewline $asf_fp $logic_data
+  }
+  puts $asf_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
+  close $asf_fp
+}
+> 
+> if { true } {
+  set post_asf ${LOGIC_DESIGN}.post.asf
+  set post_fp [open $post_asf r];
+  set post_lines {}
+  set is_pio false
+  while { [gets $post_fp line] >= 0 } {
+    if { [string first "pio_begin" $line] >= 0 } {
+      set is_pio true
+    } elseif { [string first "pio_end" $line] >= 0 } {
+      set is_pio false
+    } elseif { ! $is_pio } {
+      lappend post_lines $line
+    }
+  }
+  close $post_fp
+  set post_fp [open $post_asf w]
+  foreach line $post_lines {
+    puts $post_fp $line
+  }
+  puts $post_fp "# pio_begin  >>>>>> DO NOT MODIFY THIS SECTION! >>>>>>"
+  if { "$LOGIC_POST" != "" } {
+    set logic_fp [open $LOGIC_POST r]; set logic_data [read $logic_fp]; close $logic_fp
+    puts -nonewline $post_fp $logic_data
+  }
+  if { $logic_ip } {
+    puts $post_fp "file mkdir $IP_INSTALL_DIR"
+    puts $post_fp "if { ! \[file exists $IP_INSTALL_DIR/${LOGIC_DESIGN}.sdc\] } {"
+    puts $post_fp "  file copy -force ./${LOGIC_DESIGN}_.sdc $IP_INSTALL_DIR/${LOGIC_DESIGN}.sdc"
+    puts $post_fp "}"
+    puts $post_fp "file copy -force ./${LOGIC_DESIGN}_.ve $IP_INSTALL_DIR/${LOGIC_DESIGN}.ve"
+    puts $post_fp "file copy -force ./alta_db/packed.vx $IP_INSTALL_DIR/${LOGIC_DESIGN}.vx"
+  }
+  puts $post_fp "# pio_end    <<<<<< DO NOT MODIFY THIS SECTION! <<<<<<"
+  close $post_fp
+}
+> 
+> exit
+
+Total 0 fatals, 0 errors, 1 warnings, 0 infos.

myboard.asf

@@ -0,0 +1,11 @@
+if { [info exists BOARD_PLL_CLKIN] } {
+  if { $BOARD_PLL_CLKIN == "PIN_OSC" } {
+    set_config -loc 18 0 0 CFG_RCOSC_EN 1'b1
+  }
+}
+if { [info exists USB0_MODE] } {
+  alta::tcl_info "USB0_MODE = $USB0_MODE"
+  set_config -loc 0 1 3 CFG_PULLUP_ENB 1'b0
+  set_config -loc 0 1 3 CFG_PULLDN_ENB 1'b0
+}
+set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to PIN_26

platformio.ini

@@ -0,0 +1,102 @@
+[setup]
+boards_dir = boards
+board = agrv2k_407
+board_logic.ve = PT_0104.ve
+
+#ips_dir = ../ips
+ip_name = PT_0104_fpga
+logic_dir = logic
+; logic_ve = top.ve
+board_logic.asf = myboard.asf
+
+framework = agrv_sdk
+program = PT_0104_MCU_01042002
+
+src_dir = src
+include_dir = src
+src_filter = "-<*> +<*.c>"
+
+lwip_imp_dir =
+tinyusb_imp_dir =
+#lwip_param = freertos
+#tinyusb_param =
+
+#board_build.boot_addr = upload
+#board_build.boot_mode = sram
+#board_upload.address = 0x20000000
+#board_upload.logic_address = 0x80020000
+#board_logic.device = AGRV2KL100
+#board_logic.ve = my_board.ve
+board_upload.address = 0x80010000
+board_build.boot_addr = 0x80010000
+
+#board_build.boot_mode = flash_sram
+
+board_logic.compress = true
+build_unflags = -O2
+build_flags = -Os
+            -DLOGGER_BAUD_RATE=${setup.monitor_speed}
+            -DAGRV_FP_STACK=0
+            -DDFU_FPGA_CONFIG=\"PT_0104.inc\"
+
+build_src_flags = -Wno-cast-align
+
+
+logger_if = UART0
+#upload_port = /dev/ttyUSB0
+#monitor_port = /dev/ttyUSB0
+upload_port = COM3
+monitor_port = COM3
+monitor_speed = 57600
+debug_speed = 10000
+
+#debug_tools = cmsis-dap-openocd
+#upload_protocols = cmsis-dap-openocd
+#debug_tool = cmsis-dap-openocd
+#upload_protocol = cmsis-dap-openocd
+debug_tool = jlink-openocd
+upload_protocol = jlink-openocd
+
+#build_flags =
+#build_src_flags =
+
+#check_tool = cppcheck, clangtidy, pvs-studio
+#check_device = false
+#check_logic = 2
+
+[setup_rtt]
+logger_if = RTT
+monitor_port = socket://localhost:19021
+
+
+[platformio]
+boards_dir = ${setup.boards_dir}
+src_dir = ${setup.src_dir}
+include_dir = ${setup.include_dir}
+default_envs = dev
+#board_upload.address = 0x80010000
+
+[env]
+platform = AgRV
+extends = setup
+
+[env:dev]
+build_type = debug
+board_upload.address = 0x80010000
+
+[env:release]
+build_type = release
+board_upload.address = 0x80010000
+; board_upload.logic_address = 0x80060000
+
+[env:rtt]
+build_type = debug
+extends = setup_rtt
+
+[env:serial]
+build_type = release
+board_upload.address = 0x80010000
+upload_protocol = serial
+upload_speed = 460800
+custom_speed = 115200
+

src/agm_board.c

@@ -0,0 +1,102 @@
+#include "agm_board.h"
+#include "i2c.h"
+
+
+uint32_t apb_clken;
+uint32_t misc_ctrl;
+void m_fpga_init(void)
+{
+    apb_clken = SYS->APB_CLKENABLE;
+    misc_ctrl = SYS->MISC_CNTL;
+
+    SYS_SetHSIConfig(0xf);
+    SYS_SwitchHSIClock();
+
+    // Provide a minimal working FPGA configuration to avoid problems if the default configuration is corrupted.
+#ifdef DFU_FPGA_CONFIG
+    SYS->APB_CLKENABLE = APB_MASK_FCB0; // Disable all peripherial clocks execpt for FCB to avoid any noise from FPGA
+    __attribute__ ((aligned(4))) uint8_t fpga_config[] = {
+#include DFU_FPGA_CONFIG
+    };
+    FCB_AutoDecompress((uint32_t)fpga_config);
+#endif
+    SYS_SwitchPLLClock(SYS_HSE_BYPASS_OFF); //use hse
+}
+
+__attribute__((weak)) uint32_t FCB_GetPLLFreq(uint32_t clkin_freq);
+void agm_board_init(void)
+{
+#if(1)
+    m_fpga_init();
+    PERIPHERAL_ENABLE(DMAC, 0);
+    DMAC_Init();
+#else
+    PERIPHERAL_ENABLE(DMAC, 0);
+    DMAC_Init();
+
+    if (FCB_GetPLLFreq) {
+        uint32_t freq = BOARD_PLL_FREQUENCY;
+        SYS_EnableAPBClock(APB_MASK_FCB0);
+        if (FCB_IsActive()) {
+            freq = FCB_GetPLLFreq(board_pll_clkin_freq());
+        } else {
+            FCB_Activate();
+        }
+        SYS_SetPLLFreq(freq);
+    }
+    SYS_SwitchPLLClock(board_hse_source());
+#endif
+    INT_Init();
+    INT_EnableIntGlobal();
+    INT_EnableIntExternal();
+
+
+}
+
+
+//ι¹·
+void IWDG_feed(void)
+{
+	IWDG_ReloadCounter();
+}
+
+
+volatile uint32_t Systickcount = 0;
+volatile uint64_t TickCounter_u64 = 0;
+volatile uint8_t M_flag = 0;
+void MTIMER_isr(void)
+{
+  // GPIO_Toggle(EXT_GPIO, EXT_GPIO_BITS);
+//   GPIO_Toggle(LED_GPIO, GPIO_BIT1);
+    Systickcount++;
+    TickCounter_u64++;
+    if(Systickcount%500==0)
+    {
+        GPIO_Toggle(GPIO1, GPIO_BIT0);
+        GPIO_Toggle(GPIO1, GPIO_BIT1);
+        IWDG_feed();
+        M_flag = 1;
+    }
+    INT_SetMtime(0);
+
+}
+
+void TestMtimer(int ms)
+{
+    clint_isr[IRQ_M_TIMER] = MTIMER_isr;
+    INT_SetMtime(0);
+    INT_SetMtimeCmp(SYS_GetSysClkFreq() / 1000 * ms);
+    INT_EnableIntTimer();
+    // while (1);
+}
+
+
+void device_board_init(void)
+{
+    TestMtimer(1);
+    rtc_init();
+    i2c_init();
+    Uart0_Init(115200);
+    Uart2_Init(115200);
+}
+

src/agm_board.h

@@ -0,0 +1,12 @@
+#ifndef _AGM_BOARD_H_
+#define _AGM_BOARD_H_
+
+#include "board.h"
+#include "i2c.h"
+#include "agm_uart.h"
+#include "rtc.h"
+
+extern void agm_board_init(void);
+extern void device_board_init(void);
+
+#endif

src/agm_config.h

@@ -0,0 +1,82 @@
+#ifndef _AGM_CONFIG_H_
+#define _AGM_CONFIG_H_
+
+
+#include "board.h"
+
+//app版本号
+#define SOFTWARE_VERSION_APP 0X01042002
+
+
+
+extern volatile uint32_t Systickcount;
+extern volatile uint64_t TickCounter_u64;
+
+
+
+
+
+
+#define AG32VF407_DEVICE_ID_ADDR 0x03000100
+
+#define LORA_GROUP_NUM 4	//Lora组个数
+#define LORA_ADDR           0X180 //Lora参数起始地址
+
+
+#define DEVICE_ALRD        0x01  //设备信息是否写入eeprom标志
+
+#define EEPROM_VER                 0X01
+#define EEPROM_FIRST_INIT_FLAG     0x5AA5  //是否第一次读eeprom标记
+
+/*第一次上电(0X55)*/
+#define    EECFG_FIRST_INIT0              0x0000
+/*出厂信息是否被初始化过*/
+#define    EECFG_INFO_ALRD_INIT           0x000D
+/*Bootloader版本*/
+#define    EECFG_BT_VER0                  0x0021
+/*APP1版本*/
+#define    EECFG_APP1_VER0                0x0029
+/*EEPROM存储数据字节数*/
+#define    EECFG_NUM                      0x0035
+
+enum BKP_t {
+    BKP_DR1,
+    BKP_DR2,
+    BKP_DR3,
+    BKP_DR4,
+    BKP_DR5,
+    BKP_DR6,
+    BKP_DR7,
+};
+
+#define DEVICE_PUBLIC_INFO_ADDR     0x00        //公共信息存储地址
+#define DEVICE_VERSION_INFO_ADDR    0x100       //软件版本存储地址
+#define DEVICE_RESET_ADDR			0x140		//复位次数存储
+#define FRAM_MQTT_MSG				0x200		//mqtt信息存储地址
+
+#define EEPROM_FIRST_FLAG   0x5AA5  //是否第一次读eeprom标记
+
+
+
+
+
+
+#define MIN_IRQ_PRIORITY 1
+#define MAX_IRQ_PRIORITY PLIC_MAX_PRIORITY
+
+#define I2C_PRIORITY    (MIN_IRQ_PRIORITY + 1)
+#define TIMER_PRIORITY  (MIN_IRQ_PRIORITY + 2)
+#define DMAC_PRIORITY   (MIN_IRQ_PRIORITY + 8)
+#define UART_PRIORITY   (MIN_IRQ_PRIORITY + 9)
+#define CAN_PRIORITY    (MIN_IRQ_PRIORITY + 7)
+#define RTC_PRIORITY    (MIN_IRQ_PRIORITY + 6)
+#define EXT_PRIORITY    (MIN_IRQ_PRIORITY + 4)
+#define SPI_PRIORITY    (MIN_IRQ_PRIORITY + 5)
+#define MEMSPI_PRIORITY (MIN_IRQ_PRIORITY + 1)
+#define GPIO_PRIORITY   (MIN_IRQ_PRIORITY + 1)
+#define FLASH_PRIORITY  (MAX_IRQ_PRIORITY - 5)
+#define USB_PRIORITY    (MAX_IRQ_PRIORITY - 1)
+#define MAC_PRIORITY    (MAX_IRQ_PRIORITY - 1)
+#define WDOG_PRIORITY   (MAX_IRQ_PRIORITY - 0)
+
+#endif

src/agm_uart.c

@@ -0,0 +1,209 @@
+#include "agm_uart.h"
+#include "agm_config.h"
+#include "delay.h"
+#include "timeout.h"
+
+
+uart_info_t uart_info[UART_MAX]; // 串口接收
+
+uint8_t uart_rcv_buf[UART_MAX][UART_RCV_TEMPBUF_LEN]; // 接收数组
+uint16_t uart_rcv_len[UART_MAX];                      // 接收长度
+
+uint32_t uart_delay[UART_MAX];
+
+
+
+void data_dump(const char *name, uint8_t *data, uint16_t length)
+{
+    int index = 0;
+
+    printf("%s Data Info: \r\n    ", name);
+
+    for (index = 0; index < length; index++)
+    {
+        if ((index % 4 == 0) && index)
+        {
+            if ((index % 16 == 0) && index)
+            {
+                printf("\r\n    ");
+            }
+            else
+            {
+                printf(" ");
+            }
+        }
+        printf("%02x ", *(data + index));
+    }
+    printf("\r\n");
+}
+
+//根据波特率计算延时时间
+void uart_baud_delay(uint8_t uartid, uint32_t baud)
+{
+    uint32_t delay,temp;
+    if(uartid >= UART_MAX)
+        return;
+    temp = 1000000/baud;
+    delay = temp*10 + temp*1.5;
+    uart_delay[uartid] = delay;
+    // printf("uart%d,delay:%u\n",uartid,uart_delay[uartid]);
+}
+
+
+void Uart0_Init(uint32_t baud)
+{
+    // GPIO_AF_ENABLE(UART0_UARTRXD);
+    // GPIO_AF_ENABLE(UART0_UARTTXD);
+    GPIO_AF_ENABLE(GPIO_AF_PIN(UART, LOGGER_UART, UARTRXD));
+    GPIO_AF_ENABLE(GPIO_AF_PIN(UART, LOGGER_UART, UARTTXD));
+    SYS_EnableAPBClock(APB_MASK_UART0);
+    UART_Init(UART0, baud, UART_LCR_DATABITS_8, UART_LCR_STOPBITS_1, UART_LCR_PARITY_NONE, UART_LCR_FIFO_1);
+
+    UART_EnableInt(UART0, UART_INT_RX);
+    UART_SetRxIntFifoLevel(UART0, UART_INT_FIFO_HALF);
+    INT_EnableIRQ(UART0_IRQn, UART_PRIORITY);
+
+    uart_baud_delay(0,baud);
+}
+
+
+void UART2_isr(void)
+{
+    char data;
+    if (UART_IsRawIntActive(UART2, UART_INT_RX))
+    {
+        UART_ClearInt(UART2, UART_INT_RX);
+        UART_ReceiveCh(UART2, &data, 0);
+        uart_info[2].p_rcv.rcv_buf[uart_info[2].p_rcv.p_output] = data;
+        uart_info[2].p_rcv.p_output = (uart_info[2].p_rcv.p_output + 1) % UART_RCV_TEMPBUF_LEN;
+
+        timeout_setValue(&uart_info[2].tt_uart, UART_RCV_TIMEOUT, 1);
+    }
+}
+
+void Uart2_Init(uint32_t baud)
+{
+
+    GPIO_AF_ENABLE(GPIO_AF_PIN(UART, 2, UARTRXD));
+    GPIO_AF_ENABLE(GPIO_AF_PIN(UART, 2, UARTTXD));
+    SYS_EnableAPBClock(APB_MASK_UART2);
+    UART_Init(UART2, baud, UART_LCR_DATABITS_8, UART_LCR_STOPBITS_1, UART_LCR_PARITY_NONE, UART_LCR_FIFO_1);
+
+    UART_EnableInt(UART2, UART_INT_RX);
+    UART_SetRxIntFifoLevel(UART2, UART_INT_FIFO_HALF);
+    INT_EnableIRQ(UART2_IRQn, UART_PRIORITY);
+
+    // 485 CTL
+    SYS_EnableAPBClock(APB_MASK_GPIO1);
+    GPIO_SetOutput(GPIO1, GPIO_BIT2);
+    RS485_RX();
+
+    uart_baud_delay(2,baud);
+}
+
+// 串口发送函数
+UART_TypeDef *uart_choice(uint8_t uartid)
+{
+    UART_TypeDef *USARTx;
+    switch (uartid)
+    {
+    case UART0_ID:
+        USARTx = UART0;
+        break;
+    case UART1_ID:
+        USARTx = UART1;
+        break;
+    case UART2_ID:
+        USARTx = UART2;
+        break;
+    default:
+        break;
+    }
+    return USARTx;
+}
+/*******************************************************************************
+ *uart1_msg_send 发送报文处理
+ *Input:
+ *	buf		--需要发送的数据指针
+ *	buflen	--发送的数据长度
+ *Output:
+ *	None
+ *Return:
+ *	OK/ERROR，表示执行成功和失败
+ */
+ReturnCodeTypedef UART_Send_t(uint8_t uartid, UART_TypeDef *uart, const unsigned char *p, unsigned int num)
+{
+    for (unsigned int i = 0; i < num; ++i)
+    {
+        // UART_SendCh(uart,*p);
+        // p++;
+        // delay_us(90);
+        while (UART_IsTxFifoFull(uart))
+            ;
+
+        uart->DR = *p++;
+        delay_us(uart_delay[uartid]);
+    }
+    return RET_OK;
+}
+int uart_msg_send(uint8_t uartid, const char *buf, uint32_t buflen)
+{
+    uint32_t t = 0;
+    UART_TypeDef *USARTx;
+
+    if (uartid >= UART_MAX)
+        return -1;
+    if (uartid == UART2_ID)
+        RS485_TX();
+    USARTx = uart_choice(uartid);
+    UART_Send_t(uartid, USARTx, buf, buflen);
+    if (uartid == UART2_ID)
+    {
+        RS485_RX();
+    }
+    return 0;
+}
+uint16_t uart_blocking_read(uint8_t *buf, uint8_t uart)
+{
+    uint16_t ret = 0;
+    if (uart >= UART_MAX)
+        return ret;
+    if (uart_info[uart].p_temp.p_input != uart_info[uart].p_temp.p_output)
+    {
+        while (uart_info[uart].p_temp.p_input != uart_info[uart].p_temp.p_output)
+        {
+            buf[ret] = uart_info[uart].p_temp.rcv_buf[uart_info[uart].p_temp.p_input];
+            uart_info[uart].p_temp.p_input = (uart_info[uart].p_temp.p_input + 1) % UART_RCV_TEMPBUF_LEN;
+            ret++;
+        }
+    }
+    return ret;
+}
+
+
+void uart_rcv_process(uint8_t uart)
+{
+    if (uart >= UART_MAX)
+        return;
+    if (timeout_isOut(&uart_info[uart].tt_uart))
+    {
+        // if(uart == 0)
+        //      GPIO_Toggle(GPIO3, 0xf0);
+        while (uart_info[uart].p_rcv.p_input != uart_info[uart].p_rcv.p_output)
+        {
+            uart_info[uart].p_temp.rcv_buf[uart_info[uart].p_temp.p_output] = uart_info[uart].p_rcv.rcv_buf[uart_info[uart].p_rcv.p_input];
+            uart_info[uart].p_temp.p_output = (uart_info[uart].p_temp.p_output + 1) % UART_RCV_TEMPBUF_LEN;
+            uart_info[uart].p_rcv.p_input = (uart_info[uart].p_rcv.p_input + 1) % UART_RCV_TEMPBUF_LEN;
+        }
+    }
+
+}
+// 串口接收处理函数
+void uart_rcv_handle(void)
+{
+    uint8_t i;
+    for (i = 0; i < UART_MAX; i++)
+    {
+        uart_rcv_process(i);
+    }
+}

src/agm_uart.h

@@ -0,0 +1,54 @@
+#ifndef _AGM_UART_H_
+#define _AGM_UART_H_
+
+
+#include "board.h"
+#include "timeout.h"
+
+/*端口号*/
+enum {
+	UART0_ID    = 0,
+	UART1_ID    = 1,
+	UART2_ID    = 2,
+
+
+	UART_DEBUG  = UART0_ID,
+    UART_4G     = UART1_ID,
+    UART_485    = UART2_ID,
+	UART_MAX = 3
+};
+
+#define RS485_RX() GPIO_SetLow(GPIO1, GPIO_BIT2)
+#define RS485_TX() GPIO_SetHigh(GPIO1, GPIO_BIT2)
+
+#define UART_RCV_TEMPBUF_LEN	1024
+
+#define UART_RCV_TIMEOUT    (10)  //串口接收超时时间，单位ms
+#define UART_RCV_TIMEOUT_T  (2*1000)
+
+typedef struct _uart_rcv_temp
+{
+    uint16_t p_input;
+    uint16_t p_output;
+    uint8_t rcv_buf[UART_RCV_TEMPBUF_LEN];
+}__attribute__((packed)) uart_rcv_temp_t;
+
+//串口接收
+typedef struct _uart_info
+{
+    uart_rcv_temp_t p_rcv;
+    uart_rcv_temp_t p_temp;
+    uint8_t rcv_over;
+    timeout_t tt_uart;
+    uint32_t t_time;
+}__attribute__((packed)) uart_info_t;
+extern uart_info_t uart_info[UART_MAX];
+
+extern void data_dump(const char *name, uint8_t *data, uint16_t length);
+extern void Uart0_Init(uint32_t baud);
+extern void Uart2_Init(uint32_t baud);
+extern int uart_msg_send(uint8_t uartid, const char *buf, uint32_t buflen);
+extern uint16_t uart_blocking_read(uint8_t *buf, uint8_t uart);
+extern void uart_rcv_handle(void);
+
+#endif

src/delay.c

@@ -0,0 +1,29 @@
+/*
+ * @Description: 
+ * @Version: 2.0
+ * @Author: Seven
+ * @Date: 2023-09-04 09:34:28
+ * @LastEditors: Seven
+ * @LastEditTime: 2023-09-07 16:58:33
+ */
+#include "delay.h"
+
+void delay_us(uint32_t us)
+{
+    // volatile uint32_t i,j;
+    // for(i = 0; i < us; i++)
+    // {
+    //   for(j = 0; j < 16; j++)
+    //   {
+    //     // ;
+    //   }
+    // }
+    UTIL_IdleUs(us);
+}
+
+void delay_ms(uint32_t ms)
+{
+    // delay_us(ms*1000);
+    UTIL_IdleMs(ms);
+}
+

src/delay.h

@@ -0,0 +1,16 @@
+/*
+ * @Description: 
+ * @Version: 2.0
+ * @Author: Seven
+ * @Date: 2023-08-09 17:46:14
+ * @LastEditors: Seven
+ * @LastEditTime: 2023-08-09 17:47:05
+ */
+#ifndef DELAY_H__
+#define DELAY_H__
+#include "board.h"
+
+void delay_us(uint32_t us);
+void delay_ms(uint32_t ms);
+
+#endif // !

src/i2c.c

@@ -0,0 +1,448 @@
+#include "i2c.h"
+#include "delay.h"
+//#include "uart.h"
+
+
+#define PAGE_SIZE	64
+
+//引脚初始化
+void i2c_init(void)
+{
+    SYS_EnableAPBClock(APB_MASK_GPIO2);
+	// SYS_DisableNJTRST();
+    GPIO_SetHigh(IIC_SCL_PORT,IIC_SCL_PIN);
+    GPIO_SetHigh(IIC_SDA_PORT,IIC_SDA_PIN);
+
+    GPIO_SetOutput(IIC_WP_PORT,IIC_WP_PIN);
+    GPIO_SetOutput(IIC_SCL_PORT,IIC_SCL_PIN);
+    GPIO_SetOutput(IIC_SDA_PORT,IIC_SDA_PIN);
+
+    //打开写保护
+	IIC_WRITE_PROTECT_ENABLE();
+}
+
+/***********************iic**************************/
+
+//产生IIC起始信号
+void i2c_start(void)
+{
+	SDA_OUT();
+    IIC_SDA(1);//IIC_SDA = 1;
+    IIC_SCL(1);//IIC_SCL = 1;
+    delay_us(4);
+    IIC_SDA(0);//IIC_SDA = 0;//START:when CLK is high,DATA change form high to low
+    delay_us(4);
+    IIC_SCL(0);//IIC_SCL = 0;
+}
+
+
+//产生IIC停止信号
+void i2c_stop(void)
+{
+	SDA_OUT();
+    IIC_SDA(0);//IIC_SDA = 0;
+    IIC_SCL(0);//IIC_SCL = 0;
+    delay_us(4);
+    IIC_SCL(1);//IIC_SCL = 1;
+    delay_us(4);
+    IIC_SDA(1);//IIC_SDA = 1;
+    delay_us(4);
+}
+//等待应答信号到来
+//返回值：
+//		1，接收应答失败
+//    0，接收应答成功
+uint8_t i2c_wait_ack(void)
+{
+	volatile uint8_t ucErrTime=0;
+    SDA_IN();  // SDA 配置成输入
+    // IIC_SDA(1);//IIC_SDA=1;
+    delay_us(1);
+    IIC_SCL(1);//IIC_SCL=1;
+    delay_us(1);
+    while(READ_SDA)
+    {
+        ucErrTime++;
+        if(ucErrTime>250)
+        {
+        i2c_stop();
+        return 1;
+        }
+    }
+    IIC_SCL(0);//IIC_SCL=0;
+    return 0;
+
+}
+//产生ACK应答
+void IIC_Ack(void)
+{
+	IIC_SCL(0);//IIC_SCL = 0;
+    SDA_OUT();
+    IIC_SDA(0);//IIC_SDA = 0;
+    delay_us(4);
+    IIC_SCL(1);//IIC_SCL = 1;
+    delay_us(2);
+    IIC_SCL(0);//IIC_SCL = 0;
+}
+//不产生ACK应答
+void IIC_NAck(void)
+{
+	IIC_SCL(0);//IIC_SCL = 0;
+    SDA_OUT();
+    IIC_SDA(1);//IIC_SDA = 1;
+    delay_us(4);
+    IIC_SCL(1);//IIC_SCL = 1;
+    delay_us(2);
+    IIC_SCL(0);//IIC_SCL = 0;
+}
+//IIC发送一个字节
+//返回从机有无应答
+//1，有应答
+//0，无应答
+void i2c_send_byte(uint8_t txd)
+{
+	uint8_t t;
+    SDA_OUT();
+	IIC_SCL(0);//IIC_SCL=0;// 电平置低，开始传输数据
+	for(t=0;t<8;t++)
+	{
+		// IIC_SDA=(txd&0x80)>>7;
+		if((txd&0x80)>>7) IIC_SDA(1);
+		else IIC_SDA(0);
+		txd<<=1;
+		delay_us(4);   //
+		IIC_SCL(1);//IIC_SCL=1;
+		delay_us(2);
+		IIC_SCL(0);//IIC_SCL=0;
+        if(t==7)
+            SDA_IN();
+		delay_us(2);
+	}
+}
+//读1个字节，ack=1时，发送ACK，ack=0，发送nACK
+uint8_t i2c_read_byte(uint8_t ack)
+{
+	uint8_t i,receive=0;
+    SDA_IN();//SDA设置为输入
+    for(i=0;i<8;i++ )
+    {
+        IIC_SCL(0);//IIC_SCL=0;
+        delay_us(4);
+        IIC_SCL(1);//IIC_SCL=1;
+        receive<<=1;
+        if(READ_SDA)receive++;
+        delay_us(1);
+    }
+    if(!ack)
+        IIC_NAck();//发送nACK
+    else
+        IIC_Ack(); //发送ACK
+    return receive;
+}
+
+
+/***********************以上为IIC驱动**************************/
+
+
+
+
+
+
+
+
+
+
+
+
+/***********************iic**************************/
+//在AT24CXX指定地址读出一个数据
+//ReadAddr:开始读数的地址
+//返回值  :读到的数据
+uint8_t at24cxx_readOneByte(uint32_t ReadAddr)
+{
+	uint8_t temp;
+	uint8_t addrH,addrL;
+
+	addrH=ReadAddr>>8;
+	addrL=ReadAddr&0xff;
+
+	i2c_start();
+
+	i2c_send_byte(0xa0);
+
+	i2c_wait_ack();
+	i2c_send_byte(addrH);   //发送高地址
+	i2c_wait_ack();
+   	i2c_send_byte(addrL);   //发送低地址
+	i2c_wait_ack();
+	i2c_start();
+	i2c_send_byte(0xa1);         //进入接收模式
+
+	i2c_wait_ack();
+	temp=	i2c_read_byte(0);
+	i2c_stop();//产生一个停止条件
+
+	delay_us(4);
+	return temp;
+}
+//在AT24CXX指定地址写入一个数据
+//WriteAddr  :写入数据的目的地址
+//DataToWrite:要写入的数据
+void at24cxx_writeOneByte(uint32_t WriteAddr,uint8_t DataToWrite)
+{
+	uint8_t addrH,addrL;
+
+	addrH=WriteAddr>>8;
+	addrL=WriteAddr&0xff;
+
+	i2c_start();
+
+	i2c_send_byte(0xa0);
+
+	i2c_wait_ack();
+	i2c_send_byte(addrH);   //发送高地址
+	i2c_wait_ack();
+	i2c_send_byte(addrL);   //发送低地址
+	i2c_wait_ack();
+	i2c_send_byte(DataToWrite);     //发送字节
+	i2c_wait_ack();
+	i2c_stop();//产生一个停止条件
+
+	delay_ms(10);//两次写操作，必须加间隔，否则写不进去
+}
+//在AT24CXX里面的指定地址开始读出指定个数的数据
+//ReadAddr :开始读出的地址 对24c02为0~255
+//pBuffer  :数据数组首地址
+//NumToRead:要读出数据的个数
+void at24cxx_read(uint32_t ReadAddr,uint8_t *pBuffer,uint16_t NumToRead)
+{
+	uint8_t addrH,addrL;
+	uint16_t lentmp,lentow,lens;
+	uint8_t tmp;
+
+	if(NumToRead==0)
+		return;
+
+
+//	I2C_init();
+//	OSTimeDlyHMSM(0, 0, 0, 40, OS_OPT_TIME_DLY, &err);
+//	delay_ms(1);//40
+	// delay_us(10);
+	lentmp=NumToRead;
+	while(lentmp)
+	{
+		tmp=ReadAddr%PAGE_SIZE;
+		tmp=PAGE_SIZE-tmp;
+		if(tmp>=lentmp)//当页剩余空间大于要写入的长度
+		{
+			lentow=lentmp;
+		}
+		else
+		{
+			lentow=tmp;//写入长度只能是剩余空间长度
+		}
+		lentmp=lentmp-lentow;//计算要在下一页写入的长度
+		lens=lentow;
+		addrH=ReadAddr>>8;
+		addrL=ReadAddr&0xff;
+
+		i2c_start();
+
+		i2c_send_byte(0xa0);//写
+		i2c_wait_ack();
+
+		i2c_send_byte(addrH);   //发送高地址
+		i2c_wait_ack();
+	   	i2c_send_byte(addrL);   //发送低地址
+		i2c_wait_ack();
+
+		delay_us(4);
+		i2c_start();
+		i2c_send_byte(0xa1);  //读       //进入接收模式
+		i2c_wait_ack();
+
+		while(lentow)
+		{
+			*pBuffer=i2c_read_byte(1);
+			pBuffer++;
+			//ReadAddr++;
+			lentow--;
+
+		}
+		i2c_read_byte(0);
+		i2c_stop();//产生一个停止条件
+
+		delay_us(4);
+		//printf("at24 read %d %d\r\n", ReadAddr, lens);
+		ReadAddr=ReadAddr+lens;//下一页的地址
+	}
+	//打开写保护
+//	IIC_WRITE_PROTECT_ENABLE();
+}
+//在AT24CXX里面的指定地址开始写入指定个数的数据
+//WriteAddr :开始写入的地址 对24c02为0~255
+//pBuffer   :数据数组首地址
+//NumToWrite:要写入数据的个数
+// 每128bytes为一个page,写操作不能跨页
+void at24cxx_write(uint32_t WriteAddr,uint8_t *pBuffer,uint16_t NumToWrite)
+{
+	uint8_t addrH,addrL;
+	uint16_t lentmp,lentow,lens;
+	uint8_t tmp;
+	if(NumToWrite==0)
+		return;
+
+
+
+	IIC_WRITE_PROTECT_DISABLE();//关闭写保护
+//	delay_ms(1);//10
+	delay_us(10);
+
+	lentmp=NumToWrite;
+	while(lentmp)
+	{
+		tmp=WriteAddr%PAGE_SIZE;
+		tmp=PAGE_SIZE-tmp;
+		if(tmp>=lentmp)//当页剩余空间大于要写入的长度
+		{
+			lentow=lentmp;
+		}
+		else
+		{
+			lentow=tmp;//写入长度只能是剩余空间长度
+		}
+		lentmp=lentmp-lentow;//计算要在下一页写入的长度
+		lens=lentow;
+
+		addrH=WriteAddr>>8;
+		addrL=WriteAddr&0xff;
+
+		i2c_start();
+
+		i2c_send_byte(0xa0);
+
+		i2c_wait_ack();
+		i2c_send_byte(addrH);   //发送高地址
+		i2c_wait_ack();
+		i2c_send_byte(addrL);   //发送低地址
+		i2c_wait_ack();
+
+		while(lentow--)
+		{
+			i2c_send_byte(*pBuffer);
+			i2c_wait_ack();
+			pBuffer++;
+		}
+		i2c_stop();//产生一个停止条件
+		// if(lentmp)//需要写下一页
+			delay_ms(6);
+		//printf("at24 write %d %d %d, %d\r\n", WriteAddr, lens, addrH, addrL);
+		WriteAddr=WriteAddr+lens;//下一页的地址
+	}
+
+//	delay_ms(10);//两次写操作，必须加间隔，否则写不进去，最小5ms
+	//打开写保护
+	IIC_WRITE_PROTECT_ENABLE();
+}
+void at24cxx_clr(uint32_t WriteAddr,uint32_t NumToWrite)
+{
+	uint8_t addrH,addrL;
+	uint16_t lentmp,lentow,lens;
+	uint8_t tmp;
+
+	//关闭写保护
+	IIC_WRITE_PROTECT_DISABLE();
+
+	lentmp=NumToWrite;
+	while(lentmp)
+	{
+		tmp=WriteAddr%PAGE_SIZE;
+		tmp=PAGE_SIZE-tmp;
+		if(tmp>=lentmp)
+		{
+			lentow=lentmp;
+		}
+		else
+		{
+			lentow=tmp;
+		}
+		lentmp=lentmp-lentow;
+		lens=lentow;
+
+		addrH=WriteAddr>>8;
+		addrL=WriteAddr&0xff;
+
+		i2c_start();
+
+		i2c_send_byte(0xa0);
+
+		i2c_wait_ack();
+		i2c_send_byte(addrH);   //发送高地址
+		i2c_wait_ack();
+		i2c_send_byte(addrL);   //发送低地址
+		i2c_wait_ack();
+
+		while(lentow--)
+		{
+			i2c_send_byte(0xff);
+			i2c_wait_ack();
+		}
+		i2c_stop();//产生一个停止条件
+		delay_ms(10);
+		WriteAddr=WriteAddr+lens;
+	}
+	//打开写保护
+	IIC_WRITE_PROTECT_ENABLE();
+	delay_ms(10);
+}
+//----------------------EEPROM---------------------------//
+//--------------------------------------------------------EEPROM DATA
+
+/*********************************************END OF FILE**********************/
+#define I2C_DATA_LEN	512
+uint8_t I2c_Buf_Write[I2C_DATA_LEN], I2c_Buf_Read[I2C_DATA_LEN];
+/**
+* @brief I2C(AT24C02)读写测试
+* @param 无
+* @retval 正常返回 1 ，不正常返回 0
+*/
+/*
+写1个字节用时336us
+写16个字节用时3.17ms
+写64个字节用时9.4ms
+读1个字节用时450us
+读16个字节用时2.12ms
+读64个字节用时6.44ms
+*/
+uint8_t I2C_Test(void)
+{
+	uint16_t i;
+
+	i2c_init();
+
+	EEPROM_INFO("\r\nI2C(AT24C128)字节读写测试\r\n");
+	memset(I2c_Buf_Write, 0, I2C_DATA_LEN);
+	memset(I2c_Buf_Read, 0, I2C_DATA_LEN);
+
+	EEPROM_INFO("\r\nI2C(AT24C128)连续地址读写测试\r\n");
+	// GPIO_SetLow(GPIO1,GPIO_BIT1);
+	memset(I2c_Buf_Write, 0, I2C_DATA_LEN);
+	memset(I2c_Buf_Read, 0, I2C_DATA_LEN);
+	for ( i=0; i< I2C_DATA_LEN; i++ ) //填充缓冲
+	{
+		I2c_Buf_Write[i] = i+8;
+	}
+
+	at24cxx_write(512, I2c_Buf_Write, 64);
+
+	delay_ms(10);
+	// GPIO_SetHigh(GPIO1,GPIO_BIT1);
+	at24cxx_read(512, I2c_Buf_Read, 64);
+	// GPIO_SetLow(GPIO1,GPIO_BIT1);
+	//data_dump("I2C Write", I2c_Buf_Write, I2C_DATA_LEN);
+	//data_dump("I2C Read", I2c_Buf_Read, I2C_DATA_LEN);
+
+	EEPROM_INFO("\r\nI2C(AT24C128)读写测试成功\r\n");
+
+	return 1;
+}

src/i2c.h

@@ -0,0 +1,48 @@
+#ifndef AT24C128_H__
+#define AT24C128_H__
+
+#include "board.h"
+
+
+#define IIC_WP_PORT     GPIO2
+#define IIC_WP_PIN		GPIO_BIT0
+
+#define IIC_SDA_PORT    GPIO2
+#define IIC_SDA_PIN		GPIO_BIT2
+
+#define IIC_SCL_PORT	GPIO2
+#define IIC_SCL_PIN     GPIO_BIT1
+
+#define SDA_IN()    GPIO_SetInput(IIC_SDA_PORT,IIC_SDA_PIN)
+#define SDA_OUT()   {GPIO_SetOutput(IIC_SDA_PORT,IIC_SDA_PIN);}
+
+#define IIC_SCL(n)  (n?GPIO_SetHigh(IIC_SCL_PORT,IIC_SCL_PIN) : GPIO_SetLow(IIC_SCL_PORT,IIC_SCL_PIN))
+#define IIC_SDA(n)  (n?GPIO_SetHigh(IIC_SDA_PORT,IIC_SDA_PIN) : GPIO_SetLow(IIC_SDA_PORT,IIC_SDA_PIN))
+
+#define READ_SDA GPIO_GetValue(IIC_SDA_PORT, IIC_SDA_PIN)
+
+//写保护,低电平关闭，可以写入；高电平打开，不能写入
+#define IIC_WRITE_PROTECT_ENABLE()   {GPIO_SetHigh(IIC_WP_PORT, IIC_WP_PIN);}
+#define IIC_WRITE_PROTECT_DISABLE()  {GPIO_SetLow(IIC_WP_PORT, IIC_WP_PIN);}
+
+
+extern void i2c_init(void);
+extern void i2c_start(void);
+extern void i2c_stop(void);
+extern uint8_t i2c_wait_ack(void);
+extern void IIC_Ack(void);
+extern void IIC_NAck(void);
+extern void i2c_send_byte(uint8_t txd);
+extern uint8_t i2c_read_byte(uint8_t ack);
+
+extern uint8_t at24cxx_readOneByte(uint32_t ReadAddr);
+extern void at24cxx_writeOneByte(uint32_t WriteAddr,uint8_t DataToWrite);
+extern void at24cxx_read(uint32_t ReadAddr,uint8_t *pBuffer,uint16_t NumToRead);
+extern void at24cxx_write(uint32_t WriteAddr,uint8_t *pBuffer,uint16_t NumToWrite);
+extern void at24cxx_clr(uint32_t WriteAddr,uint32_t NumToWrite);
+
+extern uint8_t I2C_Test(void);
+
+#define EEPROM_INFO(fmt,arg...)           printf("<<-EEPROM-INFO->> "fmt"\n",##arg)
+
+#endif // !

src/main.c

@@ -0,0 +1,30 @@
+#include "main.h"
+
+#include "agm_board.h"
+#include "uart_pt.h"
+#include "public.h"
+
+
+void main(void)
+{
+    agm_board_init();
+    device_board_init();
+    power_on_read();
+    printf("\n***************************************************\n");
+    printf("pt begin\n");
+    printf("\nInit done. CLK: %.3fMHz, RTC: %dHz \n", SYS_GetSysClkFreq()/(double)1e6, BOARD_RTC_FREQUENCY);
+
+
+    g_ptTest.bTestStart = PT_ON;
+    timeout_setValue(&g_ptTest.tt_pt_time,PT_TIME,1);
+
+    while (1)
+    {
+        uart_rcv_handle();
+        pt_cmd_task();
+    }
+
+}
+
+
+

src/main.h

@@ -0,0 +1,6 @@
+#ifndef _MAIN_H_
+#define _MAIN_H_
+
+#include "board.h"
+
+#endif

src/public.c

@@ -0,0 +1,217 @@
+#include "public.h"
+#include "agm_config.h"
+#include "i2c.h"
+
+device_fixed_info_t device_fixed_info;
+device_info_t device_info;
+device_version_info_t device_version_info;
+MqttIdPort mqttidport;
+uint8_t last_reset_flag;
+//字符串转十六进制数
+uint32_t strtohex(char *data, uint8_t len)
+{
+	uint8_t i = 0;;
+	uint32_t p_data = 0;
+	uint8_t temp;
+	for(i = 0; i < len; i++)
+	{
+		temp = HexToChar(data[i]);
+		if(temp == 0xff)
+			break;
+		p_data = (p_data<<4)|temp;
+	}
+	return p_data;
+}
+
+unsigned char HexToChar(unsigned char bChar)
+{
+	if((bChar>=0x30)&&(bChar<=0x39))
+	{
+		bChar -= 0x30;
+	}
+	else if((bChar>=0x41)&&(bChar<=0x46)) // Capital
+	{
+		bChar -= 0x37;
+	}
+	else if((bChar>=0x61)&&(bChar<=0x66)) //littlecase
+	{
+		bChar -= 0x57;
+	}
+	else
+	{
+		bChar = 0xff;
+	}
+	return bChar;
+}
+
+//ascii转十六进制
+int asciitohex(char *data, uint8_t *out_data, int len)
+{
+	int i,slen=0;
+	uint8_t temp1,temp2;
+	for(i = 0; i < len; i+=2)
+	{
+		temp1 = HexToChar(data[i]);
+		temp2 = HexToChar(data[i+1]);
+		out_data[slen] = (temp1<<4) | temp2;
+		slen++;
+	}
+	return slen;
+}
+
+
+//更新设备产测信息
+void device_info_update(void)
+{
+	at24cxx_write(DEVICE_PUBLIC_INFO_ADDR,(uint8_t *)&device_info,sizeof(device_info));
+}
+//读取eeprom中的设备产测信息
+void device_info_get(void)
+{
+	// memset(&device_info,0,sizeof(device_info_t));
+	at24cxx_read(DEVICE_PUBLIC_INFO_ADDR,(uint8_t *)&device_info,sizeof(device_info_t));
+}
+
+//更新mqtt信息
+void mqtt_info_update(void)
+{
+	at24cxx_write(FRAM_MQTT_MSG,(uint8_t *)&mqttidport,sizeof(MqttIdPort));
+}
+
+//读mqtt信息
+void mqtt_info_read(void)
+{
+	at24cxx_read(FRAM_MQTT_MSG,(uint8_t *)&mqttidport,sizeof(MqttIdPort));
+	//字符串加尾0
+	mqttidport.ip[IP_LEN-1] = '\0';
+	mqttidport.port[PORT_LEN-1] = '\0';
+	mqttidport.admin[ADMIN_LEN-1] = '\0';
+	mqttidport.password[PASSWORD_LEN-1] = '\0';
+}
+uint32_t mcuID[4];
+uint32_t mcu_type_ID = 0;
+uint32_t Reset_cnt = 0;
+
+//读取UUID
+void get_mcu_uuid(void)
+{
+	FLASH_Unlock();
+	FLASH_GetUniqueID(mcuID);
+	FLASH_Lock();
+	memcpy(device_fixed_info.MCU_UUID,(uint8_t *)mcuID,16);
+	// data_dump("uuid",device_fixed_info.MCU_UUID,16);
+}
+
+//读mcu的类型
+void get_mcu_TypeIdcode(void)
+{
+	uint32_t mcutypeID=0;
+    mcutypeID = *(volatile uint32_t*)(AG32VF407_DEVICE_ID_ADDR);
+	// printf("chip id=%08x\n",mcutypeID);
+
+	mcu_type_ID  = mcutypeID;
+}
+
+//读取复位类型
+uint8_t reset_flag_get(void)
+{
+	uint8_t RestFlag = 0;
+    if(SYS_IsActiveResetFlag_LPWR())
+    {
+        RestFlag |= 1<<5;
+    }
+    if(SYS_IsActiveResetFlag_WDOG())
+    {
+        RestFlag |= 1<<4;
+    }
+    if(SYS_IsActiveResetFlag_IWDG())
+    {
+        RestFlag |= 1<<3;
+    }
+    if(SYS_IsActiveResetFlag_SFT())
+    {
+        RestFlag |= 1<<2;
+    }
+    if(SYS_IsActiveResetFlag_POR())
+    {
+        RestFlag |= 1<<1;
+    }
+    if(SYS_IsActiveResetFlag_PIN())
+    {
+        RestFlag |= 1<<0;
+    }
+    if(SYS_IsActiveResetFlag_EXT())
+    {
+        RestFlag |= 1<<6;
+    }
+    SYS_ClearResetFlags();
+    printf("restflag=%02x\n",RestFlag);
+	return RestFlag;
+}
+//eeprom上电初始化处理
+void eeprom_init_handle(void)
+{
+	uint8_t eeprom_buf[10]={0};
+	//读产测设置的信息
+	at24cxx_read(DEVICE_PUBLIC_INFO_ADDR,(uint8_t *)&device_info,sizeof(device_info_t));
+	//读设备版本信息
+	at24cxx_read(DEVICE_VERSION_INFO_ADDR,(uint8_t *)&device_version_info,sizeof(device_version_info_t));
+	//读复位次数
+	at24cxx_read(DEVICE_RESET_ADDR,(uint8_t *)&Reset_cnt,4);
+
+	//读Lora参数
+	at24cxx_read(LORA_ADDR,(uint8_t *)eeprom_buf,2);
+
+	if(eeprom_buf[0] != (uint8_t)~eeprom_buf[1])
+	{
+		eeprom_buf[0] = 0;
+		eeprom_buf[1] = ~eeprom_buf[0];
+		at24cxx_write(LORA_ADDR,(uint8_t *)eeprom_buf,2);
+	}
+	else if(eeprom_buf[0] > LORA_GROUP_NUM-1)
+	{
+		eeprom_buf[0] = 0;
+		eeprom_buf[1] = ~eeprom_buf[0];
+		at24cxx_write(LORA_ADDR,(uint8_t *)eeprom_buf,2);
+	}
+}
+//设备固定信息初始化
+void device_fixed_info_init(void)
+{
+	device_fixed_info.Soft_ver_app    =  device_version_info.APP1_ver;//;
+	device_fixed_info.Soft_ver_boot   = device_version_info.BOOT_ver;
+	device_fixed_info.MCU_Type_ID     = mcu_type_ID;
+	device_fixed_info.Reset_total_cnt = Reset_cnt;
+	device_fixed_info.Last_reset_flag = last_reset_flag;
+//	device_fixed_info.Encrypt         = Encrypt;
+	memcpy(device_fixed_info.MCU_UUID,(uint8_t *)mcuID,16);
+}
+
+//设备信息初始化处理
+void device_info_init_handle(void)
+{
+
+	//判断pt版本是否正确
+	if(device_version_info.PT_ver != SOFTWARE_VERSION_APP)
+	{
+		device_version_info.PT_ver = SOFTWARE_VERSION_APP;
+		//存储到eeprom中
+		at24cxx_write(DEVICE_VERSION_INFO_ADDR+4,(uint8_t *)&device_version_info.PT_ver,4);
+	}
+
+	//设置设备的固定信息
+	device_fixed_info_init();
+
+}
+
+
+//设备上电后信息读取
+void power_on_read(void)
+{
+    get_mcu_uuid();//读取UUID
+    get_mcu_TypeIdcode();//读mcu的类型
+    // Read_Updata_State();//读升级标志
+    last_reset_flag = reset_flag_get();//读取复位类型
+    eeprom_init_handle();//eeprom上电初始化处理
+    device_info_init_handle();//设备信息初始化处理
+}

src/public.h

@@ -0,0 +1,84 @@
+#ifndef _PUBLIC_H_
+#define _PUBLIC_H_
+
+
+#include "board.h"
+
+//设备固定信息，不需在app中写eeprom
+typedef struct _device_fixed_info
+{
+	uint32_t Soft_ver_app;       	//app版本号
+	uint32_t Soft_ver_boot;      	//bootloader版本号
+	uint8_t MCU_UUID[16];        	//MCU的UUID
+	uint32_t MCU_Type_ID;        	//MCU的芯片类型
+	uint8_t Imei[15];				//imei
+	uint32_t Reset_total_cnt;    	//复位总次数
+	uint8_t Last_reset_flag;     	//上次复位类型
+	uint8_t Encrypt;             	//明密文状态
+	uint8_t Work_State;          	//当前工作状态
+	uint32_t Voltage;            	//电压
+	uint32_t Temperature;        	//温度
+	uint8_t lora_para_group;     	//lora参数选择
+	uint8_t master_updata_start; 	//主设备开始升级标志
+	uint8_t slave_uploade_start; 	//从设备主动上报标志
+	uint8_t reset_flag;				//采集器复位标记
+	uint8_t xsp_update_start;		//显示屏开始升级标记
+
+}device_fixed_info_t;
+extern device_fixed_info_t device_fixed_info;
+
+//公共信息
+typedef struct _device_c_info_t
+{
+    uint16_t eeprom_first_flag;					//是否第一次上电
+    uint8_t	eeprom_ver;							//eeprom版本
+    uint8_t config_flag;						//是否配置的标记
+    uint32_t device_sn;            				//设备sn
+    uint16_t device_type;          				//设备类型
+    uint16_t manufactures;         				//产品制造商
+    uint16_t batch_number;         				//批次号
+    uint32_t production_data;      				//出厂日期
+    uint8_t  pcb_ver;              				//PCB版本
+}__attribute__((packed)) device_info_t;
+extern device_info_t device_info;
+
+//单片机信息
+typedef struct _device_version_info
+{
+	uint32_t BOOT_ver;					        //bootloader版本
+	uint32_t PT_ver;							//产测版本
+	uint32_t APP1_ver;							//app1版本
+	uint32_t APP2_ver;							//app2版本
+	uint32_t APP3_ver;							//app3版本
+    uint32_t FPGA_ver;                          //fpga版本
+}__attribute__((packed)) device_version_info_t;
+extern device_version_info_t device_version_info;
+
+#define PORT_LEN        8
+#define IP_LEN          32
+#define ADMIN_LEN       16
+#define PASSWORD_LEN    24
+/* mqtt IP地址 端口号*/
+typedef struct _MQTT_IP_PORT_{
+    uint8_t flag;                               //是否写入过标记
+    char port[PORT_LEN];                        //端口号
+    char ip[IP_LEN];                            //IP地址
+    char admin[ADMIN_LEN];                      //用户名
+    char password[PASSWORD_LEN];                //密码
+}__attribute__((packed)) MqttIdPort;
+extern MqttIdPort mqttidport;
+
+
+extern uint32_t strtohex(char *data, uint8_t len);
+extern unsigned char HexToChar(unsigned char bChar);
+extern int asciitohex(char *data, uint8_t *out_data, int len);
+
+extern void device_info_update(void);
+extern void device_info_get(void);
+extern void mqtt_info_update(void);
+extern void mqtt_info_read(void);
+
+extern void power_on_read(void);
+
+
+#endif

src/rtc.c

@@ -0,0 +1,116 @@
+#include "rtc.h"
+
+
+_calendar_obj calendar;	//日历结构体
+
+//rtc初始化
+void rtc_init(void)
+{
+    uint32_t times;
+    RTC_Init(board_rtc_source());
+    RTC_SetPrescaler(32768);
+    if(0x5AA5 != (RTC_ReadBackupRegister(0)))
+    {
+        times = RTC_GetEpochSeconds(2023, 8, 21, 11, 01, 00);
+        RTC_SetCounter(times);
+        RTC_WriteBackupRegister(0,0x5AA5);
+    }
+	RTC_Get();
+}
+
+//rtc时间显示
+#define  IS_LEAP_YEAR_m(year) (!((year) % 4) && (((year) % 100) || !((year) % 400)))
+const uint8_t mon_table[12]={31,28,31,30,31,30,31,31,30,31,30,31};
+//得到当前的时间
+//返回值:0,成功;其他:错误代码.
+uint8_t RTC_Get(void)
+{
+    // static uint16_t daycnt = 0;
+    // uint32_t timecount;
+    // uint32_t temp  = 0;
+    // uint16_t temp1 = 0;
+
+	time_t now;
+	now=RTC_GetCounter();
+	struct tm *tm = gmtime(&now);
+	printf("rtc time:%d:%02d:%02d-%02d:%02d:%02d\n", tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday, tm->tm_hour, tm->tm_min, tm->tm_sec);
+
+#if 0
+    timecount=RTC_GetCounter();
+    temp=timecount/86400;   //得到天数(秒钟数对应的)
+    if(timecount<86400)//不到1天
+    {
+        //从1970年1月1日开始
+        calendar.w_year  = 1970;
+        calendar.w_month = 1;
+        calendar.w_date  = 1;
+    }
+	if(daycnt!=temp)  //超过一天了
+	{
+		daycnt = temp;
+		temp1  = 1970;  //从1970年开始
+		while(temp>=365)  //计算出来的天数大于等于一年的天数
+		{
+			if(IS_LEAP_YEAR_m(temp1))  //是闰年
+			{
+				if(temp>=366)
+				{
+					temp -= 366;  //闰年的秒钟数
+				}
+				else
+				{
+					temp1++;
+					break;
+				}
+			}
+			else temp -= 365;  //平年
+			temp1++;
+		}
+		calendar.w_year = temp1;  //得到年份
+		temp1           = 0;
+		while(temp>=28)  //超过了一个月
+		{
+			if(IS_LEAP_YEAR_m(calendar.w_year)&&temp1==1)  //当年是不是闰年/2月份
+			{
+				if(temp>=29)  //如果天数超过29天
+				{
+					temp -= 29;  //闰年的秒钟数
+				}
+				else break;  //小于29天，不到闰年3月，直接跳出。
+			}
+			else
+			{
+				if(temp>=mon_table[temp1])
+				{
+					temp -= mon_table[temp1];  //平年
+				}
+				else break;
+			}
+			temp1++;
+		}
+		calendar.w_month = temp1+1;  //得到月份
+		calendar.w_date  = temp+1;   //得到日期
+	}
+
+	temp         =timecount%86400;  //得到秒钟数
+	calendar.hour=temp/3600;        //小时
+	calendar.min =(temp%3600)/60;   //分钟
+	calendar.sec =(temp%3600)%60;   //秒钟
+	                                // calendar.week=RTC_Get_Week(calendar.w_year,calendar.w_month,calendar.w_date);//获取星期
+
+	 printf("timecount:%u, current time %d-%d-%d %02d:%02d:%02d\r\n", timecount,
+		calendar.w_year,calendar.w_month,calendar.w_date,
+		calendar.hour, calendar.min, calendar.sec);
+#endif
+	return 0;
+}
+
+//设置时钟
+//以1970年1月1日为基准
+//1970~2099年为合法年份
+//参数：时间戳
+void set_time(uint32_t seccount)
+{
+	RTC_SetCounter(seccount);		//设置RTC计数器的值
+}
+

src/rtc.h

@@ -0,0 +1,44 @@
+/*
+ * @Description:
+ * @Version: 2.0
+ * @Author: Seven
+ * @Date: 2023-08-21 10:10:30
+ * @LastEditors: Seven
+ * @LastEditTime: 2023-09-19 17:47:28
+ */
+#ifndef __RTC_H__
+#define __RTC_H__
+#include "board.h"
+
+
+
+enum BKP_t {
+	BKP_DATA_0,
+    BKP_DATA_1,
+    BKP_DATA_2,
+    BKP_DATA_3,
+    BKP_DATA_4,
+    BKP_DATA_5,
+    BKP_DATA_6,
+    BKP_DATA_7,
+};
+
+
+//时间结构体
+typedef struct
+{
+	uint32_t hour;
+	uint32_t min;
+	uint32_t sec;
+	//公历日月年周
+	uint32_t w_year;
+	uint32_t  w_month;
+	uint32_t  w_date;
+	uint32_t  week;
+}_calendar_obj;
+extern _calendar_obj calendar;	//日历结构体
+
+extern void rtc_init(void);
+uint8_t RTC_Get(void);
+extern void set_time(uint32_t seccount);
+#endif // !

src/timeout.c

@@ -0,0 +1,78 @@
+#include "timeout.h"
+#include "agm_config.h"
+
+
+//获取当前时间
+uint64_t get_real_time(void)
+{
+	// return UTIL_GetMcycle();
+	return Systickcount;
+}
+
+/**
+  * @brief 设置定时器
+  * @par param[timeout_t] *tt
+  * @par param[uint32_t] val，延时ms
+  * @par param[uint8_t] flg。0:不使能；1单次使能；0xFF连续使能
+  */
+void timeout_setValue(timeout_t *tt,uint32_t val,uint8_t flg){
+	tt->flag = flg;
+	tt->count = get_real_time();
+	tt->timeout = val;//UTIL_UsToMcycle(val);
+};
+
+/**
+  * @brief 启动定时器
+  * @par param[timeout_t] *tt
+  * @par param[uint8_t] flg。0:不使能；1单次使能；0xFF连续使能
+  */
+
+/**
+ * @brief 启动定时器
+ * @param  tt               定时器指针
+ * @param  flg              是否开启
+ */
+void timeout_start(timeout_t *tt,uint8_t flg){
+	tt->flag = flg;
+	if(flg){
+		tt->count = get_real_time();
+	}
+};
+
+
+
+/**
+ * @brief 停止定时器
+ * @param  tt               定时器指针
+ */
+void timeout_stop(timeout_t *tt){
+	tt->flag = 0;
+};
+
+
+/**
+ * @brief 返回定时器是否超时
+ * @param  tt               定时器指针
+ * @return uint8_t 1:超时，0:未超时
+ */
+
+
+uint8_t timeout_isOut(timeout_t *tt){
+	volatile uint64_t time;
+	if(tt->flag){
+		time = get_real_time();
+		if((time - tt->count) >= tt->timeout){
+			tt->count = time;
+			if(tt->flag == 1){
+				tt->flag = 0;
+			}
+			return 1;
+		}
+		else{
+			return 0;
+		}
+	}
+	else{
+		return 0;
+	}
+};

src/timeout.h

@@ -0,0 +1,20 @@
+#ifndef _TIMEOUT_H_
+#define _TIMEOUT_H_
+
+
+#include "board.h"
+
+
+typedef struct timeout_
+{
+	uint8_t flag;
+	uint64_t count;
+	uint64_t timeout;
+}__attribute__((packed)) timeout_t;
+
+extern void timeout_setValue(timeout_t *tt,uint32_t val,uint8_t flg);
+extern void timeout_start(timeout_t *tt,uint8_t flg);
+extern void timeout_stop(timeout_t *tt);
+extern uint8_t timeout_isOut(timeout_t *tt);
+
+#endif

src/uart_pt.c

@@ -0,0 +1,447 @@
+/*
+ * @Description:
+ * @Version: 2.0
+ * @Author: Seven
+ * @Date: 2023-09-01 10:24:59
+ * @LastEditors: Seven
+ * @LastEditTime: 2023-10-13 13:28:23
+ */
+#include "uart_pt.h"
+#include "delay.h"
+#include "agm_uart.h"
+#include "i2c.h"
+#include "public.h"
+#include "agm_config.h"
+
+uint8_t rcv_buf[UART_RCV_TEMPBUF_LEN];
+uint16_t rcv_size;
+
+PtTest g_ptTest;
+
+/*------------------------------------------------
+ *  清空EEPROM的存储空间
+ * ------------------------------------------------*/
+void eeprom_earse(void)
+{
+    uint8_t buff[64] = {0};
+    int i = 0;
+	memset(buff,0,sizeof(buff));
+    for(i=0;i<256;i++){
+        at24cxx_write(i*64,buff,sizeof(buff));
+    }
+//    fram_write_eeprom_powerUpFlag();
+}
+
+char sendbuff[320] = {0};
+char pt_rtbuf[320] = {0};
+void pt_return_handle(uint8_t uartid, char *data)
+{
+    memset(pt_rtbuf,0,sizeof(pt_rtbuf));
+    strcpy(pt_rtbuf,data);
+	uart_msg_send(uartid,(uint8_t *)pt_rtbuf,strlen(pt_rtbuf));
+
+    timeout_setValue(&g_ptTest.tt_pt_time,PT_TIME,1);//打开产测定时
+}
+
+char Send_Buf_Char[320];
+void gw_net_send_02(char *data,  uint16_t len, uint16_t *llen)
+{
+    int i;
+    //char send_buf[320];
+    char value = 0;
+    int send_len=0;
+    const uint16_t len1 = len;
+
+    memset(Send_Buf_Char,0,sizeof(Send_Buf_Char));
+    for(i = 0;i < len1;i++) {
+        value = data[i];
+        send_len += snprintf((char *)Send_Buf_Char + send_len, sizeof(Send_Buf_Char), "%02x", value);
+    }
+    *llen = send_len;
+}
+
+/*
+参数1：分隔符
+参数2：字符串
+参数3：分割后的字符串存放的位置
+参数4：预计需要分割的个数
+*/
+int at_get_words(char chop,char *srcStr, char **word, int size)
+{
+    int index = 0;
+    int i = 0;
+    char *str = srcStr;
+    while (*(str + i) != '\0')
+    {
+        if (*(str + i) == chop)
+        {
+            word[index] = str;
+            word[index++][i] = '\0';
+            str = (str + i + 1);
+            i = -1;
+        }
+        if (*(str + i) == '\r')
+        {
+            word[index] = str;
+            word[index++][i] = '\0';
+            str = (str + i);
+            i = 0;
+            break;
+        }
+        if (index >= size)
+        {
+            return index;
+        }
+        i++;
+    }
+    if (strlen(str) > 0)
+    {
+        word[index++] = str;
+    }
+    return index;
+}
+
+#if 1
+void uart_cmd_task(uint8_t uartid, char *data, uint16_t len)
+{
+    char    * p_data = NULL;
+    char    * p_str = NULL;
+    int     i        = 0, j     = 0, flag = 0;
+    int     n        = 0, len1  = 0;
+    uint8_t temp1    = 0, temp2 = 0;
+	uint16_t len2;
+	uint32_t addr,len11;
+	uint32_t device_sn;            //设备sn
+	uint32_t device_type;          //设备类型
+	uint32_t manufactures;         //产品制造商
+	uint32_t batch_number;         //批次号
+	uint32_t production_data;      //出厂日期
+	uint32_t pcb_ver;              //PCB版本
+    uint16_t eeprom_first = 0;
+    char *pbuf[15]={NULL};
+
+    char tempbuff[128] = {0};
+    char type[4]       = {0};
+    // char ssn[11]       = {0};
+    // char pcbVr[3]      = {0};
+    // char bn[5]         = {0};
+    // char mfrs[5]       = {0};
+    // char pd[9]         = {0};
+    // char port[6]       = {0};
+    // char user01[8]     = {0};
+    // char password[16]  = {0};
+
+    if(strstr(data,"AT+PTMOD=ON\r\n")){ // 产测开始指令
+        g_ptTest.bTestStart = PT_ON;
+        pt_return_handle(uartid,"+PTMOD:ON,00000001\r\n");
+        timeout_setValue(&g_ptTest.tt_pt_time,PT_TIME,1);//打开产测定时
+    }
+    else if(strstr(data,"AT+PTMOD=OFF\r\n"))//关闭产测指令
+    {
+        g_ptTest.bTestStart = PT_OFF;
+        pt_return_handle(uartid,"+PTMOD:OFF,00000001\r\n");
+        timeout_stop(&g_ptTest.tt_pt_time);//关闭产测定时
+		delay_ms(100);
+		SYS_SoftwareReset();
+    }
+    else if(strstr(data,"AT+PTMOD\r\n"))
+    {// 查询当前是否在产测模式下 产测版本
+        if(g_ptTest.bTestStart==PT_ON)
+        {
+			pt_return_handle(uartid,"+PTMOD:ON,00000001\r\n");
+        }
+        else
+        {
+			pt_return_handle(uartid,"+PTMOD:OFF,00000001\r\n");
+        }
+    }
+    if(g_ptTest.bTestStart == PT_ON)//打开产测后
+    {
+        if(strstr(data,"AT+INITDEVINFO=WBJW,"))// 初始化信息 设备类型 sn 批次号  生产厂商 生产日期
+        {
+            p_data = strstr(data,"AT+INITDEVINFO=WBJW,");
+            if(!strstr(p_data,"\r\n"))
+            {
+                // sscanf(p_data,"AT+INITDEVINFO=WBJW,%[^\r\n]\r\n",tempbuff);
+                // sscanf((char*)tempbuff,"%[^,],%[^,],%[^,],%[^,],%[^,],%[^,],%[^,],%[^,],%s",type,ssn,pcbVr,bn,mfrs,pd,tempbuff,port,sendbuff);
+                return;
+            }
+            p_str = strstr(p_data,"W,");
+
+            at_get_words(',',p_str+2,pbuf,10);
+            device_type     = strtohex(pbuf[0],4);
+            device_sn       = atoi(pbuf[1]);
+            pcb_ver         = strtohex(pbuf[2],2);
+            batch_number    = strtohex(pbuf[3],4);
+            manufactures    = strtohex(pbuf[4],4);
+            production_data = strtohex(pbuf[5],8);
+			// sscanf(type,"%04X",&device_type); // 设备类型
+			// sscanf(ssn,"%010u",&device_sn);  //sn
+			// sscanf(pcbVr,"%02X",&pcb_ver);     //PCB版本
+			// sscanf(bn,"%04X",&batch_number); //批次号
+			// sscanf(mfrs,"%04X",&manufactures); //生产厂商
+			// sscanf(pd,"%08X",&production_data); // 生产日期
+			if(device_type != ((SOFTWARE_VERSION_APP>>16)&0x0000ffff))
+			{
+				pt_return_handle(uartid,"+INITDEVINFO:ERR,Device_mismatch00\r\n");
+                return;
+			}
+
+            device_info.eeprom_first_flag = EEPROM_FIRST_INIT_FLAG;
+            device_info.eeprom_ver        = EEPROM_VER;
+            device_info.config_flag       = DEVICE_ALRD;
+            device_info.device_type       = device_type;
+            device_info.device_sn         = device_sn;
+            device_info.batch_number      = batch_number;
+            device_info.manufactures      = manufactures;
+            device_info.production_data   = production_data;
+            device_info.pcb_ver           = pcb_ver;
+            device_info_update();//写eeprom
+
+            strcpy(mqttidport.ip,pbuf[6]);
+            strcpy(mqttidport.port,pbuf[7]);
+            strcpy(mqttidport.admin,pbuf[8]);
+            strcpy(mqttidport.password,pbuf[9]);
+            mqttidport.flag = 1;
+            mqtt_info_update();
+
+            //存储pt版本
+            device_version_info.PT_ver = SOFTWARE_VERSION_APP;
+		    //存储到eeprom中
+		    at24cxx_write(DEVICE_VERSION_INFO_ADDR+4,(uint8_t *)&device_version_info.PT_ver,4);
+
+			pt_return_handle(uartid,"+INITDEVINFO:OK\r\n");
+        }
+        else if(strstr(data,"AT+DEVINFO\r\n")) // 读取信息
+        {
+            device_info_get();//读取eeprom中的设备信息
+            mqtt_info_read();//读mqtt信息
+            memset(sendbuff,0,sizeof(sendbuff));
+            strcpy(sendbuff,"+DEVINFO:"); // 文件头
+
+            memset(tempbuff,0,sizeof(tempbuff));
+            sprintf(tempbuff,"%04x,%010u,%02x,%04x,",device_info.device_type,\
+                            device_info.device_sn,\
+                            device_info.pcb_ver,device_fixed_info.MCU_Type_ID);
+            strcat(sendbuff,tempbuff);
+
+            memset(tempbuff,0,sizeof(tempbuff));
+            gw_net_send_02((char*)device_fixed_info.MCU_UUID,12,&len2);
+            memcpy(tempbuff,Send_Buf_Char,len2);
+            strcat(sendbuff,tempbuff);
+            strcat(sendbuff,",");
+
+            memset(tempbuff,0,sizeof(tempbuff));
+            sprintf(tempbuff,"%s,%08x,%08x,%04x,%04x,%08x,","", device_fixed_info.Soft_ver_boot,\
+                            device_fixed_info.Soft_ver_app,device_info.batch_number,\
+                            device_info.manufactures,device_info.production_data);
+            strcat(sendbuff,tempbuff);
+
+            memset(tempbuff,0,sizeof(tempbuff));
+            sprintf(tempbuff,"%s,%s,%s,%s",mqttidport.ip,mqttidport.port,mqttidport.admin,mqttidport.password);
+            strcat(sendbuff,tempbuff);
+
+            len1 = strlen(sendbuff);
+
+            sendbuff[len1] = 0x0D;
+            sendbuff[len1+1] = 0x0A;
+
+            pt_return_handle(uartid,sendbuff);
+
+        }
+        else if(strstr(data,"AT+EEPROMERASE=")){ // 擦除EEPROM
+            p_data = strstr(data,"AT+EEPROMERASE=");
+            if(strstr(p_data,"\r\n")){
+                memset(type,0,sizeof(type));
+//                 sscanf(p_data,"AT+EEPROMERASE=%[^\r\n]\r\n",type);
+//                 sscanf(type,"%04X",&device_type); // 设备类型
+                p_str = strstr(p_data,"=");
+                at_get_words(',',p_str+1,pbuf,1);
+                device_type = strtohex(pbuf[0],4);
+                if(device_type!=((SOFTWARE_VERSION_APP>>16)&0x0000ffff)){
+                    pt_return_handle(uartid,"+EEPROMERASE:ERR,Device_mismatch01\r\n");
+                    memset(data,0,len);
+					return;
+                }
+                eeprom_earse();
+                pt_return_handle(uartid,"+EEPROMERASE:OK\r\n");
+            }
+        }
+        else if(strstr((char*)data,"AT+EEPROMWR=")) { // EEPROM 写
+            p_data = strstr((char*)data,"AT+EEPROMWR=");
+            if(strstr(p_data,"\r\n")){
+                memset(tempbuff,0,sizeof(tempbuff));
+//                 sscanf(p_data,"AT+EEPROMWR=%[^\r\n]\r\n",tempbuff);
+//                 sscanf(tempbuff,"%[^,],%[^,],%[^,],%[^,]",bn,type,mfrs,tempbuff);
+//                 sscanf(type,"%04x",&addr);  //地址
+//                 sscanf(mfrs,"%04x",&len11); // 长度
+//                 sscanf(bn,"%04X",&device_type); // 设备类型
+                p_str = strstr(p_data,"=");
+                at_get_words(',',p_str+1,pbuf,4);
+                device_type = strtohex(pbuf[0],4);
+                addr = strtohex(pbuf[1],4);
+                len11 = strtohex(pbuf[2],4);
+                if(device_type!=((SOFTWARE_VERSION_APP>>16)&0x0000ffff)){
+                    pt_return_handle(uartid,"+EEPROMWR:ERR,Device_mismatch\r\n");
+                    return;
+                }
+                len1 = asciitohex(pbuf[3],sendbuff,strlen(pbuf[3]));
+                if(len1 == len11)
+                {
+                    at24cxx_write(addr,(uint8_t*)sendbuff,len11);
+                    pt_return_handle(uartid,"+EEPROMWR:OK\r\n");
+                }
+                else
+                {
+                    pt_return_handle(uartid,"+EEPROMWR:ERR\r\n");
+                }
+            }
+        }
+        else if(strstr((char*)data,"AT+EEPROMRD=")){ // EEPROM 读取
+            p_data = strstr((char*)data,"AT+EEPROMRD=");
+            if(strstr(p_data,"\r\n")){
+                memset(tempbuff,0,sizeof(tempbuff));
+//                 sscanf(p_data,"AT+EEPROMRD=%[^\r\n]\r\n",tempbuff);
+//                 sscanf(tempbuff,"%[^,],%[^,]",type,mfrs);
+//                 sscanf(type,"%04x",&addr);  //地址
+//                 sscanf(mfrs,"%04x",&len11); //长度
+                p_str = strstr(p_data,"=");
+                at_get_words(',',p_str+1,pbuf,2);
+                addr = strtohex(pbuf[0],4);
+                len11 = strtohex(pbuf[1],4);
+
+                at24cxx_read(addr,(uint8_t *)tempbuff,len11);
+
+                memset(Send_Buf_Char,0,sizeof(Send_Buf_Char));
+                gw_net_send_02((char*)tempbuff,len11,&len2);
+
+                memset(sendbuff,0,sizeof(sendbuff));
+                strcpy(sendbuff,"+EEPROMRD:"); // 文件头
+
+                memset(tempbuff,0,sizeof(tempbuff));
+                sprintf(tempbuff,"%04x,%04x,",addr,len11);
+                strcat(sendbuff,tempbuff);
+
+                strcat(sendbuff,Send_Buf_Char);
+
+                len1 = strlen(sendbuff);
+                sendbuff[len1] = 0x0D;
+                sendbuff[len1+1] = 0x0A;
+                pt_return_handle(uartid,sendbuff);
+            }
+        }
+        else if(strstr(data,"AT+INITLORAPARAINDEX=WBJW,")) //写LoRa参数当前组索引号
+        {
+            p_data=strstr(data,"AT+INITLORAPARAINDEX=WBJW,");
+            if(strstr(p_data,"\r\n"))
+            {
+//                 sscanf(p_data,"AT+INITLORAPARAINDEX=WBJW,%[^\r\n]\r\n",tempbuff);
+//                 sscanf(tempbuff,"%[^,]",type);
+//                 sscanf(type,"%u",&device_type); //lora索引
+                p_str = strstr(p_data,"W,");
+                at_get_words(',',p_str+2,pbuf,1);
+                device_type = atoi(pbuf[0]);
+                if(device_type < LORA_GROUP_NUM)//正确
+                {
+                    type[0] = device_type;
+                    type[1] = ~type[0];
+                    at24cxx_write(LORA_ADDR,(uint8_t *)type,2);
+
+					pt_return_handle(uartid,"+INITLORAPARAINDEX:OK\r\n");
+                }
+                else
+                {
+					pt_return_handle(uartid,"+INITLORAPARAINDEX:ERR\r\n");
+                }
+            }
+        }
+        else if(strstr(data,"AT+LORAPARAINDEX\r\n")) //读LoRa参数当前组索引号
+        {
+            memset(sendbuff,0,sizeof(sendbuff));
+            strcpy(sendbuff,"+LORAPARAINDEX:"); // 文件头
+
+            at24cxx_read(LORA_ADDR,(uint8_t *)type,2);
+
+            memset(tempbuff,0,sizeof(tempbuff));
+            sprintf(tempbuff,"%u",type[0]);
+            strcat(sendbuff,tempbuff);
+
+            len2 = strlen(sendbuff);
+            sendbuff[len2] = 0x0D;
+            sendbuff[len2+1] = 0x0A;
+            pt_return_handle(uartid,sendbuff);
+        }
+        else if(strstr(data,"AT+ENCRYPT\r\n")) //读连接器加密状态
+        {
+            memset(sendbuff,0,sizeof(sendbuff));
+            strcpy(sendbuff,"+ENCRYPT:"); // 文件头
+
+            memset(tempbuff,0,sizeof(tempbuff));
+            sprintf(tempbuff,"%u",device_fixed_info.Encrypt);
+            strcat(sendbuff,tempbuff);
+
+            len2 = strlen(sendbuff);
+            sendbuff[len2] = 0x0D;
+            sendbuff[len2+1] = 0x0A;
+            pt_return_handle(uartid,sendbuff);
+        }
+        else if(strstr((char*)data,"AT+MQTTWR=WBJW,")) { // MQTT信息写入
+            // p_data = strstr((char*)data,"AT+MQTTWR=WBJW,");
+            // if(strstr(p_data,"\r\n")){
+            //     memset(tempbuff,0,sizeof(tempbuff));
+            //     memset(port,0,sizeof(port));
+            //     memset(user01,0,sizeof(user01));
+            //     memset(password,0,sizeof(password));
+            //     sscanf(p_data,"AT+MQTTWR=WBJW,%[^,],%[^,],%[^,],%s",tempbuff,port,user01,password);
+            //     fram_init_mqtt_msg();
+            //     sscanf(tempbuff,"%s",g_firmwareMsg.mqttidport.ip); // mqtt 服务器地址
+            //     sscanf(port,"%s",g_firmwareMsg.mqttidport.port); //mqtt 端口号
+            //     sscanf(user01,"%s",g_firmwareMsg.mqttidport.admin);
+            //     sscanf(password,"%s",g_firmwareMsg.mqttidport.password);
+            //     g_firmwareMsg.mqttidport.flag = 1;
+            //     fram_write_mqtt_msg();
+            //     pt_return_handle(uartid,"+MQTTWR:OK\r\n");
+            // }
+        }
+        else if(strstr((char*)data,"AT+MQTTRD\r\n")) { // mqtt 信息读取
+            // p_data = strstr((char*)data,"AT+MQTTRD\r\n");
+            // fram_read_mqtt_msg();
+            // memset(sendbuff,0,sizeof(sendbuff));
+            // strcpy(sendbuff,"+MQTTRD:"); // 文件头
+
+            // memset(tempbuff,0,sizeof(tempbuff));
+            // sprintf(tempbuff,"%s,%s,%s,%s",g_firmwareMsg.mqttidport.ip,g_firmwareMsg.mqttidport.port, \
+            //                         g_firmwareMsg.mqttidport.admin,g_firmwareMsg.mqttidport.password);
+
+            // strcat(sendbuff,tempbuff);
+            // len1 = strlen(sendbuff);
+            // sendbuff[len1] = 0x0D;
+            // sendbuff[len1+1] = 0x0A;
+
+            // pt_return_handle(uartid,sendbuff);
+        }
+        else if(strstr((char*)data,"AT+RST\r\n")) { //复位
+            pt_return_handle(uartid,"+RST:OK\r\n");
+            delay_ms(100);//延时100ms
+            SYS_SoftwareReset();//复位
+        }
+	}
+}
+#endif
+
+
+uint8_t PT_RCVBuf[256];
+uint16_t PT_RCVLen;
+//产测处理
+void pt_cmd_task(void)
+{
+    rcv_size = uart_blocking_read(rcv_buf,UART2_ID);
+    if(rcv_size)
+    {
+        uart_cmd_task(UART2_ID,rcv_buf,rcv_size);
+    }
+	if(timeout_isOut(&g_ptTest.tt_pt_time))
+	{
+		SYS_SoftwareReset();
+	}
+}

src/uart_pt.h

@@ -0,0 +1,27 @@
+#ifndef UART_PT_H__
+#define UART_PT_H__
+#include "board.h"
+#include "timeout.h"
+
+#define PT_ON     1
+#define PT_OFF    0
+
+#define PT_TIME (10*60*1000)//产测超时时间，连续这么长时间未收到产测指令，关闭产测
+
+
+
+
+
+
+
+
+
+typedef struct _PT_TEST_{
+    uint8_t bTestStart; // 产测开始
+	timeout_t tt_pt_time;
+}PtTest;
+extern PtTest g_ptTest;
+void uart_cmd_task(uint8_t uartid, char *data, uint16_t len);
+void pt_cmd_task(void);
+
+#endif // !