[setup]
boards_dir = boards
board = agrv2k_407
board_logic.ve = boot.ve
#board_logic.compress = true

#ips_dir = ../ips
ip_name = boot_ip
logic_dir = logic
; logic_ve = top.ve

framework = agrv_sdk
program = 0104_boot_mcu_003

src_dir = src
include_dir = src
src_filter = "-<*> +<*.c>+<master/user/app/*.c>+<master/user/db/*.c>+<master/user/inc/*.c>+<master/user/lib/*.c>+<master/user/lzma/*.c>+<master/components/atomlib/*.c>+<master/components/ringBuffer/*.c>"
src_build_flags = -Isrc -Isrc/master/user/app -Isrc/master/user/db -Isrc/master/user/inc -Isrc/master/user/lib -Isrc/master/user/lzma -Isrc/master/components/atomlib -Isrc/master/components/ringBuffer

lwip_imp_dir =
tinyusb_imp_dir =
#lwip_param = freertos
#tinyusb_param =

#board_build.boot_addr = upload
#board_build.boot_mode = sram
#board_upload.address = 0x20000000
#board_upload.logic_address = 0x80020000
#board_logic.device = AGRV2KL100
#board_logic.ve = my_board.ve
board_upload.address = 0x80000000

board_logic.compress = true

board_build.boot_addr = upload
board_build.boot_mode = flash_sram

logger_if = UART0
#upload_port = /dev/ttyUSB0
#monitor_port = /dev/ttyUSB0
upload_port = COM3
monitor_port = COM3
monitor_speed = 57600
debug_speed = 10000

debug_tool = jlink-openocd
upload_protocol = jlink-openocd

build_unflags = -O2
build_flags = -Os
              -DLOGGER_BAUD_RATE=${setup.monitor_speed}
              -DAGRV_FP_STACK=0
              -DDFU_FPGA_CONFIG=\"fpga_boot.inc\"

build_src_flags = -Wno-cast-align



[setup_rtt]
logger_if = RTT
monitor_port = socket://localhost:19021


[platformio]
boards_dir = ${setup.boards_dir}
src_dir = ${setup.src_dir}
include_dir = ${setup.include_dir}
default_envs = dev

[env]
platform = AgRV
extends = setup

[env:dev]
build_type = debug

[env:release]
build_type = release

[env:rtt]
build_type = debug
extends = setup_rtt

[env:serial]
build_type = release
upload_protocol = serial
upload_speed = 460800
custom_speed = 115200