Etusivu Tutki Apua
Kirjaudu sisään
P_0104
/
0104_APP
2
0
Fork 0
Tiedostot Ongelmat 0 Pull-pyynnöt 0 Wiki
Puu: 4f86d1fca6
Branchit Tagit
0104_APP
/
logic
/
APP_0104.qsf

APP_0104.qsf 7.1 KB
Historia Raaka

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141 
  1. # Design name Assignments, replace __design_name__ with actual design name
    2. 

  2. # ========================
    3. 

  3. set_global_assignment -name FAMILY "Cyclone IV E"
    4. 

  4. set_global_assignment -name DEVICE EP4CE75F29C8
    5. 

  5. 

  6. set_global_assignment -name TOP_LEVEL_ENTITY "top"
    7. 

  7. 

  8. set_global_assignment -name VERILOG_FILE APP_0104.v
    9. 

  9. set_global_assignment -name VERILOG_FILE APP_0104_fpga.v
    10. 

  10. set_global_assignment -name VERILOG_FILE "C:\\Users\\61552\\.platformio\\packages\\tool-agrv_logic\\etc\\arch\\rodinia\\alta_sim.v"
    11. 

  11. 

  12. set_global_assignment -name SDC_FILE .\\APP_0104.sdc
    13. 

  13. 

  14. 

  15. #set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_FILE "atom_netlists/__design_name__.vqm"
    16. 

  16. 

  17. # Project-Wide Assignments
    18. 

  18. # ========================
    19. 

  19. set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.1
    20. 

  20. set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:37:04  JANUARY 04, 2013"
    21. 

  21. set_global_assignment -name LAST_QUARTUS_VERSION 15.0.0
    22. 

  22. set_global_assignment -name PROJECT_OUTPUT_DIRECTORY ./quartus_logs
    23. 

  23. set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
    24. 

  24. set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
    25. 

  25. #set_global_assignment -name SMART_RECOMPILE ON
    26. 

  26. 

  27. # Classic Timing Assignments
    28. 

  28. # ==========================
    29. 

  29. set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
    30. 

  30. set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
    31. 

  31. 

  32. # Analysis & Synthesis Assignments
    33. 

  33. # ================================
    34. 

  34. set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
    35. 

  35. set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
    36. 

  36. #set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
    37. 

  37. #set_global_assignment -name AUTO_ROM_RECOGNITION OFF
    38. 

  38. #set_global_assignment -name AUTO_RAM_RECOGNITION OFF
    39. 

  39. #set_global_assignment -name MAX_RAM_BLOCKS_M4K 0
    40. 

  40. set_global_assignment -name AUTO_OPEN_DRAIN_PINS OFF
    41. 

  41. # set_instance_assignment -name PRESERVE_REGISTER ON -to *
    42. 

  42. #set_instance_assignment -name PRESERVE_PLL_COUNTER_ORDER ON -to *
    43. 

  43. #set_instance_assignment -name MAX_NUMBER_OF_REGISTERS_FROM_UNINFERRED_RAMS 0 -to *
    44. 

  44. 

  45. # Fitter Assignments
    46. 

  46. # ==================
    47. 

  47. set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
    48. 

  48. set_global_assignment -name ROUTING_BACK_ANNOTATION_MODE OFF
    49. 

  49. set_global_assignment -name OPTIMIZE_HOLD_TIMING "IO PATHS AND MINIMUM TPD PATHS"
    50. 

  50. set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
    51. 

  51. set_global_assignment -name ROUTER_TIMING_OPTIMIZATION_LEVEL MAXIMUM
    52. 

  52. set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 10
    53. 

  53. set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 10
    54. 

  54. set_global_assignment -name ECO_OPTIMIZE_TIMING ON
    55. 

  55. set_global_assignment -name FINAL_PLACEMENT_OPTIMIZATION ALWAYS
    56. 

  56. set_global_assignment -name FITTER_AGGRESSIVE_ROUTABILITY_OPTIMIZATION ALWAYS
    57. 

  57. set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
    58. 

  58. set_global_assignment -name IO_PLACEMENT_OPTIMIZATION ON
    59. 

  59. set_global_assignment -name SEED 1
    60. 

  60. set_global_assignment -name FIT_ONLY_ONE_ATTEMPT OFF
    61. 

  61. set_global_assignment -name MAX_GLOBAL_CLOCKS_ALLOWED 6
    62. 

  62. set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
    63. 

  63. #set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
    64. 

  64. #set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
    65. 

  65. set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
    66. 

  66. set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
    67. 

  67. 

  68. # EDA Netlist Writer Assignments
    69. 

  69. # ==============================
    70. 

  70. set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim (Verilog)"
    71. 

  71. 

  72. # LogicLock Region Assignments
    73. 

  73. # ============================
    74. 

  74. set_global_assignment -name LOGICLOCK_INCREMENTAL_COMPILE_ASSIGNMENT OFF
    75. 

  75. 

  76. # Power Estimation Assignments
    77. 

  77. # ============================
    78. 

  78. set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
    79. 

  79. set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
    80. 

  80. 

  81. # start EDA_TOOL_SETTINGS(eda_simulation)
    82. 

  82. # ---------------------------------------
    83. 

  83. 

  84. # EDA Netlist Writer Assignments
    85. 

  85. # ==============================
    86. 

  86. set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation
    87. 

  87. set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation
    88. 

  88. 

  89. # end EDA_TOOL_SETTINGS(eda_simulation)
    90. 

  90. # -------------------------------------
    91. 

  91. 

  92. # start DESIGN_PARTITION(Top)
    93. 

  93. # ---------------------------
    94. 

  94. 

  95. # Incremental Compilation Assignments
    96. 

  96. # ===================================
    97. 

  97. set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
    98. 

  98. set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
    99. 

  99. set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
    100. 

  100. set_global_assignment -name FLOW_DISABLE_ASSEMBLER ON
    101. 

  101. 

  102. # end DESIGN_PARTITION(Top)
    103. 

  103. # -------------------------
    104. 

  104. 

  105. set_global_assignment -name LL_ENABLED ON -section_id core_logic
    106. 

  106. set_global_assignment -name LL_AUTO_SIZE OFF -section_id core_logic
    107. 

  107. set_global_assignment -name LL_STATE LOCKED -section_id core_logic
    108. 

  108. set_global_assignment -name LL_RESERVED OFF -section_id core_logic
    109. 

  109. set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id core_logic
    110. 

  110. set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id core_logic
    111. 

  111. set_global_assignment -name LL_PR_REGION OFF -section_id core_logic
    112. 

  112. set_global_assignment -name LL_WIDTH 20 -section_id core_logic
    113. 

  113. set_global_assignment -name LL_HEIGHT 12 -section_id core_logic
    114. 

  114. set_global_assignment -name LL_ORIGIN X43_Y1 -section_id core_logic
    115. 

  115. set_global_assignment -name LL_MEMBER_OF core_logic -section_id core_logic
    116. 

  116. 

  117. set_global_assignment -name LL_ENABLED ON -section_id LOGIC_RESERVE_0
    118. 

  118. set_global_assignment -name LL_AUTO_SIZE OFF -section_id LOGIC_RESERVE_0
    119. 

  119. set_global_assignment -name LL_STATE LOCKED -section_id LOGIC_RESERVE_0
    120. 

  120. set_global_assignment -name LL_RESERVED ON -section_id LOGIC_RESERVE_0
    121. 

  121. set_global_assignment -name LL_SECURITY_ROUTING_INTERFACE OFF -section_id LOGIC_RESERVE_0
    122. 

  122. set_global_assignment -name LL_IGNORE_IO_BANK_SECURITY_CONSTRAINT OFF -section_id LOGIC_RESERVE_0
    123. 

  123. set_global_assignment -name LL_PR_REGION OFF -section_id LOGIC_RESERVE_0
    124. 

  124. set_global_assignment -name LL_WIDTH 13 -section_id LOGIC_RESERVE_0
    125. 

  125. set_global_assignment -name LL_HEIGHT 8 -section_id LOGIC_RESERVE_0
    126. 

  126. set_global_assignment -name LL_ORIGIN X43_Y5 -section_id LOGIC_RESERVE_0
    127. 

  127. 

  128. set_global_assignment -name MAX_BALANCING_DSP_BLOCKS 0
    129. 

  129. set_global_assignment -name MAX_RAM_BLOCKS_M4K 4
    130. 

  130. 

  131. 

  132. set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY PARTITION_ONLY -section_id eda_simulation
    133. 

  133. set_global_assignment -name LL_CORE_ONLY OFF -section_id LOGIC_RESERVE_0
    134. 

  134. set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id LOGIC_RESERVE_0
    135. 

  135. set_global_assignment -name LL_CORE_ONLY OFF -section_id core_logic
    136. 

  136. set_global_assignment -name LL_ROUTING_REGION_EXPANSION_SIZE 2147483647 -section_id core_logic
    137. 

  137. set_global_assignment -name PARTITION_COLOR 52377 -section_id rv32 -tag alta_auto
    138. 

  138. set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id rv32 -tag alta_auto
    139. 

  139. set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id rv32 -tag alta_auto
    140. 

  140. set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
    141. 

  141. set_instance_assignment -name PARTITION_HIERARCHY rv32 -to "alta_rv32:rv32" -section_id rv32
    142.